JPH0678231A - Satellite broadcast receiver - Google Patents
Satellite broadcast receiverInfo
- Publication number
- JPH0678231A JPH0678231A JP4227532A JP22753292A JPH0678231A JP H0678231 A JPH0678231 A JP H0678231A JP 4227532 A JP4227532 A JP 4227532A JP 22753292 A JP22753292 A JP 22753292A JP H0678231 A JPH0678231 A JP H0678231A
- Authority
- JP
- Japan
- Prior art keywords
- satellite broadcast
- broadcast receiver
- signal processing
- clock
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 claims 1
- 230000005855 radiation Effects 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 5
- 230000006378 damage Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
- Noise Elimination (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、衛星放送受信機に関
し、特にテレビ内蔵型やビデオ内蔵型の衛星放送受信機
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a satellite broadcast receiver, and more particularly to a built-in television or video built-in satellite broadcast receiver.
【０００２】[0002]
【従来の技術】図４は、テレビやビデオに内蔵されてい
る従来の衛星放送受信機の例であり、衛星放送データを
受信して出力バッファ２３へ処理出力を与える衛星放送
信号処理部２２と、外部コントローラ２８からの制御信
号を衛星放送信号処理部２２に与えるインタフェース２
４と、衛星放送信号処理部２２にクロックを供給する分
周回路２５とを有している。2. Description of the Related Art FIG. 4 shows an example of a conventional satellite broadcast receiver incorporated in a television or a video, and a satellite broadcast signal processing section 22 for receiving satellite broadcast data and giving a processing output to an output buffer 23. , Interface 2 for giving a control signal from the external controller 28 to the satellite broadcast signal processing unit 22
4 and a frequency dividing circuit 25 that supplies a clock to the satellite broadcast signal processing unit 22.
【０００３】このような衛星放送受信機を内蔵している
テレビやビデオでは、衛星放送受信機２１で発生する不
要輻射がテレビやビデオの信号に影響を与えることを避
けるため、衛星放送受信機２１を使用しない時には、不
要輻射の主原因である高周波で動作する出力バッファ２
３を停止させるために、ユーザーからの選択信号を受け
て、衛星放送受信機２１やテレビまたはビデオの信号処
理部２７などを制御する信号を出力するコントローラ２
８の制御信号２８ｂによって、衛星放送受信機の電源ス
イッチ３０を切断している。In a television or video having such a satellite broadcast receiver built-in, in order to avoid unnecessary radiation generated in the satellite broadcast receiver 21 from affecting the signals of the television or video, the satellite broadcast receiver 21 is used. Output buffer 2 operating at high frequency, which is the main cause of unwanted radiation when not used
In order to stop 3, the controller 2 which receives a selection signal from the user and outputs a signal for controlling the satellite broadcast receiver 21, the television or video signal processing unit 27, and the like.
The control signal 28b of 8 disconnects the power switch 30 of the satellite broadcast receiver.
【０００４】[0004]
【発明が解決しようとする課題】この従来のテレビ内蔵
型やビデオ内蔵型の衛星放送受信機では、不要輻射の影
響を少なくするために衛星放送受信機専用の電源スイッ
チと、専用のコントロール系が必要であった。In this conventional satellite broadcast receiver with a built-in television or a video, a power switch dedicated to the satellite broadcast receiver and a dedicated control system are provided in order to reduce the influence of unwanted radiation. Was needed.
【０００５】また衛星放送受信機のみの電源の投入／切
断を行うため、テレビ本体またはビデオ本体との信号の
インタフェースにおいて、電源の投入，切断時に衛星放
送受信機側または、テレビ本体，ビデオ本体側に使用さ
れている半導体素子がラッチ・アップする危険性があ
り、これを防止するため、信号ラインに抵抗を挿入する
などの対策が必要であった。Further, in order to turn on / off the power of only the satellite broadcast receiver, in the signal interface with the television main body or the video main body, when the power is turned on / off, the satellite broadcast receiver side or the television main body or the video main body side There is a risk that the semiconductor element used in the above may latch up, and in order to prevent this, it is necessary to take measures such as inserting a resistor in the signal line.
【０００６】本発明の目的は、不要輻射をなくした衛星
放送受信機を提供することにある。An object of the present invention is to provide a satellite broadcast receiver that eliminates unnecessary radiation.
【０００７】[0007]
【課題を解決するための手段】前記目的を達成するた
め、本発明に係る衛星放送受信機は、衛星放送信号処理
部と、インタフェースと、分周回路と、ゲートとを有す
る衛星放送受信機であって、衛星放送信号処理部は、衛
星放送データを受信し、出力バッファへ処理出力を与え
るものであり、インタフェースは、外部コントローラか
らの制御信号を衛星放送信号処理部に与えるものであ
り、分周回路は、衛星放送信号処理部にクロックを供給
するものであり、ゲートは、インタフェースからの制御
信号により分周回路へのクロックの供給または停止を制
御するものである。ものである。In order to achieve the above object, a satellite broadcast receiver according to the present invention is a satellite broadcast receiver having a satellite broadcast signal processing section, an interface, a frequency dividing circuit, and a gate. Therefore, the satellite broadcast signal processing unit receives the satellite broadcast data and provides a processing output to the output buffer, and the interface provides a control signal from the external controller to the satellite broadcast signal processing unit. The frequency circuit supplies a clock to the satellite broadcast signal processing unit, and the gate controls the supply or stop of the clock to the frequency dividing circuit according to a control signal from the interface. It is a thing.
【０００８】[0008]
【作用】衛星放送信号処理部２へクロックを供給してい
る分周回路５の動作／停止をゲート６で制御することに
よって、出力バッファ３の動作／停止を可能にする。The gate 6 controls the operation / stop of the frequency dividing circuit 5 which supplies the clock to the satellite broadcast signal processing unit 2, thereby enabling the operation / stop of the output buffer 3.
【０００９】[0009]
【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.
【００１０】（実施例１）図１は、本発明の実施例１を
示すブロック図である。(First Embodiment) FIG. 1 is a block diagram showing a first embodiment of the present invention.
【００１１】図１において、本発明の衛星放送受信機１
は、衛星放送データを受信して出力バッファ３へ処理出
力を与える衛星放送信号処理部２と、外部コントローラ
８からの制御信号を衛星放送信号処理部２へ与えるイン
タフェース４と、衛星放送信号処理部２にクロックを供
給する分周回路５と、インタフェース４からの制御信号
によって分周回路５へのクロックの供給／停止を制御す
る論理積ゲート６とを備えている。Referring to FIG. 1, a satellite broadcast receiver 1 according to the present invention.
Is a satellite broadcast signal processing unit 2 that receives satellite broadcast data and provides a processing output to the output buffer 3, an interface 4 that provides a control signal from the external controller 8 to the satellite broadcast signal processing unit 2, and a satellite broadcast signal processing unit. A frequency divider circuit 5 for supplying a clock to the frequency divider 2 and an AND gate 6 for controlling the supply / stop of the clock to the frequency divider circuit 5 by a control signal from the interface 4.
【００１２】テレビまたはビデオに内蔵された場合の本
発明の動作を図１及び図２を参照して説明する。ここで
図１の７はテレビまたはビデオの信号処理部及び出力回
路であり、テレビやビデオの入力データと、衛星放送受
信機１の出力データを受けて、いずれかの処理結果を出
力する。８は、ユーザーからの選択信号を受けて衛星放
送受信機１やテレビまたはビデオの信号処理部７を制御
する信号を出力するコントローラである。The operation of the present invention when incorporated in a television or video will be described with reference to FIGS. 1 and 2. Reference numeral 7 in FIG. 1 denotes a television or video signal processing unit and an output circuit, which receives television or video input data and output data of the satellite broadcast receiver 1 and outputs one of the processing results. A controller 8 receives a selection signal from a user and outputs a signal for controlling the satellite broadcast receiver 1 and the television or video signal processing unit 7.
【００１３】コントローラ８によって衛星放送受信機が
選択されている場合、ゲート６には、図２の区間Ａのク
ロックと、コントローラ８からの選択信号を受けてイン
タフェース４が出力するクロック供給信号４ｂとが入力
される。この時の分周回路５と出力バッファ３の出力
が、区間Ａのようになるとする。When the satellite broadcast receiver is selected by the controller 8, the gate 6 receives the clock in the section A of FIG. 2 and the clock supply signal 4b output by the interface 4 in response to the selection signal from the controller 8. Is entered. It is assumed that the outputs of the frequency dividing circuit 5 and the output buffer 3 at this time are as in the section A.
【００１４】次にコントローラ８より非選択信号がイン
タフェース４に入力されたとすると、インタフェース４
はゲート６へ図２の区間Ｂの４ｂのような信号を出力す
るので、ゲート６は分周回路５へのクロックの供給を停
止する。Next, assuming that a non-selection signal is input to the interface 4 from the controller 8, the interface 4
Outputs a signal such as 4b in the section B of FIG. 2 to the gate 6, so that the gate 6 stops the supply of the clock to the frequency dividing circuit 5.
【００１５】入力クロックが停止した分周回路５では、
衛星放送信号処理部２へ供給するクロックである分周出
力が停止する。このため、衛星放送信号処理部２が停止
し、したがって出力バッファ３も停止する。これによ
り、電源に接続されたままで、衛星放送受信機の出力バ
ッファ３を停止することができるようになる。In the frequency dividing circuit 5 in which the input clock is stopped,
The frequency division output which is the clock supplied to the satellite broadcast signal processing unit 2 is stopped. Therefore, the satellite broadcast signal processing unit 2 stops, and thus the output buffer 3 also stops. This allows the output buffer 3 of the satellite broadcast receiver to be stopped while still connected to the power supply.
【００１６】（実施例２）図３は、本発明の実施例２を
示すブロック図である。本実施例は、図１のゲート６に
よってクロックの供給／停止を制御するかわりに、イン
タフェース４の制御信号で分周回路５を強制的にリセッ
ト状態に保持するようにするものである。(Second Embodiment) FIG. 3 is a block diagram showing a second embodiment of the present invention. In this embodiment, instead of controlling the supply / stop of the clock by the gate 6 of FIG. 1, the frequency divider circuit 5 is forcibly held in the reset state by the control signal of the interface 4.
【００１７】[0017]
【発明の効果】以上説明したように本発明の衛星放送受
信機によれば、衛星放送受信機を内蔵するテレビやビデ
オにおいて、電源の投入／切断の制御をすることなし
に、不要輻射をとめることができるので、衛星放送受信
機専用の電源部品が必要なくなることになる。As described above, according to the satellite broadcast receiver of the present invention, unnecessary radiation is stopped in a television or video having a built-in satellite broadcast receiver without controlling power on / off. Therefore, the power supply component dedicated to the satellite receiver is not necessary.
【００１８】また、電源投入時や切断時の衛星放送受信
機側あるいは、テレビ，ビデオ本体側でのラッチ・アッ
プの危険性がなくなるという効果もある。さらに、電源
切断状態において、衛星放送受信機の入力端子に電圧が
印加され続けた場合に、静電破壊保護用のダイオードに
電流が流れ続けて、素子の劣化及び破壊を招くという危
険性もなくなる。Further, there is an effect that there is no risk of latch-up on the side of the satellite broadcasting receiver or on the side of the television or the video when the power is turned on or off. Further, when the voltage is continuously applied to the input terminal of the satellite broadcasting receiver in the power-off state, the risk that the current continues to flow in the diode for protection against electrostatic discharge, resulting in deterioration and destruction of the element is eliminated. .
【図１】本発明の実施例１を示すブロック図である。FIG. 1 is a block diagram showing a first embodiment of the present invention.
【図２】実施例１のタイミングチャートである。FIG. 2 is a timing chart of the first embodiment.
【図３】本発明の実施例２を示すブロック図である。FIG. 3 is a block diagram showing a second embodiment of the present invention.
【図４】従来の衛星放送受信機を内蔵したテレビまたは
ビデオを示すブロック図である。FIG. 4 is a block diagram showing a television or video having a built-in conventional satellite broadcast receiver.
１，１１，２１ 衛星放送受信機 ２，１２，２２ 衛星放送信号処理部 ３，１３，２３ 出力バッファ ４，１４，２４ インタフェース ５，１５，２５ 分周回路 ６ 論理積ゲート ７，１７，２７ テレビまたはビデオの信号処理部 ８，１８，２８ コントローラ ３０ スイッチ ４ｂ 制御信号 1,11,21 Satellite broadcast receiver 2,12,22 Satellite broadcast signal processing unit 3,13,23 Output buffer 4,14,24 Interface 5,15,25 Dividing circuit 6 Logical product gate 7,17,27 TV Or video signal processing unit 8, 18, 28 controller 30 switch 4b control signal
Claims (1)
と、分周回路と、ゲートとを有する衛星放送受信機であ
って、 衛星放送信号処理部は、衛星放送データを受信し、出力
バッファへ処理出力を与えるものであり、 インタフェースは、外部コントローラからの制御信号を
衛星放送信号処理部に与えるものであり、 分周回路は、衛星放送信号処理部にクロックを供給する
ものであり、 ゲートは、インタフェースからの制御信号により分周回
路へのクロックの供給または停止を制御するものである
ことを特徴とする衛星放送受信機。1. A satellite broadcast receiver having a satellite broadcast signal processing section, an interface, a frequency dividing circuit, and a gate, wherein the satellite broadcast signal processing section receives satellite broadcast data and processes it into an output buffer. The interface provides the control signal from the external controller to the satellite broadcast signal processing unit, the frequency divider circuit supplies the clock to the satellite broadcast signal processing unit, and the gate A satellite broadcast receiver characterized by controlling supply or stop of a clock to a frequency dividing circuit by a control signal from an interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22753292A JP3145800B2 (en) | 1992-08-26 | 1992-08-26 | Satellite receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22753292A JP3145800B2 (en) | 1992-08-26 | 1992-08-26 | Satellite receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0678231A true JPH0678231A (en) | 1994-03-18 |
| JP3145800B2 JP3145800B2 (en) | 2001-03-12 |
Family
ID=16862387
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22753292A Expired - Fee Related JP3145800B2 (en) | 1992-08-26 | 1992-08-26 | Satellite receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3145800B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4184293B1 (en) * | 2021-11-18 | 2025-10-15 | Aplusx Inc. | Glide for a mouse, manufacturing method thereof, and mouse having same |
-
1992
- 1992-08-26 JP JP22753292A patent/JP3145800B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP3145800B2 (en) | 2001-03-12 |
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