JPH0678348A - Changing point detection circuit - Google Patents

Abstract

PURPOSE:To relieve the load of a CPU and to improve the processing capability of the system by monitoring input of plural signals and writing an input terminal number subject to change and its changing direction to a FIFO in the order of priority. CONSTITUTION:Input signal data of n-set are replaced with a cross connect section 3 with priority controlled by a CM section 2. Data multiplexed by a multiplexer section 4 are outputted to a comparison detection section 6 in the order of priority via a replacement circuit 5. When a current value and a preceding value are dissident through the comparison, the result is written in a FIFO 9. Furthermore, the circuit 9 gives the preceding data to the FIFO. An output of a counter 7 is outputted to the FIFO via a table 8 according to the data set by the priority and only when a write signal from the detection section 6 comes, an output of the table 8 and the preceding value from the circuit 5 are written. Then a CPU 10 reads the FIFO to detect which input signal changes in what way according to the priority.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a change point detection circuit,
In particular, the present invention relates to a change point detection circuit that monitors change points with a priority for a plurality of input signals.

[0002]

2. Description of the Related Art Conventionally, this kind of change point detection circuit detects a change point for all of a plurality of input signals,
All the results of change point detection are monitored by the CPU and processed according to the priority order. The priority order is also changed within the CPU and these are processed within a fixed time.

FIG. 2 is a block diagram showing an example of a conventional change point detection circuit. Input signal n of the input terminals 11-1 to 11-n
It is a block diagram showing an example of a change point detection circuit for all the pieces. The change point detectors 12-1 to 12-n are provided for all n input signals from the input terminals 11-1 to 11-n.
Outputs from 1 to n are monitored by all n CPUs 13 and CP
In U13, processing is performed according to the priority order.

[0004]

This conventional change point detection circuit has a change point detection section for all input signals, and the CPU monitors the outputs from all the change point detection sections. However, each time the input signal is changed, the priority order is changed and the processing is performed by the CPU within a fixed time. Therefore, when the change point increases or the cycle of the fixed time is short, the CPU There has been a problem that the load is increased and the signal cannot be processed within a fixed time.

[0005]

SUMMARY OF THE INVENTION A change point detection circuit according to the present invention outputs first signals for exchanging a plurality of input signals in accordance with a set priority and outputting the signals from the first means. Second means for multiplexing and outputting as a multiplexed signal, third means for delaying the signal from the second means for a predetermined time and outputting as a delayed multiplexed signal, and the multiplexed signal and the delayed multiplexed signal do not match. When a fourth means for outputting a write signal, a fifth means for outputting a count value corresponding to the priority, a sixth means for converting the count value according to data, and a write signal are used. It has a seventh means for storing the delayed multiplexed signal and the count value in a FIFO memory, and an eighth means for processing the signal read from the FIFO memory and changing the priority order.

[0006]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention.

In this embodiment, n input terminals 1-1 to 1-n to which n signals are input, and a CPU 1 according to a priority order.
The CM section 2 that controls the cross-connect section 3 by the data set from 0, and the cross-connect section that exchanges the signals from the input terminals 1-1 to 1-n according to the priority order based on the data of the CM section 2. 3, a multiplexer 4 that multiplexes the signal input from the cross-connect unit 3, a delay circuit 5 that delays the signal from the multiplexer 4, an output value from the multiplexer 4 and an output value from the delay circuit 5. And a comparison detection unit 6 that outputs a write signal to the FIFO 9 when they do not match, an m-stage counter 7 that outputs the values 1 to n, and a CPU
Table 8 which has data according to the priority order set from 10 and which converts and outputs the value from the m-stage counter 7 according to the data, and the value from the table 8 and the value from the delay circuit 5 according to the value from the comparison detection unit 6. FIFO9 that stores and
And a CPU 10 for changing the priority order when processing is performed by the data read from the FIFO 9 and the priority order is changed.

Next, the operation of this embodiment will be described.
The n signals input to the input terminals 1-1 to 1-n are exchanged in data by the cross-connect unit 3 controlled by the CM unit 2 which is set by the CPU 10 according to the priority order. The data after the replacement is multiplexed in the multiplexing unit 4, is output to the comparison detection unit 6 in order of priority, and is output to the comparison detection unit 6 via the delay circuit 5. The comparison / detection unit 6 inputs the current value and the previous value for the signals from the respective input terminals, and compares whether or not there is a change in the input signals. If there is a mismatch as a result of comparison, it is output as a write signal to the FIFO. The delay circuit 5 is FI
The data of the previous value is passed to the FIFO 9 as information when the data is changed by being connected to the FO 9. Further, the counter 7 outputs the value corresponding to the terminal number to the table 8 when comparing the respective input terminals 1 to n. In the table 8, the outputs of 1 to n from the counter 7 are output to the FIFO 9 in the order of priority according to the data set by the CPU 10 according to the priority, and only when there is a write signal from the comparison detector 6. The output value from the table 8 and the previous value from the delay circuit are written. And CP
Since it is difficult for U10 to read the FIFO 9, it is detected which input terminal signal has changed according to the priority order. Then, the CPU 10 performs processing according to the detection result, and when changing the priority order, the CM section 2 and the table 8 are set according to the changed priority order and the change point is detected with the new priority order.

In FIG. 3, the data to the input terminals are
It has changed like. In the case of →, the previous value is written as the terminal number in which the data of the input terminals 1, 3, 5 changed from 0 to 1 and the direction of the change. And CPU
Since the FIFO 9 having the highest priority is sequentially read from 10, the change point of the input terminal having the high priority can be known quickly, and the direction of change of the change point can be known from the written value. In case of →, similarly 2 → 5 →
The data is written in the FIFO 9 in the order of 1 and read from the CPU 10. In this way, the FI is set for each state transition of the input data.
The changed terminal and the direction of change are written in the FO 9, and the CPU 10 reads the FIFO 9 to detect the data change point in the order of the priority.

[0010]

As described above, according to the present invention, the change points are monitored in priority order with respect to the input of a plurality of signals, and only the input terminals that have changed have the terminal number and the direction of change in the order of priority in the FIFO. By writing to the CPU, the CPU can detect the change point and the direction of change of each input terminal in descending order of priority by reading the value of the FIFO without monitoring each input terminal. Since priority change and priority processing are performed outside the CPU at the data input part, it is only necessary to make settings once until the priority is changed, improving efficiency. Also, changing and prioritizing the priority outside the CPU Since distributed processing improves the processing capacity of the overall system, processing can be performed even when the number of change points increases or the processing cycle is short. There is an effect.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a change point detection circuit of the present invention.

FIG. 2 is a block diagram showing an example of a conventional change point detection circuit.

FIG. 3 is a diagram showing a write operation to a FIFO of this embodiment.

[Explanation of symbols]

 1-1 to n input terminals 1, 2 ... 2 ... n 12-1 to n Change point detection units 1, 2 ... n

Claims (1)

[Claims] 1. A first means for exchanging a plurality of input signals in accordance with a set priority order and outputting the multiplexed signals, and a second means for multiplexing the signals from the first means and outputting the multiplexed signals. Third means for delaying the signal from the second means for a predetermined time and outputting it as a delayed multiplexed signal; and fourth means for outputting a write signal when the multiplexed signal and the delayed multiplexed signal do not match. The fifth means for outputting the count value corresponding to the priority, the sixth means for converting the count value according to the data, and the write signal
Seventh means for storing the delayed multiplexed signal and the count value in a FIFO memory, and eighth means for processing a signal read from the FIFO memory and changing the priority order.
And a change point detection circuit.