JPH0680682B2 - Device manufacturing method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to methods of manufacturing devices, such as semiconductor devices, and the resulting devices.

2. Technical Background Metal-containing materials, ie pure metals, molecule-type materials in which the molecule contains one or more metal atoms, and / or treated mixtures of one or more of the above. Deposition on untreated substrates plays an important role in the manufacture of various devices. These devices include, for example, discrete semiconductor devices, integrated circuit devices, and magnetic bubble devices. Typically, for example, the deposition of pure metal on selected areas of a treated or untreated semiconductor substrate is performed using a patterned deposition mask, such as
Forming a patterned photoresist layer on the substrate surface,
Subsequent electron beam evaporation or rf-sputtering of the metal on the substrate surface with the mask. Subsequent removal of the mask leaves the metal cover only in the selected substrate area. Alternatively, the metal is deposited directly on the surface of the substrate without forming a deposition mask and a patterned etch mask, eg, a patterned photoresist layer, is formed on the metal.
The metal is then etched through the etch mask and the etch mask is removed, leaving the metal only in the selected areas.

Many integrated circuit devices, the fabrication of which involves deposition of metal-containing materials, include many MOS (metal / oxide semiconductor) integrated circuit devices, such as n-channel MOS, p-channel MOS, and CMOS (complementary MOS). ) Includes integrated circuit devices.
(As used herein, integrated circuit means a plurality of interconnected discrete devices.) These MOS integrated circuits (I
C) typically comprises a plurality of MOSFETs (metal / oxide semiconductor field effect transistors), each MOSFET comprising an active surface layer of semiconductor material, eg silicon. The individual MOSFETs also have a thin gate oxide (GOX) formed on the surface of the active layer, a conductive gate of, for example, doped polycrystalline silicon (polysilicon) formed on the surface of this GOX, Formed on both sides of this gate, MOSF
It includes two heavily doped portions of the active layer that make up the source and drain of the ET. Thick field oxides (FOX) (compared to GOX) serve to isolate and electrically isolate the MOSFETs from each other.

The MOC IC described above includes a metal, eg, aluminum or aluminum / copper alloy, contact to a metal runner extending from the MOSFET's source, drain and gate, through which electrical communication with the MOSFET is achieved. It These metal contacts and runners are formed using the deposition and patterning techniques described above. That is, an electrically insulating glass, for example, a glass containing SiO ₂ —P ₂ O ₅ or SiO ₂ —P ₂ O ₅ —B ₂ O ₃ is a conventional chemical vapor deposition (CVD) technique. Is deposited on the MOSFET and FOX of the IC using. It acts as an interlevel dielectric (electrically insulating layer) between the gate metallization and the source / drain metallization. afterwards,
This interlevel dielectric is patterned to form via holes to the source, drain and gate. A metal conductor, such as aluminum, is deposited, for example by rf-sputtering or electron beam evaporation, on this interlevel dielectric and in the via holes to form electrical contacts to the source, drain and gate. The deposited aluminum (on the interlevel dielectric) is then etched through a patterned etch mask, eg, a patterned photoresist layer, to form interconnect runners terminating in contact pads.

Importantly, the deposition of metal-containing materials on device substrates is often accompanied by undesired interactions between the deposited material and the substrate. For example, semiconductor materials, such as silicon, exhibit high solubility in deposited metals used for electrical contact to the source and drain, such as aluminum. That is, silicon has a tendency to diffuse into aluminum to form an aluminum / silicon alloy. This causes aluminum to diffuse from the upper metal contacts into the lower silicon, forming what is called aluminum spikes. As is well known, aluminum is a p-type dopant for silicon. Therefore, if the aluminum spike extends through the n-type source or drain (to the p-type substrate), the pn junction at the source / substrate or drain / substrate interface is lost. aluminum
Since the spikes typically extend within about 1 μm into the silicon, their presence is usually not a major problem in devices where the source and drain pn junctions have a depth of about 1 μm or more. I won't. However, these spikes become a serious problem in a device having a pn junction depth of about 1 μm or less, which is expected to be commercialized soon.

It has been proposed that aluminum spikes can be prevented by replacing aluminum with a silicon saturated aluminum / silicon alloy, that is, an alloy saturated with silicon at the highest temperatures experienced during manufacture. (This alloy drastically reduces the silicon concentration gradient at the interface between the aluminum and the source and drain, thus disabling the diffusion of silicon from the source and drain into the metal contact.) Unfortunately, At the end of the high temperature treatment, ie at room temperature, these alloys become supersaturated with silicon, which is why (aluminum-doped)
This results in the deposition of silicon. As a result of this deposition, metal contacts to the n ⁺ source and drain (usually doped to levels above about 10 ¹⁹ cm ^-3 ) have unreasonably high contact resistances, ie contacts above about 10 ^-5 ohm-cm ^2. It exhibits resistance, that is, it gives an undesirably high contact resistance. (By contrast, the contact resistance to the p ⁺ source and drain is equal to or greater than about 10 ^-6 ohm-cm ² only.) The aluminum spike provides a barrier to the interdiffusion of aluminum and silicon. It has been proposed that this can be prevented by applying to the source and drain, and high resistance contacts can be avoided. Furthermore, it has been proposed to use tungsten (W) as this barrier. One reason for this suggestion is that tungsten has two low pressures.
It is known that it can be selectively deposited on the source and drain without the use of a deposition mask patterned using any of the CVD (LPCVD) techniques and without the need for subsequent etching. is there. According to the first technique, tungsten hexafluoride (WF ₆ ) is flown onto a treated silicon substrate after the via holes are formed in the interlevel dielectric and before aluminum is deposited in the via holes. . Since WF ₆ is relatively inert as compared to SiO _{2 in the} interlevel dielectric, WF ₆ reacts preferentially with Si in the exposed source and drain regions, forming W ( Solid) and (gas evacuated from the reaction chamber) SiF ₄ are produced via the following chemical formula:

2WF ₆ + 3Si → 2W + 3SiF ₄ (1) This reaction involves removal (etching) of silicon from the source and drain, which has been believed to be insignificant. In addition, the resulting tungsten layer is typically reported to be about 15 nanometers (nm) or less thick, so it is too thin as an effective diffusion barrier between aluminum and silicon.

In a second technique for selectively depositing tungsten, both WF ₆ and H ₂ are flowed across a treated silicon substrate (the total pressure of all gases in the reaction chamber was conventionally about 1 Kept tons). First, WF ₆ reacts with the exposed source and drain Si to form a thin layer of W (as described above). Next, the deposition temperature is about 250
W acts as a catalyst that promotes the chemical reaction between WF ₆ and H ₂ , covering the exposed source and drain regions, but not the interlevel dielectric SiO, provided that the temperature is above ℃ and below about 600 ℃ However, additional W (formed on the source and drain) produces HF (gas exiting the reaction chamber) via the following formula:

WF ₆ + 3H ₂ → W + 6HF (2) The second technique provides a sufficiently thick layer of tungsten to act as an effective diffusion barrier, but with a p ⁺ source (covered with W) with a depth of about 1 μm and Aluminum contacts to the drain region have been reported to exhibit too high a contact resistance, that is, a contact resistance of about 10 ^-5 ohm-cm ² or more. (The contact resistance to the n ⁺ source and drain having a depth of about 1 μm is reported to have a low resistance of about 10 ⁻⁶ ohm-cm ² or more).

That is, to deposit metal-containing materials on treated or untreated substrates that can avoid problems associated with the above-listed methods, a problem that has not yet been realized for those involved in device fabrication process development. The development of this technology remains.

SUMMARY OF THE INVENTION The present invention is a device comprising reacting at least two entities for the purpose of forming a metal-containing material on one region, a plurality of regions, or all of a treated or untreated substrate. It relates to a manufacturing method. In many cases,
The desired reaction is one or more of these reactive entities.
And substrate material, eg, semiconductor material (found on treated or untreated substrate), metal (found on treated substrate), or SiO ₂ (found on treated substrate).
With a second reaction between and (which may even precede). Importantly, this second reaction produces highly undesired results that have hitherto been unrecognized. For example, if one wants to react WF ₆ with H ₂ according to the reaction given in equation (2) to form W on the silicon surface of the source and drain, then WF ₆ is necessarily
Reacts with the silicon according to the reaction given to it, thus partially attacking the source and drain. While this erosion has been believed to be insignificant, it has been discovered that the degree of erosion of the n ⁺ source and drain is usually much greater than that of the p ⁺ source and drain. In fact, it has been discovered that n ⁺ sources and drains with a depth of about 1 μm or less are often severely and in some cases almost entirely eroded. In addition to this,
P ⁺ and n ⁺ (covered with W) having a depth of about 1 μm or less
The contact resistance of aluminum contacts to the source and drain is much higher than the previously reported contact resistance to p ⁺ and n ⁺ sources and drains (covered with W) with a depth of about 1 μm or more. It was discovered. For example, it has been discovered that the contact resistance to the p ⁺ source and drain (covered with W) having a depth of about 1 μm or less is about 5 × 10 ⁻⁵ ohm-cm ² or more. In addition to this, it has a depth of about 1 μm or less (covered with W).
It has been discovered that the n ⁺ source and contact resistance is greater than about 10 ^-5 ohm-cm ² .

The device manufacturing method according to the present invention differs from prior art methods in that it includes various techniques for preventing or greatly reducing the adverse effects associated with the second (undesirable) reaction. That is, the rate of (undesired) reaction between one (or more) of the at least two reactive entities of the substrate material is greatly reduced the rate of (required) reaction between the at least two reactive entities. Techniques have been developed to suppress without causing. For example, if you want to reacting WF ₆ and H ₂ to form a W, large without lowering the reaction rate between the WF ₆ and H _2, it is associated with (undesirable reactions between WF ₆ and Si ) It has been discovered that the reaction rate can be significantly reduced, for example, by increasing the concentration of one of the products of the undesired reaction, that is, by increasing the concentration of SiF ₄ (above the normal concentration). . This technique (and others) greatly reduces erosion of both n ⁺ and p ⁺ sources and drains. This reduction in corrosion is especially important in devices with n ⁺ source and drain depths of about 1 μm or less. Moreover, quite unexpectedly, it gives the good result that the contact resistance to both the n ⁺ and p ⁺ source and drain also drops significantly to levels below about 10 ⁻⁶ ohm-cm ² .

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 to 7 show various steps involved in one embodiment of a device manufacturing method according to the present invention; and FIGS. 8 to 10 are prior art manufacturing methods and the present invention. Achieved by using the device manufacturing method according to
Indicates contact resistance.

DETAILED DESCRIPTION The present invention relates to a method for manufacturing a device, such as a discrete semiconductor device, an integrated circuit device, and a bubble device, the method comprising a region of a treated or untreated substrate, Or forming a metal-containing material over a plurality of regions, or the entire region. The invention also relates to the device obtained from the method according to the invention.

The formation of the metal-containing material is achieved according to the invention by reacting at least two reactive entities (other than the substrate material). Here, at least one of the entities comprises a metal of the type contained within the metal-containing material.
As mentioned, the reaction between the at least two reactive entities often results in a second reaction (or series of reactions) between one (or more) of the reactive entities and the substrate material. Accompany. This second reaction is usually
It gives highly undesirable results that were previously unrecognized. In order to avoid this undesirable result, or to a great extent reduce it, in the device manufacturing method according to the present invention, one of various techniques for slowing down the reaction rate associated with the second undesirable reaction (or Is used). Importantly, these techniques are chosen so that the reaction rate between the two reactive entities is not significantly reduced.
(For the purposes of the present invention, this large reduction in reaction is considered to have been avoided when the rate of formation of the metal-containing material is above about 0.1 nm / min.) Some of the techniques listed above , One produced by an undesired reaction using a different total pressure (of the gas in the reaction chabber) than is conventionally used, or using a reaction temperature different from that conventionally used Or it is accompanied by a variation (out of normal) of multiple products, eg an increase. A control sample should be used to determine which technique to use in a particular situation.

Erosion As an example, as the above explanation, the case where the WF ₆ and H ₂ are reacted to form a W on the silicon surfaces of MOSFET sources and drains, the source and drain inevitably reaction WF ₆ is also silicon To do. The degree of erosion of the n ⁺ source and drain is much greater than that of the p ⁺ source and drain. In fact, as explained above, n ⁺ source and drain with depths of about 1 μm or less are severely eroded, and usually almost all. For purposes of this invention, the depth of the source or drain is the least-squares-fit planar approxi-matio with respect to the original substrate surface.
It is defined as the length of the vertical extension from n) to the lowest point where the dopant concentration in the source or drain is equal to the dopant concentration in the surrounding substrate. This point is
For example, SIMS analysis or conventional junction coloring (junction sta
ining) technology. Regarding these coloring techniques, for example, a Quick Reference Manual for Silicon Inte-g which is edited by a WE beadle (WEBeadle) or the like is used.
rated Circuit Technology, John Wiley and Sons, New York, 1985
See Sections 5-9).

Further, as mentioned above, the reaction rate for undesired reactions between WF ₆ and Si is, for example, the concentration of the products of the undesired reactions, ie the concentration of SiF ₄ (higher than normally occurs).
It has been discovered that by increasing it can be easily dropped, thus reducing overetching of the n ⁺ source and drain. The desired effect is enhanced as the concentration of SiF ₄ is increased. However, when the concentration of SiF ₄ is increased, WF ₆ and H
The reaction rate between the _two tends to decrease. Therefore, according to the present invention, WF ₆ and H ₂ are added to the reaction chamber, for example,
10 sccm (standard cubic centimeters perminute) each
And 2000 sccm, and SiF ₄ is flown into the reaction chamber at a flow rate in the range of about 1 sccm to about 100 sccm. about
SiF ₄ flow rates below 1 sccm are undesirable as they counteract the effect of reducing the reaction rate between WF ₆ and Si. SiF ₄ flow rates above about 100 sccm are undesirable as this significantly slows the reaction rate between WF ₆ and H ₂ .

In addition, the total pressure inside the reaction chamber is 133Pa
It has been discovered that the reaction rate between WF ₆ and Si slows down even above (1 torr). In addition, the use of reaction temperatures outside the conventional temperature range, such as temperatures below about 250 degrees C and above about 600 degrees C, give similar desirable results. However, temperatures above about 600 ° C. reduce the selectivity in the formation of W.

The techniques described above are not only effective in forming W, but are also effective in forming a wide range of metal-containing materials.
For example, metals such as molybdenum, tantalum, titanium and rhenium, and their corresponding silicides are fluorides or chlorides of these metals, such as MoF ₆ , TaCl ₅ TiC.
l ₄ and ReF ₆ as a reducing agent, such as H ₂ (forms a metal) or
It is easily produced by reacting with SiH ₄ (which produces silicide). As mentioned above, these metal fluorides or chlorides tend to react with silicon, giving the undesirable results explained above. However, the reaction rates associated with these unwanted reactions can be easily slowed down using the techniques described above.

As an academic aspect for a more complete understanding of the present invention, a device manufacturing method according to the present invention for manufacturing a MOS IC including one n-channel MOSFET, for example, an n-channel MOS IC or a CMOS IC, is described below. The application of is described. Importantly, the n-channel MOSFET includes n ⁺ source and drain having a depth of about 1 μm or less. Furthermore, this MO
The SFET includes a diffusion barrier, such as a tungsten diffusion barrier, to prevent or reduce interdiffusion of aluminum and silicon at the source and drain,
Therefore, it prevents aluminum from spikes through these sources and drains.

As shown in FIGS. 1 to 7, according to the present invention,
MOS ICs, including n-channel MOSFETs, are manufactured by forming a thin GOX 30 and a thick FOX 40 on the surface of a layer of doped semiconductor material 20. Layer 20 is a substrate 10 of semiconductor material.
Constituting the surface active layer of. MOS IC is n-channel and p
When including both -channel MOSFETs, the substrate 10 necessarily includes both p-type and n-type bulk regions.
In the following description, it is assumed that the n-channel MOSFET is manufactured in a p-type valve region with a doping level of 10 ¹⁶ cm ^-3 , for example.

Thick FOX40 is the GOX on which the MOSFET on the surface of layer 20 should be formed.
GASAD (gate-and-source-and-drain) regions 50 covered with are separated. For example, if active layer 20 is silicon, GOX 30 and FOX 40 are typically composed of thin and thick layers of SiO ₂ , respectively. FOX40 is, for example, layer 20
It is formed by thermally oxidizing the surface of. Layer 20
After opening a window (by conventional technique) in the FOX to expose the GASAD region 50 on the surface of the GOX30, eg layer 2
It is formed by thermally oxidizing the surface of 0 again. For example, in the case of a VLSI (very large scale integrated) MOS IC, the thickness of SiO ₂ GOX 30 is in the range of about 15 nm to about 100 nm, preferably about 20 nm. GOX30 with a thickness of less than about 15 nm shows that this thin layer has a dielectric breakdown (dielectir
It is not desirable due to the risk of causing (c breakdown). On the other hand, thicker than about 100 nm is not desirable because device operation requires unnecessarily high voltage.

The thickness of the SiO ₂ of the MOS IC is in the range of about 200 nm to about 800 nm, preferably about 400 nm. Thicknesses below about 200 nm can cause the voltage applied to the runners to invert the underlying semiconductor material. On the other hand, thicknesses above about 800 nm are not desirable as such thick layers make subsequent conformational deposition of the metal, eg aluminum, difficult.

After the GOX 30 and FOX 40 are formed, a layer of gate material, such as polysilicon, is deposited over the GOX and FOX and then patterned (by conventional techniques) to form gate 60. The thickness of the deposited gate material, and thus the gate thickness, is in the range of about 200 nm to about 800 nm, preferably about 600 nm. Thicknesses below about 200 nm such thin layers have an undesirably high sheet resistance and risk excessive erosion during the etching of via holes through the interlevel dielectric. . Thicknesses above about 800 nm are undesirable because it becomes difficult to achieve substantially vertical gate sidewalls when etching such thick layers.

Using the gate 60 as a deposition mask, a dopant, which is later diffused into the active layer 20 to form the MOSFET source and drain, is implanted into the active layer 20 opposite the gate. It is an n-channel MOSFET, and the active layer 20 is
For example, in the case of silicon (p-type), effective dopants (to form the n ⁺ source and drain) include, for example, phosphorus, arsenic, and antimony. In addition, the radiant energy of these dopants (in
cident energies) is in the range of about 10keV to 300keV,
It is preferably about 100 keV. Energy below about 10 keV is undesirable because the resulting junction becomes too shallow. At energies above 300 keV, the resulting bond becomes too deep. That is, it reaches a depth of 1 μm or more after diffusion.

If the MOS IC also includes a p-channel MOSFET, eg a MOS
If the IC is a CMOS IC, the substrate 10 has a typical dopant level of about 10 ¹⁶ cm ^-3 (within the p-channel MO).
N-type valve region (where the SFET is formed) is also included. Boron, aluminum, and gallium are effective p-type dopants that are subsequently implanted into the n-type valve region, eg, the active layer of n-type silicon, to form the source and drain of the p-channel MOSFET. included. The radiant energy of these dopants is usually the same as the above levels.

Interlevel dielectric 70 is then FOX 40, gate 60, and GASAD
Deposited on the doped portion of region 50. As the interlevel dielectric 70, for example, SiO ₂ --P ₂ O ₅ or SiO _2-
Including but _{P 2 O 5 -B 2 O 3} , these materials can be easily deposited using conventional CVD techniques. The interlevel dielectric 70 has a thickness in the range of about 1/2 μm to about 2 μm, preferably about 1 μm. Thicknesses less than about 1/2 μm are not desirable due to poor insulation in such thin layers. About 2
At thicknesses of μm and above, such thick layers do not lend itself well to subsequent step metallization.

The top surface of the deposited interlevel dielectric 70 is typically not flat (which is usually a problem in later processing). Derives the fluidity of the interlevel dielectric 70, and therefore
To achieve surface planarity and to drive the implanted dopants into the active layer 20 to form the source 80 and drain 90, the substrate is at a temperature in the range of about 850 ° C. to about 1100 ° C. It is heated for a corresponding period ranging from 1 hour to about 2 hours. Temperatures below about 850 ° C. and heating times below about 1 hour are undesirable because the amount of glass flowing becomes too small. On the other hand, temperatures above about 1100 degrees C,
And heating times of about 2 hours or more can form undesired deep bonds.

After formation of the source and drain, the inter-level dielectric will provide via holes 100, 110, and to the source, drain, and gate, respectively.
Patterned (using conventional techniques) to open 120. Using aluminum as electrical contacts (to be formed later) to the source, drain and gate,
If the substrate 10 is silicon, barriers (130, 140) are formed on the individual sources and drains to prevent aluminum and silicon interdiffusion. At the same time, gate 60
Layer 150 is formed thereon. The diffusion barrier comprises, for example, a region of tungsten. Alternatively, the barrier may include titanium, tantalum, molybdenum or rhenium regions. Diffusion barrier thickness is about 30 nm to about 150 nm
And is preferably about 100 nm. About 30 nm
The following thicknesses are undesirable because such thin areas give diffusion areas that are too weak. Thicknesses above about 150 nm result in loss of selectivity in forming tungsten.

When the diffusion barriers 130 and 140 are tungsten, an effective thickness of tungsten is simply and selectively formed on the source and drain by reacting WF ₆ and H ₂ . Further, excessive SiF ₄ is introduced to suppress excessive etching of the n ⁺ source and drain. The flow rate of WF ₆ is about 1 sccm
To about 30 sccm, preferably about 10 sccm. At a flow rate below about 4 sccm, the tungsten formation rate becomes too slow. On the other hand, at a flow rate of about 30 sccm or more,
The corrosion of the equipment used to form the tungsten is severe and undesirable.

The flow rate of H ₂ is in the range of about 100 sccm to about 5000 sccm, preferably about 2000 sccm. Flow rates below about 100 sccm are undesirable because they cause excessive silicon erosion. About 50
Flow rates above 00 sccm result in undesirably high total pressures.

The flow rate of SiO ₄ ranges from 1 sccm to about 100 sccm, preferably about 20 sccm. Flow rates below about 1 sccm and above about 100 sccm are undesirable for the above reasons.

The total pressure of the gas used in the selective formation is about 13 Pa (10
It ranges from 0 millitorr to about 267 Pa (2 torr), preferably about 133 Pa (1 torr). In addition to this, the reaction temperature is in the range of about 250 ° C to about 600 ° C, preferably about 300 ° C or about 550 ° C. About 13Pa (100
Total pressures below millitorr and reaction temperatures below about 250 degrees C are undesirable because they give low tungsten formation rates. A total pressure of about 267 Pa (2 Torr) or higher is undesirable because it provides vapor phase nucleation of tungsten and not nucleation on the source and drain surfaces. At reaction temperatures above about 600 ° C, the selectivity in tungsten formation is lost.

After forming the diffusion barriers 130 and 140, a layer of metal 160, eg, an aluminum layer, is deposited on the interlevel dielectric 70 and in the via holes leading to the source, drain and gate. The thickness of layer 160 is in the range of about 1/2 μm to about 2 μm. Thicknesses less than about 1/2 μm give undesirably high sheet resistance. Above a thickness of about 2 μm, such thick layers do not achieve substantially vertical sidewalls during patterning of this layer. Following deposition, the metal layer 160 is patterned (not shown), eg, selective reactive ion etching, to form interconnect metal runners terminating in the metal contact pads. The substrate thus treated is then subjected to about 1 ° C., for example at a temperature of 450 ° C., to remove the radiation damage generated during reactive ion etching.
Annealed for hours.

MOS IC is completed by a series of conventional steps,
During these steps, a silicon nitride layer is typically deposited on the IC by conventional techniques of plasma-enhanced CVD to form a barrier to protect against moisture and physical damage.

The MOS ICs described above differ from conventional MOS ICs in that the formation of the diffusion barrier provides a substantially erosion-free n ⁺ source and drain. (For purposes of the present invention, a source or drain is a vertical extension of about 30 nm or less from the least squares corrected plane approximation of the original substrate surface to the lowest point of the interface between the diffusion barrier and the source or drain. It is considered to be virtually eroded at times). In addition to this, unexpectedly, metal contacts to all sources and drains of this IC, including the sources and drains of n-channel MOSFETs, are typically less than about 10 ¹⁶ ohm-cm ^2. Shows a contact resistance of about 5 × 10 ⁻⁷ ohm-cm ² or less.
Importantly, this unexpectedly low contact resistance is thermally stable, that is, substantially unaffected by conventional annealing procedures such as those described above.
As a result, the resulting contact resistance is thermally stable and still well below the levels previously achievable. (For the purpose of the present invention, the contact resistance to the source or drain is the product of the contact resistance Rc to the source or drain and the area A of the upper surface of the source or drain. It can be easily determined by measuring a current-voltage (IV) curve across the area of the device substrate that contains the upper surface area A and the source or drain depth d in the prior art. For example, scanning electron microscopy, transmission electron microscopy, or secondary ion mass spectroscopy can be used to determine the ideal curve IV for the source or drain based on the measurements of A and d . , For example,
SM sze (SMSze), semiconductor device physics (Physi
cs of Semiconductor Devices), John Willie
And Sons (John Wiley and Sons, NY), 2nd
Edition, calculated from the method shown on page 304. Typically, the measured IV curve deviates from the theoretical IV curve by a certain amount. What is important is that Rc has a certain relationship with this deviation. That is, it is represented by Rc = ΔV / I. Where ΔV represents the difference in voltage value between the two IV curves for a fixed current I. Alternatively, Rc applies a forward bias voltage across the source or drain and increases it to the corresponding dV / dI,
That is, it can be easily determined by measuring the derivative with respect to the source / drain current as a result of the applied voltage. Contact resistance is saturated, that is, when dV / dI stops changing with increasing forward bias.
Equal to dV / dI.

Although not essential to the invention, the above MOS IC is preferably a region of metal silicide, ie cobalt silicide, titanium silicide, on the source or drain prior to forming the diffusion barrier as described above. , Platinum silicide, or molybdenum silicide. These metal silicide regions are important because they result in a stable contact resistance to heat to the source and drain of a MOS IC, including the source and drain of the n-channel MOSFET. The contact resistance thus obtained is even lower than the values explained above. That is, it is about 10 ^-6 ohm-cm ² or less, and further about 10 ^-7 ohm-cm ² or less. The thickness of metal silicide is about
The range is from 30 nm to about 100 nm. A thickness of about 30 nm or less is unsuitable because such a thin layer cannot usually prevent the upper metal from penetrating the substrate and consequently increasing contact resistance. Thicknesses above about 100 nm are unsuitable because such thick layers consume unduly large amounts of substrate material during silicide formation.

Preferably, the metal silicide region deposits corresponding pure metal in the via holes in the interlevel dielectric, i.e., rf-sputtered, and then sintered in an inert atmosphere, e.g., argon, thus removing the metal. It is formed by reacting with the silicon of the source and drain. The thickness of the deposited metal is in the range of about 15 nm to about 50 nm. Thicknesses less than about 15 nm and greater than about 50 nm are undesirable because they give metal suicide thicknesses outside the ranges described above.
Suitable sintering temperature and corresponding sintering time is about 300 degree C
The temperature ranges from about 1 hour to about 1000 ° C for about 1 hour. Sintering temperatures below about 300 ° C. and sintering times below about 1 hour are not suitable due to incomplete reaction between the metal and silicon. Sintering temperatures of about 1000 ° C. and above, and sintering times of about 1 hour and above are not suitable to cause undesired reactions between both metal and silicon and silicon dioxide in the metal silicide.

Using the sintering procedure to form the metal silicide regions described above, some erosion of the source and drain occurs. However, this erosion is typically small compared to the erosion produced by the undesired reaction between WF ₆ and the source and drain silicon.

Importantly, this metal silicide region is porous, thus allowing reactive entities, such as WF _6, to react with and attack the source and drain silicon.
In addition, WF ₆ tends to leach out and react with the metal silicide silicon. For this reason, the method according to the invention described above is essential for preventing the erosion of the metal suicide and achieving a substantially erosion-free source and drain. (For purposes of the present invention, a diffusion barrier and a source or drain covered with a metal silicide is the length of extension from a particular virtual plane to the lowest point of the interface between the metal silicide and the source or drain. Is considered to be substantially free of erosion when is less than about 30 nm.This virtual plane is located below (inside of) the least-squares correction approximation plane to the original substrate surface and parallel to it. , The vertical length extending between the two planes is equal to the thickness of the corresponding uniform layer of silicon consumed to form the metal suicide, which thickness depends on the amount of metal in the metal suicide. Easy to guess,
This is the case, for example, with the traditional Rutherford Backscatter (Ru
It can be easily determined using the therford Back-Scattering technique. If the silicon source used to form the metal silicide is not a source or drain, the virtual plane will be the same as the least squares corrected plane approximation to the original substrate surface. Example: Two groups of silicon wafers of opposite conductivity type were processed as follows. The first group, referred to herein as Group I, contains 25 p-type wafers exhibiting a resistance of 20-100 Ωcm, while the second group, referred to as Group II, contains 25 p-type wafers exhibiting a resistance of 10-20 Ω. Of n-type wafers.

First, a silicon dioxide layer with a thickness of about 10 nm was thermally grown on individual wafers. A relatively highly doped n-type bulk region is then formed in the group I wafer, and a relatively highly doped n-type bulk region is formed in the group II wafer. The p-tabs and n-tabs that were formed and employed in CMOS devices were simulated. It implants boron ions into group I wafers (30keV, 4 × 10 ¹² cm ^-2 ) and phosphorus ions into group II wafers (100keV, 2 ×).
10 ¹² cm ^-2 ) and then heating the wafer at 1100 degrees C for about 2 hours to diffuse into the wafer.

A layer of silicon nitride having a thickness of about 120 nm was deposited on individual Group I and Group II wafers using conventional LPCVD techniques. The silicon nitride layer on each wafer is then
Selective reactive ion etching was performed in an atmosphere of CHF ₃ and O ₂ .
Field oxide (FOX) having a thickness of about 600 nm was thermally grown on the resulting exposed surface area of individual wafers. After removing the silicide nitride, a gate oxide (GOX) with a thickness of about 25 nm was thermally grown on the individual wafers on the surface area previously covered by silicon nitride.

In order to ultimately form what will be the source and drain regions within the wafer, Group I wafers are 100 keV at various dose levels ranging from 8 × 10 ¹⁴ cm ^-2 to 1 × 10 ¹⁶ cm ^-2. An implant of arsenic (n-type dopant) was made. Arsenic passed through the GOX-covered area but did not reach the FOX-covered area. Similarly, for Group II wafers from 8 x 10 ¹⁴ cm ^-2 to 1 x 10 ¹⁶
50keV boron at various dose levels in the cm ^-2 range-
Implantation of difluoride (p-type dopant) was performed.

An interlevel dielectric consisting of a 200 nm layer of undoped silicon dioxide was deposited on individual wafers using conventional LPCVD techniques. (The interlevel dielectric was not doped to avoid contaminating the p ⁺ region with phosphorus, an n-type dopant.) This interlevel dielectric then heats the wafer at 900 ° C. for 30 minutes. Was tightly packed by. In addition, by heating the wafer at 950 ° C for about 60 minutes, the interlevel dielectric is flushed to planarize this upper surface, arsenic and phosphorus implants are activated, and the source / drain is drained. Diffused into the wafer to form regions.

The interlevel dielectric was selectively wet etched using HF to form via holes to the source / drain regions. (Reactive Ion Etching was not dared to avoid the erosion of silicon by this etch.) This via hole has a 1.25 μm long side (as achieved using anisotropic reactive ion etching). Although intended to be a square with, the isotropic etching provided by HF tends to widen the via holes into squares with sides as long as 2.2 μm.

The processed wafers were divided into three categories (Category I, II and III). Categories I and II
Includes p-type (Group I) and n-type (Group II) wafers with varying arsenic implant levels and Boron difluoride implant levels, respectively, while Category III includes one p-type wafer and Included one n-type wafer.

A layer of tungsten was selectively deposited on the source / drain regions of Category I wafers using a two step process. That is, a film of tungsten having a thickness of about 15 nm is first formed on a Category I wafer by passing WF ₆ across the wafer, eg, at a temperature of 290 ° C. for about 1 minute (equation (1) Was selectively deposited (via the reaction given to). The thickness in the deposition chamber was 400 Pa (3 torr). The partial pressure of WF ₆ is 0.67Pa
(5 mTorr) and the partial pressure of Argon constituted the remaining pressure of the total pressure. Then, an additional layer of tungsten having a thickness of about 50 nm is applied by flowing WF ₆ and H ₂ across the wafer at a temperature of, for example, 290 ° C. for about 15 minutes (the reaction given in equation (2)). Selectively). The total pressure in the deposition chamber was 186.7 Pa (1.4 torr), the partial pressure of WF ₆ was 1.3 Pa (10 mtorr), and the partial pressure of H ₂ constituted the rest of this total pressure.

A layer of tungsten with a thickness of about 50 nm is about 1 at a temperature of 290 ° C.
It was selectively deposited on the source / drain regions of Category II wafers by flowing WF ₆ , H ₂ and SiF ₄ across the wafer for 5 minutes. The total pressure in the deposition chamber is 189.
3 Pa (1.42 Torr), WF ₆ partial pressure is 1.3 Pa (10 mTorr), SiF ₄ partial pressure is 6.7 Pa (20 mTorr), and H ₂ partial pressure is the remainder of this total pressure. Configured.

The processing of Category III wafers differs from the processing of Category II wafers only in that a layer of platinum siliside is formed on the source / drain regions prior to the formation of tungsten. That is, a Category III wafer was first cleaned with a HNO ₃ / H ₂ SO ₄ solution. Next, a 20 nm thick layer of platinum is sputter-deposited on the upper surface of the wafer and the wafer is placed in a gas atmosphere containing 90 percent argon (by volume) and 10 percent oxygen.
Sintered at 650 ° C for about 15 minutes. As a result, about 40 nm
A layer of platinum silicide having a thickness of .epsilon. Was selectively formed on the exposed upper surface of the source and drain. The remaining unreacted platinum was removed using aqua regia. The wafers were cleaned with a 100: 1 FH solution prior to tungsten formation.

Following the selective tungsten deposition procedure, Category I,
All II and III wafers were metallized. That is,
A 1 μm thick Al-1 / 2 percent Cu film was sputtered onto individual wafers. The aluminum on the interlevel dielectric then runs through the runner (ru) that terminates at the contact pad.
nr) was formed by selective reactive ion etching in a BCl ₃ / Cl ₂ atmosphere.

The contact resistance to the source and drain regions of all wafers is source / drained using the conventional kelvin method.
The drain surface doping concentration was measured as a function of N _D. In this regard, for example, RA Levy 2 (RALevy)
Paper [In-source Al-0.5% Cu for CMOS devices]
In-Source Al-0.5% Cu Metallization for C
MOS Devices)], Journal of the Electrochem Society
ical Society), Vol. 132, page 159, 1985. To test the thermal stability of these contact resistances, the wafer was placed at a temperature of 330 ° C. for 45 minutes and then 450.
Sintered for 45 minutes at C and the contact resistance was measured after each sintering procedure.

The values of contact resistance measured as a function of N _D are plotted in FIGS. 8-10. As can be seen in Figures 8 and 9 which show the results achieved with Category I wafers, the contact resistance to the p ⁺ source / drain regions is lower than that to the n ⁺ regions at equivalent surface doping concentrations. high. In addition to this, the contact resistance to both the n ⁺ and p ⁺ regions is thermally unstable. That is, there is a large rise after the sintering procedure.

Figure 10 shows the results achieved with Category II and Category III wafers. As is clear from the figure,
The contact resistance to the p ⁺ region in a Category II wafer is equal to or lower than the contact resistance to the n ⁺ region,
Both sets of contact resistance are thermally stable.
In addition to this, Category III wafers exhibit greatly reduced and thermally stable contact resistance to both the n ⁺ and p ⁺ regions.

Scanning electron and transmission electron microbluffs were taken on samples taken from Category I, II and III wafers. These micro bluffs are category II and II
It was shown that the source and train areas in the I wafers suffered significantly less vertical and lateral erosion than the corresponding areas in the Category I wafers.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Levy, Roland Albert United States 07974 New Jersey, Murray Hill, Summit Road 40

Claims (8)

[Claims] 1. A method of manufacturing a device, the method comprising the steps of forming a metal-containing material on a region of a treated or untreated substrate containing a substrate material, and completing the manufacture of the device. A step of reacting at least a first reactive entity with at least a second reactive entity and the substrate material, the reacting step comprising: a product containing the metal-containing material; A method of manufacturing a device for producing a product comprising a substrate material, the first reactive entity and the substrate without substantially slowing down the reaction rate between the first and second reactive entities. A method comprising adding a reactive entity comprising a reaction product of the substrate material and the first reactive entity to reduce a reaction rate between materials. 2. The method of claim 1, wherein the substrate material comprises a semiconductor material. 3. The method of claim 2 wherein the semiconductor material comprises silicon. 4. The method according to claim 1 or 2, wherein the semiconductor material includes silicon, and an aluminum layer is provided on the metal-containing material. how to. 5. The method according to claim 1, wherein the metal-containing material contains at least one of tungsten, tantalum, titanium, molybdenum, and rhenium. And how to. 6. A method according to any one of claims 1 to 5 wherein the first reactive entity comprises WF ₆ . 7. A method as claimed in any one of claims 1 to 6 wherein the second reactive entity comprises H ₂ . 8. The method according to claim 1, wherein the product contains SiF ₄ .