JPH0680751B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0680751B2 JPH0680751B2 JP63041071A JP4107188A JPH0680751B2 JP H0680751 B2 JPH0680751 B2 JP H0680751B2 JP 63041071 A JP63041071 A JP 63041071A JP 4107188 A JP4107188 A JP 4107188A JP H0680751 B2 JPH0680751 B2 JP H0680751B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- lead
- back surface
- carrier tape
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/701—Tape-automated bond [TAB] connectors
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はテープ・オートメーテイツド・ボンデイング方
式（以下TAB方式という）によつて半導体素子が接合さ
れた半導体装置に関し、特にそのパツケージ構造に関す
るものである。The present invention relates to a semiconductor device in which semiconductor elements are joined by a tape automated bonding method (hereinafter referred to as TAB method), and more particularly to a package structure thereof. Is.
〔従来の技術〕 従来、TAB方式に裏面電位を必要とする半導体素子を用
いる場合には、基板上の配線に半導体素子の裏面を接着
し、その配線と半導体素子の表面端子とをリード配線を
介して接続することにより半導体素子の裏面電位を得て
いた。[Prior Art] Conventionally, when a semiconductor element that requires a back surface potential is used in the TAB method, the back surface of the semiconductor element is adhered to the wiring on the substrate, and the lead wire is connected to the wiring and the surface terminal of the semiconductor element. The back surface potential of the semiconductor element was obtained by connecting through.
第４図はTAB方式によつてキヤリアテープに半導体素子
が固着された状態を示す図で、同図（ａ）は平面図、
（ｂ）は（ａ）図中IV−IV線断面図を示し、第５図は半
導体装置が基板に実装された状態を示す側断面図であ
る。これらの図において、符号１は半導体素子、２はこ
の半導体素子１のパツド上に固着されたバンプと呼ばれ
る突起電極、３はキヤリアテープで、このキヤリアテー
プ３はポリイミドテープ等によつて形成され、半導体素
子１を臨む開口部3aと、後述する半導体素子１の切り離
し工程でキヤリアテープ３から半導体素子１を切断する
位置となるアウターリード孔3bとが設けられ、これらの
開口部3aとアウターリード孔3bによつてサポート部3cが
形成されており、インナーリード4a、アウターリード4b
およびテストパツド部4cからなるリード配線４が貼着さ
れている。また、このリード配線４はテープ基材に銅等
の金属箔を貼り合わせ、その後リードパターンに形成さ
れており、リードのパターンが複雑になつたり、あるい
は長くなつた際には、リードの載置が不安定にならない
よう前記サポート部3cによつて保持されることになる。
すなわち、半導体素子１は、TAB方式におけるインナー
リードボンデイング工程において、ボンデイングツール
等により前記インナーリード4aに突起電極２が熱圧着さ
れることによつて、キヤリアテープ３に固着されること
になる。なお、突起電極２は半導体素子に形成される
他、インナーリード4aに形成されるものである。５は半
導体素子１をキヤリアテープ３に固定すると共に保護す
るための封止樹脂、６は半導体装置と他の回路を接続す
るための基板で、この基板６上には前記アウターリード
4bが接合される基板配線7aおよび半導体素子１の裏面が
接着される基板配線7bが設けられている。８は半導体素
子１の裏面と基板配線7bを接着するダイスボンデイング
材、９は外装樹脂である。FIG. 4 is a view showing a state in which the semiconductor element is fixed to the carrier tape by the TAB method, and FIG. 4 (a) is a plan view,
FIG. 5B is a sectional view taken along line IV-IV in FIG. 5A, and FIG. 5 is a side sectional view showing a state in which the semiconductor device is mounted on the substrate. In these drawings, reference numeral 1 is a semiconductor element, 2 is a protruding electrode called a bump fixed on the pad of the semiconductor element 1, 3 is a carrier tape, and the carrier tape 3 is formed by a polyimide tape or the like. An opening 3a facing the semiconductor element 1 and an outer lead hole 3b at a position where the semiconductor element 1 is cut from the carrier tape 3 in a step of separating the semiconductor element 1 described later are provided, and the opening 3a and the outer lead hole are provided. The support portion 3c is formed by 3b, and the inner lead 4a and the outer lead 4b are formed.
Also, the lead wiring 4 including the test pad portion 4c is attached. Further, the lead wiring 4 is formed by bonding a metal foil such as copper to a tape base material and then forming a lead pattern. When the lead pattern becomes complicated or becomes long, the lead is placed. Will be held by the support portion 3c so that it does not become unstable.
That is, the semiconductor element 1 is fixed to the carrier tape 3 by thermocompression bonding the protruding electrode 2 to the inner lead 4a by a bonding tool or the like in the inner lead bonding process in the TAB method. The protruding electrode 2 is formed not only on the semiconductor element but also on the inner lead 4a. 5 is a sealing resin for fixing the semiconductor element 1 to the carrier tape 3 and protecting it, 6 is a substrate for connecting the semiconductor device and other circuits, and the outer leads are provided on the substrate 6.
Substrate wiring 7a to which 4b is joined and substrate wiring 7b to which the back surface of semiconductor element 1 is bonded are provided. Reference numeral 8 is a die bonding material for adhering the back surface of the semiconductor element 1 and the substrate wiring 7b, and 9 is an exterior resin.
したがつて、キヤリアテープ３に固着された半導体素子
１はキヤリアテープ３におけるアウターリード孔3bから
アウターリード4bと共に所定寸法に打ち抜かれ、次いで
基板配線7aおよび7bにアウターリード4bの切断端および
半導体素子１の裏面が接合され、外装樹脂９によつて固
定される。この際、半導体素子１の裏面は基板配線7bお
よび図示しないリード配線を介して突起電極２に接続さ
れている。Therefore, the semiconductor element 1 fixed to the carrier tape 3 is punched to a predetermined size together with the outer lead 4b from the outer lead hole 3b in the carrier tape 3, and then the cut ends of the outer lead 4b and the semiconductor element are attached to the board wirings 7a and 7b. The back surface of 1 is joined and fixed by the exterior resin 9. At this time, the back surface of the semiconductor element 1 is connected to the protruding electrode 2 via the substrate wiring 7b and the lead wiring (not shown).
TAB方式によつてキヤリアテープに固着された裏面電位
を要する半導体素子は最終的に基板上に接合させてから
でないと半導体素子の裏面と表面端子が接続されないの
で、インナーリードボンデイング後の動作の確認ができ
なかつた。このため半導体素子とインナーリードとの接
合不良を起した半導体素子および封止樹脂により欠陥が
生じた半導体素子などのバーンインが不可能であり、製
品としての歩留が落ちることとなる。また、上記のよう
な不良半導体素子の接合された基板は全て無駄になつて
しまうという問題もあつた。Confirm the operation after bonding the inner lead because the semiconductor device fixed to the carrier tape by the TAB method and requiring the back surface potential must be finally joined to the substrate before the back surface and surface terminals of the semiconductor device are connected. I couldn't do it. For this reason, it is impossible to burn-in a semiconductor element having a defective joint between the semiconductor element and the inner lead, a semiconductor element having a defect due to the sealing resin, etc., and the yield as a product is reduced. Further, there is a problem that all the substrates to which the defective semiconductor elements are bonded as described above are wasted.
本発明に係る半導体装置は、内側底面に半導体素子の裏
面が接着される金属キヤツプを備え、先端がキヤリアテ
ープの開口部内に挿入され前記金属キヤツプに接合され
るコンタクト部を半導体素子の表面電極と接続された裏
面電位接続用リードに一体に設けたものである。The semiconductor device according to the present invention includes a metal cap to which the back surface of the semiconductor element is adhered on the inner bottom surface, and a contact portion whose tip is inserted into the opening of the carrier tape and joined to the metal cap is a front surface electrode of the semiconductor element. It is provided integrally with the connected back surface potential connecting lead.
金属キヤツプおよび裏面電位接続用リードを介して半導
体素子の裏面の電極とが接続される。The electrodes on the back surface of the semiconductor element are connected via the metal cap and the leads for connecting the back surface potential.
以下、その構成等を図に示す実施例により詳細に説明す
る。Hereinafter, the configuration and the like will be described in detail with reference to the embodiments shown in the drawings.
第１図は本発明に係る半導体素子を示す側断面図、第２
図（ａ），（ｂ）はキヤリアテープに半導体素子が固着
された状態を示す平面図と要部を拡大して示す断面図で
ある。これらの図において前記第４図および第５図で説
明したものと同一もしくは同等部材については同一符号
に付し、詳細な説明は省略する。これらの図において
は、11はキヤツプで、このキヤツプ11は導電性の良い金
属によつて形成され、その内側底面は半導体素子１の裏
面にダイスボンデイング材８によつて接合されている。
12はリード配線４と前記キヤツプ11とを接続するための
コンタクトリードで、このコンタクトリード12は、半導
体素子１における裏面電位を必要とするパツド（図示せ
ず）上の突起電極２に接続された裏面電位接続用リード
としてのリード配線４と一体に形成されている。すなわ
ち、このコンタクトリード12は、リード配線４を形成す
る際に、コンタクトリード12となる部分が残るように、
キヤリアテープ３上に貼着された銅箔をエツチング処理
することによつて形成される。13は前記コンタクトリー
ド12の先端部が挿入される透孔で、この透孔13はキヤリ
アテープ３のサポート部3cに穿設されている。なお、14
は封止用樹脂である。FIG. 1 is a side sectional view showing a semiconductor device according to the present invention, and FIG.
FIGS. 3A and 3B are a plan view showing a state in which a semiconductor element is fixed to a carrier tape and a cross-sectional view showing an enlarged main part. In these figures, the same or equivalent members as those described in FIGS. 4 and 5 are designated by the same reference numerals, and detailed description thereof will be omitted. In these drawings, reference numeral 11 denotes a cap, and the cap 11 is formed of a metal having good conductivity, and the inner bottom surface thereof is joined to the back surface of the semiconductor element 1 by a die bonding material 8.
Reference numeral 12 is a contact lead for connecting the lead wiring 4 and the cap 11, and the contact lead 12 is connected to the protruding electrode 2 on the pad (not shown) requiring the back surface potential of the semiconductor element 1. It is formed integrally with the lead wiring 4 as a back surface potential connecting lead. That is, in the contact lead 12, when the lead wiring 4 is formed, the portion that will become the contact lead 12 remains,
It is formed by etching the copper foil adhered on the carrier tape 3. Reference numeral 13 is a through hole into which the tip portion of the contact lead 12 is inserted, and the through hole 13 is formed in the support portion 3c of the carrier tape 3. In addition, 14
Is a sealing resin.
このように構成された半導体装置を組立てるには、先
ず、TAB方式におけるインナーリードボンデイング工程
においてキヤリアテープ３にリード配線４を介して半導
体素子１を固着させる。そして、コンタクトリード12の
先端部を第２図（ｂ）に示すように透孔13内に挿入させ
た状態で、半導体素子１の裏面とキヤツプ11の内側底面
とをダイスボンデイング材８によつて接合させる。次で
前記コンタクトリード13の先端を前記半導体素子１接合
用ダイスボンデイング材８によつてキヤツプ11に接合さ
せる。すなわち、この時点で半導体素子１の裏面と表面
のパツドはキヤツプ11、コンタクトリード12、裏面電位
接続用リードとしてのリード配線４を介して連結される
ことになる。しかる後、封止樹脂14をキヤツプ11内に充
填し、半導体素子１およびリード配線４等を封止する。
樹脂封止後、アウターリード4bを切断することによつて
キヤリアテープ３から半導体装置として分断されること
になり、組立てが終了する。In order to assemble the semiconductor device having such a structure, first, the semiconductor element 1 is fixed to the carrier tape 3 through the lead wiring 4 in the inner lead bonding process in the TAB method. Then, with the tip end of the contact lead 12 inserted into the through hole 13 as shown in FIG. 2B, the back surface of the semiconductor element 1 and the inner bottom surface of the cap 11 are separated by the die bonding material 8. Join. Next, the tips of the contact leads 13 are joined to the cap 11 by the die bonding material 8 for joining the semiconductor element 1. That is, at this time, the pads on the back and front surfaces of the semiconductor element 1 are connected via the cap 11, the contact leads 12, and the lead wiring 4 as the back surface potential connection lead. Then, the cap 11 is filled with the sealing resin 14 to seal the semiconductor element 1, the lead wiring 4, and the like.
After the resin is sealed, the outer lead 4b is cut, so that the carrier tape 3 is separated as a semiconductor device, and the assembly is completed.
したがつて、半導体素子１の裏面と表面の突起電極２
は、封止樹脂14によつて封止される以前にキヤツプ11、
コンタクトリード12および裏面電位接続用リードとして
のリード配線４を介して接続され、インナーリードボン
デイング後の動作を確認することができる。Therefore, the protruding electrodes 2 on the back and front surfaces of the semiconductor element 1
Is the cap 11, before being sealed by the sealing resin 14.
It is connected via the contact lead 12 and the lead wiring 4 as a back surface potential connecting lead, and the operation after the inner lead bonding can be confirmed.
なお、本実施例におけるコンタクトリード12は、キヤリ
アテープ３に穿設された透孔13内に先端部が挿入される
ものを示したが、本発明においてはこのような限定にと
らわれることなく、例えば第３図に示すように形成して
もよい。第３図は他の実施例を示す平面図で、同図にお
いて前記第１図および第２図と同一もしくは同等部材に
ついては同一符号が付されている。第３図において、コ
ンタクトリード12は先端部がキヤリアテープ３の開口部
3aに臨むように形成されており、組立て工程において前
記先端部が開口部3a内に挿入され、キヤツプ11と接続さ
れることになる。コンタクトリード12をこのように形成
すると透孔13を穿設する手間が省ける。Although the contact lead 12 in this embodiment is one in which the tip portion is inserted into the through hole 13 formed in the carrier tape 3, the present invention is not limited to such a limitation. It may be formed as shown in FIG. FIG. 3 is a plan view showing another embodiment, in which the same or equivalent members as those in FIGS. 1 and 2 are designated by the same reference numerals. In FIG. 3, the contact lead 12 has an opening at the opening of the carrier tape 3.
It is formed so as to face the 3a, and the tip portion is inserted into the opening 3a and connected to the cap 11 in the assembly process. When the contact lead 12 is formed in this way, the labor of forming the through hole 13 can be omitted.
以上説明したように本発明によれば、内側底面に半導体
素子の裏面が接着される金属キヤツプを備え、先端がキ
ヤリアテープの開口部内に挿入され前記金属キヤツプに
接合されるコンタクト部を前記半導体素子の表面電極と
接続された裏面電位接続用リードに一体に設けたため、
半導体素子をキヤリアテープに固着した時点で動作の確
認ができ、半導体素子の異常を早期に発見することがで
きる。このため、歩留りの向上およびコストダウンが実
現される。As described above, according to the present invention, the inner bottom surface is provided with the metal cap to which the back surface of the semiconductor element is adhered, and the tip is inserted into the opening of the carrier tape and the contact portion joined to the metal cap is provided in the semiconductor element. Since it is integrated with the back surface potential connection lead connected to the front surface electrode of
The operation can be confirmed when the semiconductor element is fixed to the carrier tape, and the abnormality of the semiconductor element can be detected early. Therefore, the yield is improved and the cost is reduced.
第１図は本発明に係る半導体装置を示す側断面図、第２
図（ａ），（ｂ）はキヤリアテープに半導体素子が固着
された状態を示す平面図と要部を拡大して示す断面図、
第３図は他の実施例を示す平面図、第４図はTAB方式に
よつてキヤリアテープに半導体素子が固着された状態を
示す図で、同図（ａ）は平面図、（ｂ）は（ａ）図中IV
−IV線断面図を示し、第５図は半導体装置が基板に実装
された状態を示す側断面図である。 １……半導体素子、２……突起電極、３……キヤリアテ
ープ、3a……開口部、４……リード配線、11……キヤツ
プ、12……コンタクトリード、13……透孔。FIG. 1 is a side sectional view showing a semiconductor device according to the present invention, and FIG.
(A) and (b) are a plan view showing a state in which a semiconductor element is fixed to a carrier tape and a sectional view showing an enlarged main part,
3 is a plan view showing another embodiment, FIG. 4 is a view showing a state in which a semiconductor element is fixed to a carrier tape by the TAB method, FIG. 3 (a) is a plan view, and FIG. (A) IV in the figure
FIG. 5 is a side sectional view showing a state in which the semiconductor device is mounted on a substrate. 1 ... semiconductor element, 2 ... projection electrode, 3 ... carrier tape, 3a ... opening, 4 ... lead wiring, 11 ... cap, 12 ... contact lead, 13 ... through hole.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 寺岡 康宏 兵庫県伊丹市瑞原４丁目１番地 三菱電機 株式会社北伊丹製作所内 (72)発明者 関 博司 兵庫県伊丹市瑞原４丁目１番地 三菱電機 株式会社北伊丹製作所内 (72)発明者 立川 透 兵庫県伊丹市瑞原４丁目１番地 三菱電機 株式会社北伊丹製作所内 (56)参考文献 特開 昭62−217621（ＪＰ，Ａ) 特公 昭52−3275（ＪＰ，Ｂ２) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasuhiro Teraoka 4-1-1 Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Corporation Kita-Itami Works (72) Inventor Hiroshi Seki 4-1-1 Mizuhara, Itami City, Hyogo Mitsubishi Electric Corporation Company Kita Itami Works (72) Inventor Toru Tachikawa 4-1, Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Co., Ltd. Kita Itami Works (56) References JP 62-217621 (JP, A) Japanese Patent Publication Sho 52- 3275 (JP, B2)
Claims (1)
よつて固着された半導体装置において、内側底面に半導
体素子の裏面が接着される金属キヤツプを備え、先端が
キヤリアテープの開口部内に挿入され前記金属キヤツプ
に接合されるコンタクト部を前記半導体素子の表面電極
と接続された裏面電位接続用リードに一体に設けたこと
を特徴とする半導体装置。1. A semiconductor device in which a semiconductor element requiring a back surface potential is fixed by a TAB method, the inner bottom surface is provided with a metal cap to which the back surface of the semiconductor element is adhered, and the tip is inserted into an opening of a carrier tape. A semiconductor device, wherein a contact portion joined to the metal cap is integrally provided on a back surface potential connecting lead connected to a front surface electrode of the semiconductor element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63041071A JPH0680751B2 (en) | 1988-02-24 | 1988-02-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63041071A JPH0680751B2 (en) | 1988-02-24 | 1988-02-24 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01215051A JPH01215051A (en) | 1989-08-29 |
| JPH0680751B2 true JPH0680751B2 (en) | 1994-10-12 |
Family
ID=12598213
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63041071A Expired - Fee Related JPH0680751B2 (en) | 1988-02-24 | 1988-02-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0680751B2 (en) |
-
1988
- 1988-02-24 JP JP63041071A patent/JPH0680751B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01215051A (en) | 1989-08-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0856889B1 (en) | Semiconductor device mount structure and semiconductor device mounting method | |
| JP2982450B2 (en) | Film carrier semiconductor device and method of manufacturing the same | |
| JPH01132142A (en) | Package structure of semiconductor device | |
| US6717244B1 (en) | Semiconductor device having a primary chip with bumps in joined registration with bumps of a plurality of secondary chips | |
| KR0175417B1 (en) | Semiconductor device and manufacture thereof | |
| JP2569400B2 (en) | Method for manufacturing resin-encapsulated semiconductor device | |
| JPH11191574A (en) | Semiconductor device | |
| JPH0680751B2 (en) | Semiconductor device | |
| JP2718299B2 (en) | Large-scale integrated circuits | |
| JP3270883B2 (en) | Semiconductor device | |
| JPS63204735A (en) | Package structure for semiconductor device | |
| JPH1140728A (en) | Lead frame, electronic component using the lead frame, and method for manufacturing electronic component | |
| JP2503646B2 (en) | Lead frame and semiconductor integrated circuit device | |
| JPH03261153A (en) | Package for semiconductor device | |
| JPH07201928A (en) | Film carrier and semiconductor device | |
| JPS63185035A (en) | Semiconductor device | |
| JPH11186467A (en) | Semiconductor device, lead frame used for manufacturing the same, and method of manufacturing the same | |
| JPH01215050A (en) | Semiconductor device | |
| JP2555878B2 (en) | Method of manufacturing film carrier tape | |
| JP2551243B2 (en) | Semiconductor device | |
| JP3024046B2 (en) | Semiconductor package | |
| JP2699284B2 (en) | Substrate bonding method | |
| JPH0366150A (en) | Semiconductor integrated circuit device | |
| JP2555916B2 (en) | Film carrier semiconductor device | |
| JP2614005B2 (en) | Film carrier tape and lead bonding method therefor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| LAPS | Cancellation because of no payment of annual fees |