JPH0683402A - PWM drive circuit - Google Patents

Abstract

PURPOSE:To obtain the PWM driving circuit of simple constitution which generates small distortion. CONSTITUTION:This circuit is equipped with a saw-tooth wave generating circuit 3 which compares the level of an input signal VIN with the level of a reference voltage VR and generates a saw-tooh wave signal WSAW with a necessary polarity, a comparator 1 which compares the level of the input signal VIN with the level the saw-tooth wave signal WSAW generated by the saw-tooth wave generating circuit 3 and generates a PWM signal with a necessary polarity, and a PWM logic circuit means 4 which determines the driving direction of a load 5 on the basis of the comparison result POL and the generated PWM signal with the necessary polarity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PWM drive circuit for controlling electric power supplied to a load such as a motor or an actuator with a PWM (pulse width modulation) signal.

[0002]

2. Description of the Related Art A conventional PWM drive circuit for rotationally driving a motor or the like in both directions is constructed as shown in FIG. In the figure, the input signal VIN supplied to the input terminal
Is supplied to the full-wave rectifier circuit 31 and full-wave rectified as shown in FIG. 7B based on the reference voltage VR applied to the reference voltage terminal.

The input signal VIN is also supplied to a comparator circuit 32 for determining the polarity, and the polarity of the voltage value is higher or lower than the reference voltage VR is determined, and the polarity determination output POL of the comparison result is obtained. Are sent to one input of the logic circuit 33. The logic circuit 33 is an AND circuit 33.
a, 33b and a knot circuit 33c. Further, a sawtooth wave generator 34 for generating a sawtooth wave WSAW synchronized with the clock signal PWM is provided as shown in FIG. 7C supplied from the clock terminal.

The full-wave rectification output of the full-wave rectification circuit 31 is PWM.
The signal is sent to one input of the comparator 35 for signal generation, and the level of the sawtooth wave output of the sawtooth wave generator 34 sent to the other input is compared and converted into a PWM signal. This PWM signal is sent to the other input of the logic circuit 33.

The logic circuit 33 separates the PWM signal into a positive polarity PWM signal and a negative polarity PWM signal on the basis of the PWM signal and the polarity discrimination output POL, and each of the separated PWM signals is a forward drive power transistor Q1 and It is supplied as a gate signal for controlling the negative direction driving power transistor Q2.

As a result, the power source VD →
Q1 → load 36 → GND or GND → load 36 → Q2
→ Apply a current in the two directions of the power supply VE to load 36
Is to drive.

FIGS. 4A and 4B show another conventional circuit. The circuit shown in FIG. 4 (a) is a conventional example in which a circuit for feeding back the voltage applied to the load 36 to the input terminal side is provided to suppress fluctuations in VD and VE. However, the driving principle for the load 36 is the circuit described above. Is the same as.

Further, the circuit shown in FIG. 1B is a circuit of a conventional example having a single power supply configuration, but the main components such as the full-wave rectifier circuit 31 are the same as those of the conventional example described above, The principle is the same.

[0009]

In the conventional PWM driving circuit as described above, the same comparator 35 is used to generate the positive direction driving PWM signal and the negative direction driving PWM signal.
A means for performing full-wave rectification of the input signal VIN relative to the reference voltage VR, obtaining only the deviation of the absolute voltage value with respect to the reference voltage VR, and transmitting this to the comparator 35, that is, the full-wave rectification circuit 31 is required. Met.

Further, it is difficult for the full-wave rectifier circuit 31 to obtain an ideal linearity due to the rising characteristics of the diode, and as shown by the solid line in FIG. A dead zone is formed in the full-wave rectifier circuit 31 due to distortion, and as shown in FIG. 5 (a), when the voltage of the input signal VIN is close to the reference voltage VR, the linearity of the output voltage is impaired and distortion occurs. There was also a problem. The present invention has been made to solve such a problem, and an object of the present invention is to provide a PWM drive circuit having a simple configuration and less distortion.

[0011]

A PWM drive circuit according to the present invention supplies power to a load from both positive and negative directions by a PWM signal obtained by comparing the levels of an input signal and a sawtooth wave signal having a constant period. In a PWM drive circuit for supply control, means for comparing the levels of an input signal and a reference voltage and generating a sawtooth wave signal of a required polarity based on the comparison result, and an input signal and a sawtooth wave signal of the required polarity. And a means for generating a PWM signal of a required polarity by comparing the levels of and and a generated PWM of the required polarity.
And a means for determining the drive direction of the load based on the signal.

[0012]

With this structure, a means such as a full-wave rectifier circuit for obtaining the difference voltage between the input signal and the reference voltage is unnecessary, and a PWM drive signal with less distortion can be obtained.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing the configuration of this embodiment and a waveform diagram for explaining the operation. In the circuit shown in FIG. 1A, the input signal VIN supplied to the input terminal is sent to one input of the comparison circuit 1 for generating a PWM signal.

The input signal VIN is also sent to a voltage comparator 2 for polarity detection. In this comparator 2, the reference voltage VR supplied from the reference voltage terminal is compared with the voltage value to obtain the reference voltage. The polarity that is higher or lower than VR is determined.

The polarity discrimination output POL of the voltage comparator 2 is P
A sawtooth wave generation circuit 3 that generates a sawtooth wave that defines the waveform width of the WM and a PWM logic circuit 4 that separates the PWM signal
Sent to one of the inputs.

The sawtooth wave generation circuit 3 is set by one polarity of the polarity discrimination output POL of the comparator 2 as shown in FIG. 2B, and one cycle of the PWM clock signal PWNCK sent from the clock input terminal. A flip-flop 3a that is reset at each rising edge, an up edge detection circuit 3b that detects the rising edge of the clock signal PWNCK, a charging / discharging capacitor 3c whose one side for generating a sawtooth waveform is connected to the reference voltage VR, Constant current circuits 3d, 3 for supplying charging currents having different polarities to the capacitor 3c
e, a switch 3f for opening and closing the constant current circuit 3d with respect to the capacitor 3c by the output POLD of the flip-flop 3a,
Further, the constant current circuit 3e is connected to the output P of the flip-flop 3a.
The switch 3h is opened and closed by the output of the OLD inverter 3g, and the switch 3i is used to discharge the capacitor 3c by the edge output of the up edge detection circuit 3b.

When the polarity of the polarity discrimination output POL of the comparator 2 is, for example, negative and the polarity discrimination output POLD of the output of the flip-flop 3a is L, the switch 3h is closed as shown in FIG. A charging current is supplied to the constant current circuit 3e side through the capacitor 3c to linearly charge the capacitor 3c.

The charge stored in the capacitor 3c is discharged by the switch 3i at the next rising edge of the clock signal PWNCK, and the charging of the clock signal PWNCK starts again. Further, when the polarity of the polarity determination output POL is changed to the positive polarity, the switch 3f is closed and the switch 3h is opened to charge the capacitor 3c in the reverse direction.

In this way, according to the polarity of the polarity discrimination output POL, as shown in FIG. 3C, in the period in which the polarity of POL is positive (POLD = H), the positive voltage is in the positive direction with respect to the reference voltage VR value.
In addition, a signal for PWM generation of a sawtooth wave whose polarity is inverted with respect to the reference voltage VR value so that it is in a negative direction with respect to the reference voltage VR value during a period in which the polarity of POL is negative (POLD = L). It generates WSOW and sends this signal output WSOW to the other input of the comparator 1.

The comparator 1 compares both the input signal VIN and the voltage of the sawtooth waveform signal WSOW, and generates a PWM signal having a width until the levels of the input signal VIN and the sawtooth signal WSOW become equal to each other. The signal is sent to the other input of the PWM logic circuit 4.

The PWM logic circuit 4 for separating the PWM signal is composed of AND circuits 4a, 4b and knot circuits 4c, 4d. For example, when the polarity of the polarity discrimination output POL is positive, the AND circuit 4a is opened to open the AND circuit. 4b is closed via the knot circuit 4d. On the contrary, when the polarity of POL is negative, the AND circuit 4a is closed and the AND circuit 4b is opened via the knot circuit 4d. Therefore, the AND circuit 4a opens, and when the AND circuit 4a receives a positive PWM signal from the comparator 1, the AND circuit 4a outputs this PWM signal.

When the AND circuit 4b is opened and a negative PWM signal is applied to the AND circuit 4b from the comparator 1, the AND circuit 4b is inverted by the NOT circuit 4c to output the AND circuit 4b.
Outputs this negative PWM signal.

An AND circuit 4a of the PWM logic circuit 4,
The output of 4b is supplied as a gate signal for controlling the positive direction driving power transistor Q1 and the negative direction driving power transistor Q2, respectively. As a result, the load 5
For power supply VD → Q1 → load 5 → GND or GND
→ Load 5 → Q2 → Power 5 is driven by passing current in the two directions of power supply VE.

As described above, in this embodiment, the input signal VIN is compared with the reference voltage VR, and when the comparison polarity is reversed, the sawtooth signal WSOW is inverted with respect to the reference voltage VR to generate the PWM signal. Is generated.

2 (a) and 2 (b) are circuit diagrams of different embodiments. In the embodiment shown in FIG. 2 (a), feedback is provided from the load 5 to the input side via the feedback circuit 6 to suppress fluctuations of the power supplies VD, VE, etc., and to stabilize the voltage supplied to the load 5. Is.

FIG. 3B shows an embodiment in which a load 5 is driven from both directions by a single power source configuration in order to save power consumption by using a battery or the like. In this embodiment, the output circuit is an output transistor Q1.
, Q2, Q3, Q4 form an H-type bridge to supply electric power to the load 5. In this embodiment as well, feedback is provided to the input side via the feedback circuit 6.

According to these embodiments, since the full-wave rectifier circuit required in the conventional circuit is unnecessary, the non-linearity due to the full-wave rectifier circuit is eliminated, and the input / output characteristics are shown in FIG.
As shown in (b), linearity is obtained over the entire range of the input signal VIN, and the output waveform is not distorted. The present invention is not limited to the above-mentioned embodiments, and can be modified and carried out without changing the gist.

[0028]

According to the present invention, the full-wave rectifier circuit for the input signal, which is required in the conventional circuit, is not required, and the circuit configuration is simplified, and the full-wave rectifier circuit that causes the distortion is not required. Therefore, it is possible to provide a PWM drive circuit with less distortion.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a configuration of an embodiment of the present invention and a waveform diagram for explaining operation.

FIG. 2 is a block circuit diagram showing the configuration of another embodiment.

FIG. 3 is a block circuit diagram showing a configuration of a conventional PWM drive circuit and a waveform diagram for explaining operation.

FIG. 4 is a block circuit diagram showing the configuration of another conventional PWM drive circuit.

FIG. 5 is a characteristic diagram showing input / output characteristics of a conventional PWM drive circuit and input / output characteristics of the PWM drive circuit of the present invention.

[Explanation of symbols]

1 ... Comparator (level), 2 ... Comparator (polarity), 3 ... Sawtooth wave generation circuit, 3a ... Flip-flop, 3b ... Up edge detection circuit 3b, 3c ... Capacitor, 3d, 3e ...
Constant current circuit, 3g ... Not circuit, 3f, 3h, 3i ... Switch 4 ... PWM logic circuit, 4a, 4b ... AND circuit, 4c, 4d ... Not circuit, 5 ... Load, 6 ... Feedback circuit, Q1 ... Forward drive Power Transistor, Q2 ... Negative direction drive power transistor, Q3, Q4 ... Output transistor, VIN ... Input signal, VR ... Reference voltage, VD, VE ...
Power supply, POL ... Polarity discrimination output, POLD ... Polarity discrimination output (flip-flop 3a output) PWMCK ... PWM clock,
WSOW ... Sawtooth wave signal.

Claims (1)

[Claims] 1. A PWM drive circuit for controlling power supply to a load from either positive or negative directions by a PWM signal obtained by comparing the levels of an input signal and a sawtooth wave signal having a constant period, and the input signal and a reference signal. A means for generating a sawtooth wave signal having a required polarity on the basis of a result of the level comparison with the voltage, and a PWM signal having a required polarity by comparing the levels of the input signal and the sawtooth wave signal having the required polarity. And a means for determining the drive direction of the load based on the comparison result and the generated PWM signal of the required polarity.