JPH0683639A - Register device - Google Patents

Abstract

(57) [Summary] [Purpose] It is possible to save and restore the context during interrupt processing without using multiple bus cycles. [Structure] The second register 12 stores in advance information necessary for interrupt processing. When the interrupt processing is accepted and the control signals 5 and 10 rise, the second register 12
Is transferred to the first register 13 and the first latch 14
The original task processing context stored in
It is transferred to the register 15. In addition, before accepting the interrupt,
The value of the first register 13 has been transferred to the first latch 14. When returning to the original task process, the control signal 6 rises, and the context saved in the third register 15 is directly transferred to the first register 13 via the second latch 16. [Effect] Overhead can be reduced, and switching to high-speed interrupt processing and restoration can be performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a register device built in a processor. More specifically, the present invention relates to a register device that realizes high-speed switching and restoration of normal task processing and interrupt processing for interrupt processing of a system using a processor.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a conventional structure of a register device incorporated in a processor. The main part of the conventional register device is the internal register 13A shown in FIG. The internal register 13A is connected to the internal bus 1 of the processor, and when the control signal 4A is applied to the internal register 13A, the data of the internal bus 1 is written in the internal register 13A. Also, control signal 5
Is applied to the internal register 13A, the internal register 1
3A writes the data value to the internal bus 1. An input / output buffer 19 is provided between the processor inside 17 and the processor outside 18, and the processor outside 18
An external memory 21 is connected to the system bus 20 of FIG. As will be described later, the external memory 21 is used to save the context (information regarding the program currently being executed by the processor) stored in the internal register 13A during interrupt processing.

Next, in a system using a processor having the register device shown in FIG. 4, (a) a process switching operation to an interrupt handler (a program dedicated to interrupt processing), which is performed when the processor accepts interrupt processing. And (b) the returning operation from the interrupt handler to the original task processing will be described below.

(A) Process Switching Operation to Interrupt Handler When the processor accepts an interrupt process, first, the context is saved before the interrupt handler process. To save this context, the internal register 13
The latest value of A (context of task processing at the time of interrupt acceptance) is output to the internal bus 1 for each register unit, and the latest value of the internal register 13A is externally output via the input / output buffer 19 and the system bus 20. Write to the memory 21.

When the saving of the context is completed, it is transferred from the outside to another register inside the processor, the stored interrupt vector is output to the internal bus 1, and the value of the interrupt vector is stored in the program in the internal register 13A. Write to a counter (not shown). As a result, the processing of the interrupt handler is started in the processor.

(B) Return to original task processing On the other hand, when the processor returns to the original task processing from the interrupt handler, it is necessary to read the context saved in the external memory 21 into the internal register 13A. Therefore, for each register unit, the context is output from the external memory 21 to the system bus 20, and the internal register 1 is output via the input / output buffer 19 and the internal bus 1.
It is read by 3A. The reading of the internal register 13A is controlled by the control signal 4A.

As described above, in the conventional register device, in the transition to the interrupt processing after receiving the interrupt processing,
The context of the tact process being executed is saved in the external memory 21, and then the process is switched to the interrupt handler or the like. Further, by re-reading the saved context into the internal register 13A, the return to the original task processing is realized.

[0008]

Since the conventional register device is constructed as described above, the following problems have occurred when switching to and returning from interrupt processing.

One of the problems is that it is necessary to write each value of the internal register to the external memory as a context and save it each time the process is switched to the interrupt handler or the like upon receipt of the interrupt process. Further, when returning to the original task processing, it is necessary to read the saved contexts into the internal registers via the system bus or the like. Therefore, if the context consisting of n pieces of register information is saved and read at the time of restoration,
One bus cycle was required.

As described above, many bus cycles are required to shift the processing to the interrupt handler and the like and to return to the original task processing by the conventional register device, and the real-time property is required for the interrupt processing and the like. In this case, the overhead of switching to an interrupt handler and returning from the interrupt handler poses a serious system problem.

The present invention has been made to solve such a problem, and an object of the present invention is to save the context necessary for accepting an interrupt process and read the context necessary for returning to the original task process on a plurality of buses. It is to provide a register device that can be realized at high speed without using cycles.

[0012]

[Means for Solving the Problems]

1) A register device according to claim 1 is built in a processor, and a first register device that stores a context of task processing before the processor accepts interrupt processing, and a register device connected to the first register device for interrupt processing A second register device in which information necessary for interrupt processing is stored in advance before reception is provided, and the second register device transfers information necessary for interrupt processing to the first register device in response to the acceptance of interrupt processing. It is something that is done.

2) A register device according to a second aspect is built in a processor and stores a context of task processing before the processor accepts interrupt processing.
A register device and a second register device connected to the first register device are provided, and the context of the task being executed by the first register device is transferred to the second register device in response to the acceptance of the interrupt process. It was done.

3) In the register device according to claim 3,
The first register device in the register device according to claim 2,
A first register storing the context and a latch connected to the first register and the second register device are provided, and the first register transfers the context to the latch immediately before the acceptance of the interrupt processing. Then
The latch transfers the transferred context to the second register device in response to the acceptance of the interrupt process.

4) A register device according to claim 4 is a first register device which is built in a processor and stores information necessary for interrupt processing, and an output end of which is connected to the first register device to accept interrupt processing. A second register device that stores the context of the task process at the time, and the second register device sets the context to the first register at the time when the processor returns from the interrupt process to the task process at the time of accepting the interrupt process. It is designed to be transferred to the device.

5) A register device according to claim 5 is built in a processor, and a first register device that stores a context of task processing currently being executed by the processor and an output end of the first register device are A second input which is connected to the first input terminal and in which information necessary for interrupt processing is stored in advance before the processor accepts the interrupt processing;
A second register having a register device and an input end connected to an output end of the first register device and an output end connected to a second input end of the first register device; and a second register The device transfers the information necessary for the interrupt processing to the first register device in response to the acceptance of the interrupt process, and the first register device determines the context of the task process at the time of the acceptance of the interrupt process in the third register. While transferring to the device, the third register device transfers the context to the first register device at the time when the processor returns from the interrupt process to the task process at the time of acceptance.

6) In the register device according to claim 6,
The first register device according to claim 6, wherein the first and second input terminals are respectively connected to the output terminal of the second register device and the output terminal of the third register device, and a first register storing a context, A latch connected between the first register and the second register device is provided. Moreover, the first register transfers the context to the latch immediately before the acceptance of the interrupt processing, and the latch is transferred from the first register. The transferred context is transferred to the third register device in response to the acceptance of the interrupt process.

[0018]

[Action]

1) In the invention according to claim 1, when the processor accepts the interrupt processing, the second register device directly transfers the information necessary for the interrupt processing to the first register device without passing through the internal bus of the processor.

2) In the invention according to claim 2, when the processor accepts the interrupt processing, the first register device directly directly passes through the internal bus of the processor.
The context of the task processing when the interrupt processing is accepted is transferred to the second register device inside the processor.
As a result, the saving of the context is executed.

3) In the invention according to claim 3, immediately before the processor accepts the interrupt processing, the context of the task processing being executed by the first register is directly transferred to the latch. Further, the latch directly transfers the context to the second register device when the interrupt process is accepted. Therefore, when the interrupt process is accepted, the first register is ready to receive the information necessary for the interrupt process.

4) In the invention according to claim 4, when the processor returns from the interrupt processing to the task processing that was being executed at the time of accepting the interrupt processing, the second register device directly does not go through the internal bus of the processor. ,
The context of the task process is transferred to the first register device.

5) In the invention according to claim 5, when the processor accepts the interrupt process, the first register device directly determines the context of the task process at the time of accepting the interrupt process without passing through the internal bus of the processor. Transfer to register device. At the same time, the second register device also directly transfers the information necessary for the interrupt processing to the first register device without passing through the internal bus of the processor. Therefore, at the same time when the interrupt processing is accepted, the information stored in the first register device is switched from the context of the task processing to the information necessary for the interrupt processing, and the context is saved at the same time. Will be completed promptly.

On the other hand, when the processor returns to the task processing when the interrupt processing is accepted, the third register device directly transfers the saved context to the first register device without passing through the internal bus of the processor. To do. Therefore, at the same time as the return, the information stored in the first register device is rewritten from the information necessary for the interrupt processing to the context of the original task processing.

6) In the invention according to claim 6, immediately before the processor accepts the interrupt processing, the context of the task processing being executed by the first register is directly transferred to the latch. Further, the latch directly transfers the context to the third register device when interrupt processing is accepted. Therefore, when the interrupt process is accepted, the first register is ready to receive the information necessary for the interrupt process.

[0025]

1 is a block diagram showing the structure of a register device according to an embodiment of the present invention. In this figure,
4 that are the same as those in FIG. 4 indicate the same components. The core part of this register device is the first register 13 and the second register.
A register 12 and a third register 15. Each of the registers 12, 13 and 15 is connected to the internal bus 1 of the processor. The configuration of each register 12, 13, 15 is as follows.

First, as will be described later, the second register 12 is for preliminarily storing information such as the start address of the interrupt handler (information necessary for interrupt processing). Two control signals 2 and 3 are applied to the second register 12. Of these, the former 2 is a control signal for writing the value of the internal bus 1 into the second register 12,
The latter 3 is a control signal for reading the value stored in the second register 12 to the internal bus 1. Also, one of the output terminals of the second register 12 is connected to the first register 13.

On the other hand, the first register 13 is a register used for the operation of the processor and corresponds to the internal register. Four types of control signals 4 to 7 are applied to the first register 13. Among them, the control signal 4 is
The control signal 7 is a control signal for writing the value of the internal bus 1 to the first register 13, and the control signal 7 is a control signal for reading the value stored in the first register 13 to the internal bus 1. On the other hand, as the control signal 5, the value stored in the second register 12 (information necessary for interrupt processing) is set to the first value.
The control signal 6 is a control signal for transferring to the register 13, and the control signal 6 is a control signal for transferring the value of the second latch 16 described later to the first register 13.

A first latch 14 is connected between the first register 13 and the third register 15. The first latch 14 is for further transferring the value transferred from the first register 13 to the third register 15. The control signal 8 applied to the main latch 14 is a bus clock signal for transferring the value stored in the first register 13 to the first latch 14. The bus clock signal 8 is also used to transfer the value stored in the third register 15 to the second latch 16.

The third register 15 is for storing a register value which is a context until the interrupt processing is started, and corresponds to a context saving register as described later. The control signals 9 to 11 applied to the third register 15 are as follows. That is, the control signal 9 is for writing the value of the internal bus 1 to the third register 15, and the control signal 10 is a control signal for transferring the value of the first latch 14 to the third register 15. The signal 11 is a control signal for writing the value stored in the third register 15 to the internal bus 1. Further, one end of the output end of the third register 15 is connected to the second latch 16. As described above, the second latch 16 is for transferring the value transferred from the third register 15 in response to the control signal 6 to the first register 13.

Here, FIG. 2 is an example in which the register device shown in FIG. 1 is specifically configured for one bit. In FIG. 2, reference numerals 1.1, 12.1 to 16.1 correspond to 1 and 12 to 16 in FIG. 1, respectively.

FIG. 3 is a timing chart showing the operation of the register device shown in FIGS. (A) to (e) of the same figure show the values of the control signals 2, 5, 10, 6 and 8, respectively. Further, (f) to (k) in the figure respectively show the value of the internal bus 1, the value of the second register 12, the value of the first register 13, the value of the first latch 14, the value of the third register 15, and the second value. The value of the latch 16 is shown. Also, the same figure (l)
Indicates the time axis. That is, time t22 is the time when the information necessary for the interrupt processing is written in the second register 12, and time t23 is the time when the processor accepts the interrupt processing. Further, time t24 is the time at which the processor returns from the processing of the interrupt handler to the task processing performed before the interrupt processing, and time t25 is the time at which the processor again accepts the interrupt processing.

Next, the operation when the processing of the processor is switched to the processing of the interrupt handler will be described with reference to FIG.

First, the task processing processed by the processor before the interrupt processing is set to the A series, and the processing of the interrupt handler processed after the interrupt processing is set to the B series.
As shown in FIG. 3, before the interrupt processing (time t23), the value of the first register 13 is changed from A1 to A2 by A.
It is a value according to the processing of the series. At this point, information necessary for the interrupt handler to be executed after accepting the interrupt processing (the start address of the handler, etc.) is stored at the time t.
It is written in the second register 12 by the control signal 2 at or before 22. In FIG. 3, at time t22, the control signal 2 rises from the L level to the H level, and the value B1 of the internal bus 1 is written in the second register 12. Moreover, in this embodiment, the control signal 8
Also at time t22, since it rises to the H level, the context value A2 stored in the first register 13 is transferred to the first latch 14.

When the processor next accepts the interrupt processing at time t23, the control signal 5 rises to the H level, and as a result, the value B1 stored in the second register 12 is transferred to the first register 13. . As a result, the value of the first register 13 changes from the context value A2 required for task processing to the value B1 required for execution of the interrupt handler, and the processor immediately starts processing of the interrupt handler. Moreover, since the control signal 10 rises to the H level in synchronization with the control signal 5, the context value A2 stored in the first latch 14 is transferred to the third register 15. That is, the value A2 of the first register 13 used for the previous task processing is saved as the context in the third register 14 at time t23 via the first latch 14. When the interrupt processing is accepted in this way, the information necessary for the interrupt processing is directly transferred from the second register 12 to the first register 13, and the context of the previous task processing held by the first register 13 is also changed. It is directly transferred to the third register 15 without going through the internal bus 1.

Similarly, the operation for returning from the interrupt handler process to the previously executed task process will be described with reference to FIG. As shown in FIG. 3, while the processing of the interrupt handler is being performed (time t23 to time t24), the value of the first register 13 changes to B1, B2, and B3 according to the processing of the interrupt handler.

At time t24, when the interrupt handler ends, the control signal 6 rises to H level and the third
The previous register value stored in the register 15 is transferred to the first register 13 via the second latch 16 as the context. The transfer from the third register 15 to the second latch 16 is executed when the control signal 8 first rises to the H level after time t23. Therefore, the value of the first register 13 is rewritten from the value B3 to A2, and the original task processing is immediately continued. In this way, even when returning to the original task processing, the context of the original task processing is directly transferred to the first register 13 without going through the internal bus 1.

Further, when the processor again accepts the interrupt processing at the time t25, the information B1 necessary for the interrupt processing stored in the second register 12 at the time t22 is also stored in the first register 13 similarly. Transferred to
Thereafter, at time t23, the same operation is performed as when the processing of the processor is switched to the processing of the interrupt handler.

As described above, in this embodiment, since the information necessary for the interrupt processing is transferred to the second register 12 in advance, the information of the interrupt handler and the like held in the processor every time the interrupt is accepted as in the conventional device. Need not be transferred to the register via the internal bus 1, and the interrupt handler can be started immediately after receiving the interrupt. Moreover, by the control signals 5 and 10 generated each time the processor accepts the interrupt processing, the register information as the context of the task processing executed before the interrupt processing is saved in the third register 15, and like the conventional device. It is not necessary to save the information as a stack on the memory outside the processor. As a result, it is not necessary to access the external memory by the number of registers to be saved, and the interrupt handler can be executed immediately after receiving the interrupt processing.

Further, when returning from the interrupt handler to the original task processing, the saved context is read from the third register 15 to the first register 13 without reading the saved context from the memory outside the processor as in the conventional device. It is possible to return from the interrupt handler without incurring the overhead of memory access.

When the nesting of interrupts is of two or more layers, switching to and returning from the interrupt handler of the first layer is performed by using this register device, and when switching the interrupt handler of the second layer and above, Control signal 5,
After masking 6 and 10, the context of the previous task processing may be saved as a stack in a memory outside the processor, as in the case of switching to the conventional interrupt processing. That is, the conventional function is used for switching to and returning from the interrupt processing of the second and higher layers.

It is also possible to use the second and third registers 12 and 15 of this register device only when switching to a specific interrupt handler that requires high-speed switching.

Further, as in the present embodiment, switching to interrupt processing and restoration are not all performed by using the second and third registers 12 and 15, but only when the information necessary for interrupt processing is transferred. Alternatively, the first and third registers 13 and 15 may be used, or the first and third registers 13 and 15 may be used only to save or restore the context of the task processing. In these cases, transfer of information via the internal bus 1 will be partially used.

[0043]

【The invention's effect】

1) In the invention according to claim 1, the information necessary for the interrupt processing performed each time the interrupt processing is accepted is written in the internal register directly from the second register device to the first register device without using the internal bus. It can be achieved by writing to. As a result, the overhead at the time of writing can be reduced, which can greatly contribute to the speeding up of the switching operation to the interrupt processing.

2) In the inventions according to claims 2 and 3, after accepting the interrupt processing, the context saving of the current task processing required for switching to the interrupt processing is accessed to the memory outside the processor like the conventional apparatus. This can be realized promptly by directly transferring the data from the first register device to the second register device without accessing the bus inside the processor. Moreover, the saving can be realized immediately after accepting the interrupt processing. As described above, the present invention can significantly reduce the overhead at the time of saving the context, and can greatly contribute to the realization of high-speed switching to the interrupt processing.

Further, since the saving of the context can be completed immediately, it becomes possible to promptly write the information necessary for the interrupt processing required as the next processing to the first register device.

3) Further, in the inventions according to claims 3 and 6, since the context of the task processing stored in the first register in advance just before the acceptance can be transferred to the latch, the saving of the context and the interrupt processing It is possible to surely execute writing of information necessary for the same as the reception of the interrupt processing.

4) In the invention according to claim 4, since the context of the task process at the time of accepting the interrupt process is stored in the second register device directly connected to the first register device, A return to the task processing can be realized immediately by simply transferring the context directly to the first register device. At that time, since access to the external memory or access to the internal bus is not required, the overhead at the time of restoration can be significantly reduced, and after the restoration, it is possible to immediately shift to the original task processing. . As described above, the present invention has the effect of speeding up recovery from interrupt processing.

5) In the invention according to claims 5 and 6, after the interrupt processing is accepted, the context of the task processing is directly transferred from the first register device to the third register device, thereby immediately completing the saving of the context. You can At this time, since the third register device inside the processor is used, there is no need to access the external memory, and since it is not necessary to access the bus inside the processor, the overhead required for context saving can be greatly reduced. Further, information necessary for interrupt processing can be written in the first register device by directly transferring the information from the second register device inside the processor to the first register device without accessing the internal bus. The overhead required for the writing can be significantly reduced as compared with the conventional device.

Moreover, when returning from the interrupt processing to the original task processing, it is sufficient to directly transfer the context of the task processing from the third register device to the first register device, so that the overhead required for the recovery is significantly increased. Can be reduced to

As described above, the present invention can realize both high-speed switching to interrupt processing and high-speed recovery from interrupt processing.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a register device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of a 1-bit register device.

FIG. 3 is a timing chart showing the operation of the register device.

FIG. 4 is a block diagram showing a configuration of a conventional register device.

[Explanation of symbols]

 1 Internal Bus 12 2nd Register 13 1st Register 14 1st Latch 15 3rd Register 16 2nd Latch

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[Procedure amendment]

[Submission date] January 11, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0005

[Correction method] Change

[Correction content]

[0005] When the saving of the context is finished, the beginning of the interrupt handler from the outside in accordance with the interrupt <br/> seen vector address
Read the value into a program counter (not shown) in the internal register 13A. As a result, the processing of the interrupt handler is started in the processor.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction content]

As described above, in the conventional register device, in the transition to the interrupt processing after receiving the interrupt processing,
The context of the task being executed is saved in the external memory 21, and then the process is switched to the interrupt handler or the like. In addition, the context saved is stored in the internal register 13A.
By re-reading into, the return to the original task processing is realized.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction content]

One of the problems is that each time the processing is switched to the interrupt handler or the like upon receipt of the interrupt processing, it is necessary to write and save each value of the internal register as a context in the external memory. Further, when returning to the original task processing, it is necessary to read the saved contexts into the internal registers via the system bus or the like. Therefore, if save the context of n pieces of register information, the and reads at the time of return, 2
N bus cycles were required.

[Procedure amendment 4]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 3

[Correction method] Change

[Correction content]

[Figure 3]

Claims (6)

[Claims] 1. A register device built in a processor, the first register device storing a context of a task process before the processor accepts an interrupt process, and the interrupt process connected to the first register device. A second register device in which information necessary for the interrupt processing is stored in advance before the acceptance of the interrupt request, and the second register device stores the information necessary for the interrupt process in the first register in response to the acceptance of the interrupt process. Register device characterized by transferring to a device. 2. A register device built into a processor, the first register device storing a context of task processing before the processor accepts an interrupt process, and a second register connected to the first register device. A first register device, and the first register device sets the context of the task process being executed in response to the interrupt process to the second context.
A register device characterized by transferring to a register device. 3. The first register device comprises a first register storing the context, and a latch connected to the first register and a second register device, the first register being the interrupt. The context is transferred to the latch immediately before the acceptance of processing, and the latch transfers the context transferred from the first register to the second register device in response to acceptance of the interrupt processing. The register device according to claim 2. 4. A register device built in a processor, the first register device storing information necessary for interrupt processing, and an output terminal thereof connected to the first register device, when the interrupt processing is accepted. A second register device that stores the context of the task processing in the above, and the second register device stores the context in response to a time point when the processor returns from the interrupt process to the task process at the time of accepting the interrupt process. A register device for transferring to a first register device. 5. A register device built in a processor, the first register device storing a context of task processing currently being executed by the processor, and its output end being a first input of the first register device. A second device which is connected to the end and stores information necessary for the interrupt processing in advance before the processor accepts the interrupt processing.
A third register device having an input end connected to an output end of the first register device and an output end connected to a second input end of the first register device; The device transfers information necessary for the interrupt processing to the first register device in response to the acceptance of the interrupt process, and the first register device responds to the acceptance of the interrupt process in the context of the task process at the time of acceptance. Is transferred to the third register device, while the third register device transfers the stored context to the first register device in response to a time point when the processor returns from the interrupt process to the task process at the time of acceptance. A register device characterized by: 6. The first register device has a first and a second input end connected to an output end of the second register device and an output end of the third register device, respectively, and a first storing the context. A register and a latch connected between the first register and a second register device, wherein the first register transfers the context to the latch immediately before the reception of the interrupt processing, and the latch 6. The register device according to claim 5, wherein said context transferred from said first register is transferred to said third register device in response to the acceptance of said interrupt processing.