JPH0683733A - Reception control system - Google Patents

Abstract

PURPOSE:To prevent the generation of over-run in a reception control part due to the delay of turning processing of a descriptor and to improve the using efficiency of a receiving buffer in an external storage area. CONSTITUTION:A receiving circuit constituted of a DMA controller 1-9 and a reception control part 1-17 includes a circuit 1-15 for storing the information of a receiving buffer area and the information of a descriptor 1-1 included in an external storage area in a register built in a DMA controller and computing the leading address and idle area of a receiving buffer. Even at the time of receiving plural frames having respectively different frame lengths, respective frames are DMA-transferred to one buffer area without tuning the descriptor, so that the generation of over-run due to the delay of data transfer in the control part 1-17 can be prevented and a receiving buffer using area in an external storage area to which a received frames are to be transferred can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving circuit control system, and more particularly to a receiving control system using a descriptor.

[0002]

2. Description of the Related Art Conventionally, in a receiving system of a communication system, when a DMA controller continuously reads received data from a receiving circuit and transfers it to a buffer area in an external storage area, a host system controls the DMA controller in real time. In order to prevent a decrease in system efficiency due to this, DM by descriptor control described below is used.
A control method of the A controller has been proposed.

For example, in a communication system, a high level data link control procedure (hereinafter referred to as HDL)
(Referred to as C), the received frame is received by the descriptor control as shown in FIG. 3 by a plurality of receiving buffers 3-7, 3-8, 3-in the external storage area.
DMA transfer to 9. As shown in FIG. 3, the host system previously sets information of a plurality of descriptors in a continuous area on the external storage area according to a predetermined descriptor format. The format of each descriptor 3-1 is the command area 3-2 that stores control information for the DMA controller 3-10, and the start addresses of the individual reception buffers 3-7, 3-8, and 3-9 that store transfer data. It includes an address area 3-3, a transfer size area 3-4 for storing the number of transfer data, and a status area 3-5 for storing the execution result of the DMA transfer.

The host system uses the descriptor address as the start address of the descriptor to be executed first.
Set in register 3-11, DMA controller 3-1
Start 0. The DMA controller 3-10 DMAs the set value of the descriptor address register 3-11.
In the address register 3-13, the size of the descriptor specified in advance is set in the DMA size register 3-
14 respectively.

The DMA controller 3-10 uses the address set in the DMA address register 3-13 to DM
The DMA transfer is started by the number of data set in the A size register 3-14. By this first DMA transfer, the command area 3-2, the address area 3-3 and the transfer size area 3-4 of the designated descriptor 3-1 on the external storage area are read into the DMA controller 3-10.

The DMA controller 3-10 uses the read information in the command area 3-2 as control register 3-12 and the read information in the address area 3-3 as DMA address register 3
-13, transfer size area 3-4 information in DMA size
The register 3-14 is set and the DMA transfer is started again. By this second DMA transfer, the reception controller 3-1
Each data of the reception frame stored in the reception data FIFO 3-17 received by the
Receive buffer area 3 on the external storage area specified by -1
Stored in -6.

When the transfer of the received data is completed by the second DMA transfer, the DMA controller 3-10 transfers the number of data actually transferred by the second DMA transfer to the size area 3-4 as the third DMA transfer. Information on the execution result of the DMA transfer and the received frame is DMA-transferred to the status area 3-5. The data transfer to the buffer area of the received frame is completed by the series of operations by the above-described three DMA transfers.

If the received frame is large, it may not be possible to store it in one receive buffer 3-7. If chaining by descriptors is further specified by the control information stored in the control register 3-12, the DMA controller 3-10 sets the address of the descriptor following the descriptor 3-1 to the DMA address register 3-.
13 is set, and the descriptor information stored in the address following the descriptor 3-1 is read. Further, according to this information, the DMA transfer for transferring the remaining received frames to the designated buffer area is activated.

Thus, by chaining the descriptors, it is possible to transfer one reception frame to a plurality of reception buffers designated by a plurality of descriptors. The chaining of descriptors is continuously executed until the end of chaining is designated by the control information designated in the command area 3-2 of the descriptor.

[0010]

For example, in HDLC, a received I frame is transferred to a buffer area designated by one descriptor in order to avoid overrun of a received information frame (hereinafter referred to as I frame). In this case, since each buffer must be prepared according to the maximum frame length, a short frame such as a monitoring frame (hereinafter referred to as S frame) or an unnumbered frame (hereinafter referred to as U frame) When it is received, it will be transferred to a large buffer. Therefore, there is a drawback that the utilization efficiency of the external storage area is reduced.

To avoid this, one received frame is transferred to a plurality of buffer areas by chaining descriptors. However, according to the above-described conventional method, when each field of one received frame is transferred to a plurality of buffer areas by chaining descriptors, DM is performed twice during transfer to each buffer area.
Since A transfer is included, the time interval becomes large, and reception overrun is likely to occur in high-speed communication.

As a result, the efficiency of use of the external storage area decreases, the overhead of the host system increases due to the retransmission processing of the lost frame from the transmitting side, and the throughput on the line side decreases. There is a drawback that the execution efficiency of is reduced.

An object of the present invention is to provide a reception control system which prevents overrun and improves the use efficiency of the reception buffer.

[0014]

In order to achieve the above object, the reception control method according to the present invention comprises a first storage means,
A reception control method comprising MDA transfer of a reception frame according to a plurality of descriptors set in advance in an external storage area, the reception control method including a second storage means, a third storage means, and an arithmetic circuit, The first storage means stores the start address of the descriptor, the second storage means stores the start address of the reception buffer area for storing the reception frame, and the third storage means. Is for storing control information stored in the descriptor, and the arithmetic circuit is for determining the presence or absence of the reception buffer area based on the stored contents,
The control information stored in the plurality of descriptors stored in the external storage area transfers the plurality of reception frames to a continuous area of the reception buffer by one DMA transfer based on the information of each one of the descriptors. To do.

The third storage means stores the start address and the end address.

[0016]

Even when a plurality of frames having different frame lengths are received, each frame is DMA-transferred to one buffer area without descriptor chaining, so that overrun due to delay of data transfer in the reception control unit can be prevented. It is possible to reduce the use area of the reception buffer of the external storage area for transferring the reception frame.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing the system configuration of Embodiment 1 of the present invention. In the figure, 1-1 is one of a plurality of descriptors set in the external storage area 1-17, and the command area 1-2 and the address area 1-
3, transfer size area 1-4, and status area 1-5
It consists of

DM controlled by the above-mentioned descriptor
The frame length is variable by the A controller 1-10.
When receiving a frame, a fixed-length U frame, or an S frame and storing it in a designated buffer area, the host system first sets a descriptor for frame reception. The command area 1-2 includes descriptor control information, the address area 1-3 does not indicate the start address of the reception buffer, but the end address of the entire reception buffer area 1-6, and the transfer size area 1-4 indicates the received frame. Set the maximum frame length. Further, the start address of the entire reception buffer area 1-6 is set in the reception buffer address register 1-15.

After that, the DMA controller 1-10 is activated, and a plurality of descriptors in the continuous external storage area 1-17 are used to specify the received frame by each descriptor. −
Transfer to 7, 1-8, 1-9. In the following, DMA transfer is continuously executed by chaining each descriptor,
The operation when transferring to the reception buffer area 1-6 will be described.

The host system uses the descriptor address as the start address of the descriptor to be executed first.
Set in register 1-11, DMA controller 1-1
Start 0. The DMA controller 1-10 DMAs the set value of the descriptor address register 1-11
In the address register 1-13, the size of the descriptor specified in advance is set in the DMA size register 1-
14 respectively. DMA controller 1-1
0 starts DMA transfer by the number set in the DMA size register 1-14 from the address set in the DMA address register 1-13. Descriptor 1 designated in the external storage area 1-17 by this DMA transfer
-1 command area 1-2, address area 1-3, and transfer size area 1-4 are read into the DMA controller 1-10, and the control register 1-12, the DMA address register 1-13, and the DMA size register, respectively. 1-1
4 is transferred.

Information of the descriptor is stored in the control register 1-
12, the end address of the reception buffer area 1-6 stored in the DMA address register 1-13 by the address arithmetic circuit 1-16 when transferred to the DMA address register 1-13 and the DMA size register 1-14. When,
The sum of the DMA size register 1-14 and the receive buffer address register 1-15 is compared. If the end address of the receive buffer area 1-6 is larger, it is determined that there is still space in the receive buffer area 1-6, and the DMA address register 1-13 stores the receive buffer area which is the start address of the receive buffer area 1-7. Address register 1-
Transfer the contents of 15. Thereafter, as the second DMA transfer, the reception data FIF received by the reception control unit 1-18 is received.
Each data of the reception frame stored in O1-19 is DMA-transferred to the reception buffer area 1-6 on the designated external storage area. That is, the DMA controller 1-1
0 starts the DMA transfer to the reception buffer 1-7 designated by the control register 1-12, the DMA address register 1-13, and the DMA size register 1-14.

In this way, when the DMA transfer by the number set in the DMA size register 1-14 is completed or the final data of the received frame is completed, the second DMA transfer is performed as the third DMA transfer. The head address of the DMA transfer, the transfer size number, and the status of the execution result are written back to the address area 1-3, the transfer size area 1-4, and the status area 1-5 of the descriptor by the DMA transfer. Also, the receive buffer 1- that stores the next received frame
8 address, that is, the address obtained by adding the transfer size number to the address of the second DMA transfer, is calculated by the address calculation circuit 1-16, and the received buffer address
Write back to register 1-15.

Receive buffer area 1-6 for one I frame or U / S frame by the above-mentioned three DMA transfers
Transfer to. After this, the DMA controller 1-
It is possible to transfer the next frame to be received by rereading the next chained descriptor in 10.

As described above, the DMA controller has the reception buffer area 1- regardless of the type of the received frame.
It is possible to transfer a plurality of received frames in succession to 6. Further, one received frame is transferred by one descriptor information.

Therefore, the delay of data transfer caused by transferring one frame to a plurality of buffer areas by descriptor chaining can be eliminated, and reception overrun in the reception control unit 1-18 can be avoided. Also, since I-frames of arbitrary length, and short fixed-length frames such as U-frames and S-frames are transferred to the continuous reception buffer area 1-6, it is possible to improve the efficiency of use of the external storage area.

Therefore, it is possible to improve the system efficiency such that the number of frame retransmissions in the partner station is reduced, the overhead of the host system is reduced, and the line efficiency is improved.

(Embodiment 2) FIG. 2 is a block diagram showing the system configuration of Embodiment 2 of the present invention. In the first embodiment, the start address of the entire receive buffer area is set in the receive buffer address register, but in the second embodiment, the start address and the end address are set.

Reference numeral 2-1 in the figure is one of a plurality of descriptors set in the external storage area 2-18, and includes a command area 2-2, a transfer size area 2-3, and an address area 2-4.
And a status area 2-5.

DM controlled by the above-mentioned descriptor
The frame length is variable by the A controller 2-10.
When receiving a frame, a fixed-length U frame, or an S frame and storing it in a designated buffer area, the host system first sets a descriptor for frame reception. The descriptor control information is set in the command area 2-2, and the maximum frame length of the received frame is set in the transfer size area 2-3. Receive buffer area 2
-6 Set the start address and end address of the whole to the receive buffer / start address register 2-15 and the receive buffer / end address register 2-16, respectively.

Thereafter, the DMA controller 2-10 is activated, and a plurality of consecutive descriptors in the external storage area 2-18 designate the received frame by the descriptors, and each reception buffer 2 in the external storage area 2-18. −
Transfer to 7, 2-8, 2-9. In the following, DMA transfer is continuously executed by chaining each descriptor,
The operation of transferring to the reception buffer area 2-6 will be described.

The host system uses the descriptor address as the start address of the descriptor to be executed first.
Set in register 2-11, DMA controller 2-1
Start 0. The DMA controller 2-10 DMAs the set value of the descriptor address register 2-11.
The address register 2-14 stores the predetermined descriptor size in the DMA size register 2-
13 respectively. DMA controller 2-1
0 starts the DMA transfer by the number set in the DMA size register 2-13 from the address set in the DMA address register 2-14. Descriptor 2 designated in external storage area 2-18 by this DMA transfer
-1 command area 2-2, transfer size area 2-3 is D
It is read by the MA controller 2-10, and the control register 2-12 and the DMA address register 2-13 are respectively read.
Transferred to.

Information of the descriptor is control register 2-
12. When transferred to the DMA size register 2-13, the end address of the receive buffer area 2-6 stored in the receive buffer end address register 2-16 by the address calculation circuit 2-17, and the DMA size register 2-13 and reception buffer / start address register 2
The sum of the start addresses of the reception buffer areas 2-6 stored in -15 is compared. If the end address of the reception buffer area 2-6 is larger, it is determined that there is still space in the reception buffer area 2-6, and the DMA address register 2-
The contents of the reception buffer / start address register 2-15, which is the start address of the reception buffer 2-7, are transferred to 14. After this, as the second DMA transfer, the reception control unit 2-
The respective data of the reception frame received by 19 and stored in the reception data FIFO 2-20 are DMA-transferred to the reception buffer area 2-6 on the designated external storage area. That is, the DMA controller 2-10 includes a control register 2-12, a DMA size register 2-13, and a DM.
The DMA transfer to the reception buffer 2-7 designated by the A address register 2-14 is started.

In this way, when the DMA transfer of the number set in the DMA size register 2-13 is completed or the transfer of the final data of the received frame is completed, the second DMA transfer is performed as the second DMA transfer. The top address of the DMA transfer, the transfer size number, and the status of the execution result are written back to the transfer size area 2-3, the address area 2-4, and the status area 2-5 of the descriptor by the DMA transfer. In addition, a reception buffer 2-for storing the next reception frame
8 start address, that is, an address obtained by adding the transfer size number to the start address of the second DMA transfer, is calculated by the address calculation circuit 2-17, and the reception buffer address
Write back to register 2-15.

Reception buffer area 2-6 for one I frame or U / S frame by the above-mentioned three DMA transfers
Transfer to. After this, DMA controller 2-
It is possible to transfer the next frame to be received by rereading the next chained descriptor in 10.

As described above, the DMA controller has the reception buffer area 2- regardless of the type of the received frame.
It is possible to transfer a plurality of received frames in succession to 6. Further, one received frame is transferred by one descriptor information.

Therefore, the delay of data transfer caused by transferring one frame to a plurality of buffer areas by descriptor chaining can be eliminated, and reception overrun in the reception control unit 2-19 can be avoided. Further, since I-frames of arbitrary length, and short fixed-length frames such as U-frames and S-frames are transferred to the continuous reception buffer area 2-6, it is possible to improve the use efficiency of the external storage area.

Therefore, it is possible to improve the system efficiency such that the number of frame retransmissions in the partner station is reduced, the overhead of the host system is reduced, and the line efficiency is improved.

[0039]

As described above, according to the present invention, when a fixed-length or variable-length frame is received and transferred to the buffer area designated by the descriptor, one descriptor is used regardless of the type of the received frame. Since transfer is possible, utilization efficiency of the external storage area is improved.

Further, when the data in each buffer area is DMA-transferred to and from the reception controller, the execution interval of the DMA transfer due to the chaining of a plurality of descriptors can be neglected, so that even the high-speed communication can be received. It is possible to prevent reception overrun in the control unit. Therefore, it is possible to improve the system efficiency such as improving the communication line efficiency while reducing the overhead of the host system resetting the descriptor by retransmitting the frame in the partner station.

[Brief description of drawings]

FIG. 1 is a block diagram showing a system configuration of a first embodiment of the present invention.

FIG. 2 is a block diagram showing a system configuration of a second embodiment of the present invention.

FIG. 3 is a block diagram showing a system configuration of a conventional example.

[Explanation of symbols]

 1-1 Descriptor 1-2 Command area 1-3 Address area 1-4 Transfer size area 1-5 Status area 1-6 Receive buffer area 1-7 Receive buffer 1-8 Receive buffer 1-9 Receive buffer 1-10 DMA Controller 1-11 Descriptor Address Register 1-12 Control Register 1-13 DMA Address Register 1-14 DMA Size Register 1-15 Receive Buffer Address Register 1-16 Address Operation Circuit 1-17 External Storage Area 1 -18 Reception control section 1-19 Reception data FIFO 2-1 Descriptor 2-2 Command area 2-3 Transfer size area 2-4 Address area 2-5 Status area 2-6 Reception buffer area 2-7 Reception buffer 2-8 Receive buffer 2-9 Receive buffer 2-1 DMA controller 2-11 Descriptor address register 2-12 Control register 2-13 DMA size register 2-14 DMA address register 2-15 Receive buffer / start address register 2-16 Receive buffer / end address register 2 -17 Address calculation circuit 2-18 External storage area 2-19 Reception control section 2-20 Reception data FIFO

Claims (2)

[Claims] 1. A first storage means and a second storage means,
A reception control method that includes a third storage unit and an arithmetic circuit, and MDA-transfers a reception frame according to a plurality of descriptors that are continuously set in advance in an external storage area. A second storage unit stores a start address of the descriptor, a second storage unit stores a start address of a reception buffer area that stores the reception frame, and a third storage unit stores the descriptor in the descriptor. The arithmetic circuit determines whether or not there is the reception buffer area based on the stored contents, and the control circuit stores the control information stored in the plurality of descriptors stored in the external storage area. According to the information, the plurality of reception frames are transferred to the reception buffer in one DMA transfer by the information of one descriptor each. Reception control method, characterized by transferring the contiguous area. 2. The reception control system according to claim 1, wherein the third storage means stores a start address and an end address.