JPH0685554A - Semiconductor transmitter - Google Patents

Abstract

(57) [Abstract] [Purpose] When the gate bias of the Ga As FET is out of the proper value range, the drain bias voltage applied to the drain of the Ga As FET is cut off,
Prevents destruction of As FET. [Structure] A source follower is connected to the gate of the Ga As FET, a gate bias voltage is detected and input to a window comparator. When the gate bias voltage is out of the proper range, the window comparator generates an abnormal signal. The drain bias voltage is Ga through the cutoff circuit.
Although applied to the drain of the As FET, when the gate bias voltage is out of the proper value range and an abnormal signal occurs, the cutoff circuit cuts off the application of the drain bias voltage to the drain of the Ga As FET.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply for a semiconductor transmitter.

[0002]

2. Description of the Related Art FIG. 3 is a diagram showing a conventional semiconductor transmitter. 1 gallium arsenide field effect transistor in FIG. (G a A s F ield E ffect T ra
nistor; hereinafter referred to as Ga As FET), 4
Is a gate bias circuit for supplying a gate bias voltage to this Ga As FET 1, and 12 is a Ga As FET
1 is a drain bias circuit that supplies a drain bias voltage to the first circuit.

The conventional semiconductor transmitter is constructed as described above, and the gate bias voltage which is a constant negative voltage generated in the gate bias circuit 4 is applied to the gate of the Ga As FET1. The drain bias voltage, which is a constant positive voltage generated by the drain bias circuit 12, is Ga.
It is applied to the drain of As FET1.

[0004]

In the conventional semiconductor transmitter as described above, the gate bias circuit 4 fails to apply a proper value of the gate bias voltage to the gate of the Ga As FET 1, particularly a state close to the positive voltage. And G
When a drain bias voltage is applied to the drain of the As As FET 1, the characteristics of the Ga As FET 1 are G
a Excessive current flows in the drain of As FET1, causing Ga
There was a problem of destroying the As FET1.

The present invention has been made to solve the above problems, and when an abnormality occurs in the gate bias circuit and the gate bias voltage is out of the proper range,
The purpose is to obtain a power supply that cuts off the drain bias voltage and prevents the Ga As FET from being destroyed.

[0006]

Means for Solving the Problems A semiconductor transmission device according to the present invention, low frequency power amplification field-effect transistor a gate bias voltage to a source follower [F ield E ffect T ransisto
r; hereinafter referred to as FET], current amplification is performed, the output is input to the window comparator, and when the gate bias voltage is out of the proper value range, an abnormal signal is output to disconnect the circuit. Drive, Ga As
The drain bias voltage applied to the FET 1 is cut off.

Further, when the drain bias voltage is cut off by the cutoff circuit, it is necessary to increase the variation time of the gate bias voltage so as to facilitate the time cutoff.
Add a capacitor to the gate of the FET.

[0008]

In the semiconductor transmitter configured as described above, the gate bias voltage applied to the Ga As FET is the FE for low frequency power amplification which constitutes the source follower.
Connect to the gate of T. The source follower has a high input impedance due to its elemental and circuit properties, and its output power is almost equal to the input voltage. Therefore, when a gate bias voltage outside the proper range is applied to the gate of the Ga As FET due to a failure of the gate bias circuit, the gate bias voltage is passed through the source follower composed of the low frequency power amplification FET, Is input to the sensor and an abnormal signal is generated
s FET drain bias voltage is cut off, and Ga
The drain bias voltage is not applied to the drain of the As FET to prevent the Ga As FET from being destroyed.

In addition, by adding a large-capacity capacitor to the gate of the Ga As FET to make the fluctuation time for the gate bias voltage to change outside the proper range,
This facilitates the blocking of the drain bias voltage by the blocking circuit in terms of time.

[0010]

EXAMPLES Example 1. FIG. 1 is a diagram showing an embodiment of the present invention, in which 1, 4, 12 are exactly the same as the above-mentioned conventional device. 2 is a drain bias terminal connected to the drain of the Ga As FET 1; 3 is a grounded drain bias ground terminal; 5 is an abnormality detection terminal connected to the gate of the Ga As FET 1; 6 is a grounded abnormality detection ground terminal; Is an abnormality input terminal connected to the abnormality detection terminal 5,
8 is an abnormal input return terminal connected to the abnormal detection ground terminal 6 and grounded, 9 is a low frequency in which the abnormal input terminal 7 is connected to the gate, the drain is connected to the bias voltage V _DS , and the source is grounded through an additional resistor. A power amplification FET, 10 is a load resistance in which one electrode is connected to the source of the low frequency power amplification FET 9 and the other electrode is grounded, and 11 is an input voltage of the gate bias voltage of the Ga As FET. A window comparator that outputs an abnormal signal when the value is out of the proper range, 13 is a drain bias output terminal connected to the drain bias terminal 2, 14 is a drain bias output return terminal connected to the drain bias ground terminal 3, and 15 is a window The output of the comparator 11 and the drain bias voltage generated by the drain bias circuit 12 are input to the window. Cutoff circuit output abnormal signal when outputting the drain bias voltage is to shut off the drain bias voltage when the output does not output an abnormality signal of the comparator 11, 16 is a transmitter unit, 17 is a power supply unit.

In the semiconductor transmitter configured as described above, the gate bias voltage applied to the gate of the Ga As FET 1 is input to the source follower composed of the low frequency power amplification FET 9 and the load resistor 10. . The source follower has a high input impedance and a voltage gain of about 1 as a device used and a circuit property. Therefore, the output voltage of the source follower is Ga As
It can be considered to have the same value as the gate bias voltage applied to the FET1. Further, the window comparator 11 is set to output an abnormal signal when the input voltage is out of the proper range of the gate bias voltage of the Ga As FET1. Therefore, due to an abnormality of the gate bias circuit 4, Ga
When the gate bias voltage applied to the gate of As FET1 is out of the proper range, the window comparator 11 outputs an abnormal signal, and the cutoff circuit 15 is generated in the drain bias circuit 12 and applied to the drain of Ga As FET. Ga to cut off the drain bias voltage
It prevents an excessive current from flowing into the As FET1 and destroying it.

Example 2. FIG. 2 shows G in the first embodiment.
a Large-capacity capacitor 18 at the gate of As FET1
The fluctuation of the gate bias voltage applied to the gate of the GaAs FET 1 is greater than that in the case where the capacitor 18 is not provided even if the gate bias voltage is out of the proper value range due to a failure of the gate bias circuit 4 or the like. It is possible to lengthen the time and facilitate the interruption of the drain bias voltage by the interruption circuit 15 in terms of time.

[0013]

Since the present invention is constructed as described above, it has the following effects.

When the gate bias voltage of the Ga As FET is out of the proper voltage range, it is detected by the source follower and the window comparator, and the cutoff circuit is driven to cut off the drain bias voltage of the Ga As FET. Can be prevented from being destroyed.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a second embodiment of the present invention.

FIG. 3 is a diagram showing a conventional semiconductor transmitter.

[Explanation of symbols]

 1 Ga As FET 2 Drain bias terminal 3 Drain bias ground terminal 4 Gate bias circuit 5 Abnormality detection terminal 6 Abnormality detection grounding terminal 7 Abnormal input terminal 8 Abnormal input return terminal 9 Low frequency power amplification FET 10 Load resistance 11 Wind comparator 12 Drain Bias circuit 13 Drain bias output terminal 14 Drain bias output return terminal 15 Interruption circuit 16 Transmitter section 17 Power supply section 18 Capacitor

Claims (2)

[Claims] 1. A gallium arsenide field effect transistor for amplifying a high frequency, a drain bias terminal connected to the drain of the gallium arsenide field effect transistor, a grounded drain bias ground terminal, and the gallium arsenide field effect transistor. A gate bias circuit connected to the gate of the transistor to generate a gate bias voltage, an abnormality detection terminal connected to this gate bias voltage, a grounded abnormality detection ground terminal, and an abnormality input terminal connected to the abnormality detection terminal. And the abnormal input return terminal connected to the abnormal detection ground terminal, the abnormal input terminal connected to the gate, the source grounded via a load resistor, the drain connected to the bias voltage, the gate bias voltage amplified by current Field effect type for low frequency power amplification output as bias detection signal A transistor and a window comparator which receives the gate bias detection signal and outputs an abnormal signal when the gate bias detection signal is out of the range of the proper gate bias voltage,
A drain bias circuit for generating a drain bias voltage of the gallium arsenide field effect transistor; a drain bias output terminal connected to the drain bias terminal; a drain bias output return terminal connected to the drain bias ground terminal; When the output of the window comparator and the drain bias voltage are input and the output of the window comparator does not output an abnormal signal, the drain bias voltage is output, and when the output of the window comparator becomes the above abnormal signal, the drain bias voltage is cut off. A semiconductor transmitter comprising a drain bias output and a cutoff circuit connected to the drain bias output return terminal. 2. The semiconductor transmitting device according to claim 1, wherein a capacitor is added to the gate of the gallium arsenide field effect transistor.