JPH068940B2 - Camera display - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device for a camera, and more particularly to a display device for displaying an aperture value of the camera.

2. Description of the Related Art Conventionally, in a camera that calculates and displays an aperture value, a camera that displays the aperture value of a taking lens displays the aperture value determined by calculation or setting by using the aperture value in units of predetermined EVs. What is known is. For example, in a camera adapted to display an aperture value in units of 0.5 EV, the display sequence is ... 2.8,
They are 3.4, 4, 4.8, 5.6 ... However, in the above conventional camera, when the determined aperture value is the aperture value of the lens, an aperture value different from the actual aperture value may be displayed. For example, when a lens having an open aperture value of 4.5 is set and the lens is set to be open, the open aperture value is only displayed as 4.8. Therefore, data different from the open aperture value data of the lens used is displayed. Also, for example, when a lens with an open aperture value of 3.5 is attached, the open aperture value is displayed as 3.4, and a value that cannot be achieved with that lens is actually displayed. become.

The above display not only makes the photographer feel distrust of the displayed data, but may misunderstand that a failure has occurred, and eventually interrupt the photographing operation.

The present invention has been made to solve the above-described inconvenience, and an object of the present invention is to provide a highly reliable display device for a camera that can correctly display the open aperture value of a lens.

Means for Solving the Problems In order to achieve the above object, in the present invention, a taking lens, an aperture value determining means for determining an aperture value of the taking lens by calculation or setting, and an aperture value determining means. In a camera equipped with a display unit for displaying the selected aperture value, the data output unit for outputting data indicating the open aperture value of the taking lens, the aperture value determined by the aperture value determining unit, and the data output unit When the determined aperture value is different from the open aperture value according to the comparison result of the output aperture value and the comparison result of the comparison means, the determined aperture value is set to a predetermined value E.
Display is performed by using the aperture value in units of V, and when the determined aperture value is equal to the open aperture value, the display means is controlled to display the open aperture value. .

By this, when the aperture value determined by calculation or setting is not the open aperture of the lens, the aperture value is displayed in units of predetermined EV. On the other hand, when the determined aperture value is the lens aperture value, the lens aperture value at that time is displayed.

Embodiment FIG. 1 is a diagram showing the appearance of a camera to which the present invention is applied. Reference numeral 1 is a camera body, 2 is a shutter button, 3 is an interchangeable lens, and the data of the lens, for example, an open aperture value, is included in the interchangeable lens 3. There is provided a device that outputs data indicating the above as an electric signal to the camera body side. Further, the shutter button 2 is provided with a photometric switch S1 and a release switch S2 which operate according to the amount of pressing the button by a known method.

An external display unit 4 displays the calculated EV value and operation mode, and various other data described in detail later.

Reference numeral 5 denotes a finder, and an internal display unit 6 (see FIG. 2) for displaying data displayed on the external display unit 4 is provided in the field of view of the finder 5.

SM is a main switch.

FIG. 2B shows the details of the display on the external display unit 4, and there is PROGRAMS for AE mode display from above. PROGRAM is displayed when the AE mode is the program mode (hereinafter, referred to as P mode), S is turned off, A is displayed when the aperture priority mode (hereinafter, referred to as A mode), and PROG
Turn off R and MS. In the manual mode (hereinafter, referred to as M mode) and the shutter speed priority mode (hereinafter, referred to as S mode), M and S are displayed, respectively. Below that is the ISO mark in the ISO mode, and immediately below is a 7-segment 4-digit SS, ISO, CTR display section,
On the right side thereof, there is a setting instruction mark TA1. Below that, there is a 7-segment 2-digit F, +/- display part across the display part of the bar that is simply turned off when the main switch SM of the camera is turned off. There is an instruction mark TA2. An aperture value determination mark F is provided on the left of the two digits, and a +/- mark, which is a code when overriding is set, is provided at the left end.

Further, FIG. 2c shows details of the display on the internal display unit 6,
2 in close proximity for displaying camera shake (camera shake) in order from the left end
There are two camera-shaped marks CA1 and CA2, followed by a 7-segment 4-digit SS, ISO, and CTR display section, and then S, P, and A for AE mode display. S
The mark is composed of an arrow pointing to the 7-segment 4-digit side to indicate the shutter speed priority, and similarly, the A mark is composed of an arrow to the right of the 7-segment 2-digit side to indicate the aperture priority. . Since the P mark is iris and both seconds are not prioritized, no arrow is attached between S and A. A
The right 7-segment 2-digit display for E mode displays the F value and the +/- value during the +/- mode. Immediately to the right is the M mark for AE mode display. This is because the metered manual display lights up at the same time.
It is displayed near the meter display for easier understanding. To the right of it, there are + and-marks, which are the symbols for override and metered manual, and then there is a numerical band consisting of 7 segments. This numerical range is AE
Display of +/- value in mode (only in P, A, S mode)
And the metered manual value display in AE mode (only in M mode). Lastly, there are AS1 and AS2 marks indicating the photometric mode, only AS1 is lit for average photometry, and both AS1 and AS2 are lit for partial photometry.

32a, b and 33a, b are displaying the override, but in the viewfinder internal display, the place where the value of the override is displayed is the override (+ /
-) Mode and AE mode are different. This is intended to be displayed in the vicinity of the center of the display section so that it can be seen more easily while the override mode is being displayed.

FIG. 3 shows the overall configuration of the control device relating to the display of the above-mentioned camera. A CPU 10 using a central control microcomputer for controlling the operation of the entire camera is supplied with a power source + E from a battery 11, a main switch SM pulled up by a resistor R, a reference oscillator XL1 for operating the CPU 10 and peripheral circuits ( A control signal group (especially for display), ▲ ▼, ▲ ▼, and serial data SDATA necessary for serial transfer of data, and a serial clock SCK are connected to the periphery.

The outline of the operation of the CPU 10 will be described later.

On the other hand, the display circuit section 20 has a power source + E from the battery 11, a main switch SM, and signals ▲ ▼, ▲ from the CPU 10.
▼, SDATA, SCK, XL of reference oscillator, reference power source 21 for driving liquid crystal are input, and as outputs, driving for common and segment electrodes of external display unit 4 and internal display unit 6 using liquid crystal display Output group. The drive output terminal groups are respectively connected to the external display section 4 of the camera and the external display section 6 in the finder which are connected in parallel.

Inside the display circuit 20, a data latch unit 22 that latches serial data, a decoder unit 23 that decodes the latched data, and a segment driver unit 2 that drives the LCDs of the external and internal display units 4 and 6 by the decoded signal.
4, a common driver section 2 for driving the common section of the LCD
5. Oscillation frequency division unit 26, L for generating the operation clock of each unit
There is a voltage generator 27 that generates a drive voltage for the CD.

FIG. 4 is a detailed diagram of the oscillation frequency division unit 26 of FIG. 3, and includes an oscillation unit of one stage of an inverter (IN1) using an external crystal oscillator XL2 and a flip-flip (FF) frequency division of this reference oscillation.
It is configured with the dividing stage configured in 1). The flip-flop FF1 is provided with a reset terminal R so as to be initialized by mounting a battery.

FIG. 5 is a detailed view of the common driver section 25, which is VLCDO, VLCD
Each voltage of LCD2, VDD is analog switch AS1-AS4
And φ ₉ and φ ₁₀ through PchFETs FP1 and FP2
It is configured to output to COM1 and COM2 at the timing. NAND gate NA1,2, NOR gate NR1,
2 and the inverters IN3 and 4 are gates for making timings.

FIG. 6 is a part of a detailed view of the segment driver section 24.
Analog switch AS for switching each voltage of VLCD2 and VDD
5 and PchFET EP3 are connected to flip-flop FF2
Of the timings of φ ₉ and φ ₁₀ processed in step 1, the driving is performed according to the state of the segment data S2n, S2n-1. NAND gate NA3 ~ N
The A7 and the inverters IN6 and 7 form a clock selector composed of S2n and S2n-1.
The flip-flop FF2 constitutes a clock generator for creating four types of clocks having a phase difference from φ ₉ and φ ₁₀ .

The entire segment driver unit is of a type in which a clock selector, an analog switch, and PchFETs corresponding to the number of SEG output terminals in FIG. 6 are prepared, and a clock generator is added.

FIG. 7 is a detailed view of the data latch unit 22. When the serial data SDATA is input from the CPU 10, there are seven 8-bit shift registers SR1 to SR7, and the parallel outputs of these shift registers are latched at the falling edge of the signal 7 respectively. 8-bit latches LT1 to LT7
Connected to.

The reset R input is applied to the j10 data of the latch LT1 and the set S input is applied to the j11 data, so that the j10 data and the j11 data are reset and set by the power-on reset POR signal. Therefore, in the initial state, j10 = "Low" and j11 = "High".

On the other hand, the serial clock SCK from the outside is the NOR gates NR3 to NR as the φs signal passing through the OR gate OR1.
It also serves as an input of 9 and also serves as a φ input of the counter decoder CD. Counter decoder CD set input S
Is "High", the output BS1 to BS1 of the counter decoder CD
All of BS7 are "High", and when the S input becomes "Low", one of BS1 to BS7 sequentially becomes "Low" every eight pulses of φ input.

When any one of BS1 to BS7 is "Low", one of the corresponding NOR gates NR3 to NR9 becomes active, and the φs signal which is the input of the NOR gate is input to any one of the serial registers SR1 to SR7. To enter. External control signal from CPU 10
The OR gate OR3 ORs the ▼ and ▲ ▼ to obtain a P · CS signal, which is input to the other input of the OR gate OR1 and the S input of the counter decoder. Further, it becomes one input of the OR gate OR2, and OR logic is taken with the other input BS7, and the flip-flop F
It is the D input of F3 and one input of the NAND gate NA8. The POR signal of the flip-flop FF3 is input to the set input S, and the output is connected to the other input of NA8. The φ input of the flip-flop FF3 has a fourth
The φ ₂ output in the figure is connected.

FIG. 8 is a detailed block diagram of the decoder unit 23 in FIG. 3, and the switch circuits SW1, SW2 and the data conversion units DC1 to DC.
4, segment decoder sections SD1 to SD6, and output control section CTL1. The outputs j12 to j of the decoder 22 are input to the switch circuit SW1.
16, j22 to j27, j32 to j37, j40 to j4
7 of the data, 4 of the outputs j50 to j53 of the decoder 22 as an input to the data converter DC3, the data converter DC
4 are outputs j10, j11, j20, j of the decoder 22.
21, j54 to j57, j60 to j67, j70 to j7
24 of 7 and 53 in total are latches LT1 to LT of FIG.
It is connected to the output of 7. In addition, the signal SM of the main switch shown in FIG. As shown in FIG. 4, φ ₁₄ is connected as an input to the output controller CTL1, and S ₁₄ is connected as an output.
Seventy pieces 1 to S70 are connected to the segment driver 24.

FIG. 9 is a detailed diagram of the switch circuit SW1 of FIG.
Jn from the data latch 22 (n = 12 to 47 (however, 1
7, 20, 21, 30, 31 are excluded)) → Pn (n = 12)
2 to 47 (excluding 17, 20, 30, 31))
FO using 5 NAND gates NA for 5 signals
It is switched by M, CTR, ISO and SS signals. When the FON, CTR, ISO and SS signals are "Low", the Pn signal becomes "High" and the jn signal is cut off.
When the FON, CTR, ISO and SS signals are "High", Pn = jn and the switch is turned on.

FIG. 10 is a diagram for explaining the symbols used in FIGS. 11, 13 to 15 and 23, in which the intersections with the output Q of the arrow correspond to the inputs A, B, C and D. By marking ○, the same function as the NAND gate is shown. I.e. Is.

FIG. 11 is a detailed view of the data conversion unit DC3 of FIG.
The logic of the outputs p1 to p9 is shown for the inputs j50 to j53. This output is the input of the switch circuit SW2 in FIG.

FIG. 12 is a detailed diagram of the switch circuit SW2 of FIG. 8, and shows the logic in which the inputs p1 to p9 are switched to q71 to q78 and q82 to q89 by the switching signals MON and +/- ON signals. The input p signal is input to the NAND gate,
When the switching signals MON and +/- ON signals are "Low", the output q signal becomes "High" and the p signal is cut off. MON, +
When the / -ON signal is "High", the output q signal becomes equal to the input p signal and the switch is turned on.

FIG. 13 shows the segment decoder sections SD1 to SD shown in FIG.
Outputs r1 to r2 for inputs q1 to q39 in the detailed diagram of FIG.
The logic of 9 is shown. This figure shows the segment decoder section S
Although the same basic configuration is shown in D1 to SD4, they are shown in the same drawing, but each of SD1 to SD4 is a necessary portion taken out from this drawing. This output is the input of the output control unit CTL1 in FIG.

FIG. 14 is a detailed diagram of the data converter DC2 of FIG. 8, showing the logic of the outputs q40 to q62 for the inputs p12 to p16. This output is the segment decoder SD of FIG.
It is an input of 5.

FIG. 15 is a detailed diagram of the segment decoder section SD5 of FIG. 8, in which inputs q40 to q62 and q71 to q78 are:
The logic of the outputs r30 to r43 is shown. This output is the 8th
It is an input of the output control unit CTL1 in the figure.

FIG. 16a is a part of the detailed view of the output control unit CTL1 in FIG. 8, and the outputs of S1 to S70 are obtained by the outputs of the segment decoder units SD1 to SD6 and the data conversion unit DC4 and the clock φ ₁₄ .

In this figure, r2n and Bm are shown in an arbitrary combination, but in reality, they are connected in the combinations shown in Table 1.

Table 1 shows a truth table by replacing the circuit diagram of FIG. 16a with a logical expression. Furthermore, the combination of r2n and Bm is specifically shown. (1 ≦ m ≦ 8), (1 ≦ 2n ≦ 6
8) r69 is shown in Fig. 16b.

FIG. 16b shows the logic for the input r69 and the outputs s69, s70.

FIG. 17 shows the relationship between the outputs q1 to q39 of the data conversion unit DC1 of the decoder unit 23 and the characters displayed on the display units 4 and 6, and the inputs q22 to q to the data conversion unit DC1.
When q1 to q39 are output according to the states of 27, p32 to p37, p40 to p47, and CTR, display characters are controlled according to the "Low" or "High" state of q1 to q39.

That is, if the output q1 is "High", SD1 is displayed. Therefore, the display of the display unit 4 (and 6) at the 10 ° position is 0, and q2 is "Hi".
"gh" indicates that the display of 10's is 2. The shutter speed SS value is p22 to p27, the ISO value is p32 to p37, and the CTR value is p40 to p40.
Data is provided by the p47 and CTR signals. Also, p
When 22 to p27, p32 to p37, and p40 to p47 are all "High", no output for the data is output. Therefore, for example, when the data of p22 to p27 corresponding to the shutter speed SS value is output, the other p32 to p37 and p40 to p47 are all set to "High" by the data conversion unit DC4 and the switch circuit SW1. . (Fig. 9 and 2
The contents that can be displayed are illustrated in FIG. 18. There are 36 types of SS values, 31 types of ISO values, and 100 types of CTR values.

FIGS. 19 and 20 are diagrams showing the relationship between the data of the data conversion unit DC2 and the switch circuit SW2 and the characters displayed on the display units 4 and 6, and the input of the data conversion unit DC2,
p12 to p16 and p1 to p9 of SW2, MON, +
/ -Q40 to q62, q71 to q7 depending on the ON state
8, q82 to q89 output data as shown in the figure. P12 to p16 for F value, p1 to p9 for override value and metered manual value
Give each data.

FIG. 21 is a part of a detailed view of the data conversion unit DC4 of FIG. 8, showing switch switching signals of the switch circuits SW1 and SW2, MON, +/- ON, FON, CTR, ISO, S.
The logic of S, the logic of ▼ and OFF signal of the CTL1 section, and the logic of OFFVLCD signal given to the voltage generating section 27 of FIG. 3 are shown. The input signals are output signals j10, j11, j55, j56, j60 of the data latch unit.
~ J67, j70, j71 and external signal, SM, ▲
▼

FIG. 22 is a part of a detailed view of the data conversion unit DC4 of FIG. 8 and shows the logic of the B1 to B8 signals of the CTL1 unit.
The input signal is the output signal j20, j55 of the data latch unit.
.About.j57, j61 to j64, j70 to j74 and an external signal ▲ ▼.

FIG. 23 is a part of the detailed view of the data conversion unit DC4 of FIG. 8 and shows the logic of the signals r51 to r69 of the control unit CTL1. The input signal is the output signal j of the data latch section.
21, j54, j57, j70 to j73, j75 to j7
7 and output signal q40 of DC2 section, and external signal ▲
▼ 21 to 23, all the data conversion units DC4 of FIG. 8 are included.

FIG. 24 is a detailed view of the voltage generator 27. By creating a reference voltage VLCD in which a diode D1 and a resistor R1 are inserted between + E and GND externally and supplying the reference voltage VLCD to a booster circuit 27a (a portion surrounded by a broken line) including capacitors C ₁ and C ₂ ,
It generates a voltage (+ E-VLCD1) that is double the voltage of (+ E-VLCD). Both VLCD and VLCD1 are analog switches and PchF
The output control circuit formed by ET leads to VLCD0 and VLCD2, respectively. VLCD0 and VLCD2 change their outputs depending on the state of OFFVLCD. When OFFVLCD is "Low", VLCD0 = VLCD, VLCD2 = VLCD1 and OFFVL
When CD is "High", VLCD0 = VLCD2 = VDD.

Further, the booster circuit unit 27a performs boosting by switching the connection of the capacitors C ₁ and C ₂ by obtaining a clock from φ _{6 in} FIG. Further, POR is a terminal for starting the booster circuit, which is started by the POR output shown in FIG.

FIG. 26 is a time chart of the data latch unit 22 of FIG. External signals ▲ ▼ and ▲ ▼ are both "Lo"
w ”, and the serial register S at the falling edge of SCK
The data of R1 to SR7 is rewritten. The contents of SR1 are all rewritten at the falling edge of the first 8th pulse of SCK, and from the 9th pulse, the shift registers SR2 to
It is rewritten every SR7 and 8 pulses. At the rise of the 49th pulse immediately after SR6 is rewritten, BS7 becomes "Low", and rewriting of SR7 starts, and at the same time,
In the flip-flop FF3, to read a D input phi ₂ rising, the output of FF3 becomes "Low", it does not change until again BS7 is "High".

A pulse is created by the output and the P.CS signal, and the contents of the SR1 to SR7 serial registers are set to L.
It will be taken into the latch of T1 to LT7.

FIG. 25 is a time chart showing a rough operation of the whole after the battery is attached to the camera. Immediately after the battery is mounted, the display circuit section 20 is initialized by the POR signal. Signal VLCD1
Goes to ground GND level, and OFFVLCD is "High".
become. Therefore, no voltage is applied to the liquid crystal.
After that, XL1 of CPU10 starts oscillation, and CPU1
0 starts operation. After a while, display circuit section 2
0 oscillation unit XL2 starts oscillating, and clocks φ _{0 to} φ
₁₄ starts to start. When the clock φ ₂ starts to operate, the data latch unit 22 starts to operate, and when serial data comes from the CPU 10, it operates as shown in FIG. When the clock φ ₆ starts to operate, the voltage generator 27 in FIG. 24 operates and the potential of the signal VLCD1 becomes stable after a short time.
After that, if OFFVLCD is set to "Low" as required, the liquid crystal drive voltages VLCD0 and VLCD2 are supplied to the display units 4 and 6.

28 to 35 and FIGS. 37 to 39 show various display modes of the external display unit 4 and the content display unit 6, except for FIG. FIG. b shows the display on the internal display unit 6.

28a and 28b are AE displays in the program mode,
Auto speed 1/250, auto aperture values 5, 6 and program PROGRAM, and Indicates.

The mark AS1 at the right end of FIG. 28b is a display in the photometric mode and indicates average photometry.

29A and 29B are AE displays in the aperture priority mode,
Aperture setting mark And setting aperture value 5.6 and auto second 1/250,
A with aperture priority And AE modes.

30a and 30b are AE displays in the shutter speed priority mode. Shutter speed setting mark And set shutter speed 1/250 and automatic aperture value 5.
6 and S with shutter speed priority And AE modes.

31A and 31B are AE displays in the manual mode.
Setting mark for shutter speed and aperture value And set shutter speed value 8 "and set aperture value 1.4, and M in manual mode And AE modes. There is a partial metering mark in the metering mode at the right end of the internal display, the left side is the value of the error amount of the manual setting value with respect to the proper value, the so-called metered manual instruction value, and there is an indication difference of +6.5 EV. Indicates. The mark at the left end is a mark indicating a camera shake (camera shake) report, and the two marks are alternately lighted.

32A and 32B show the display during the setting of the override. It represents the direction + of the override and the absolute amount of 1.5 EV.

33A and 33B show the AE mode display after the override setting. Compared to FIG. 28, the direction + of overriding is added. Further, in the internal display, the value of 1.5 EV which is the absolute amount of override is also displayed. However, in the internal display, +1.5 is blinking.

34a and 34b show the display during ISO setting. An ISO mark and an ISO value of 100 are displayed. However, the ISO mark does not light in the internal display.

37a and 37b show the display of a hand shake (camera shake) warning. In the internal display unit 6, the mark CA of the leftmost camera
1 and CA2 are alternately turned on to show the movement.

FIG. 37 c shows the display on the external display unit 4.

FIG. 35 shows the display in the standby mode. Only the bar display appears and everything else is off. Functions other than the display of the camera are stopped.

<Description of Operation> -Overall Operation-The basic operation of the display circuit section 20 will be described. When the DC voltage + E is supplied from the power source 11, a momentary P generated by the power-on reset circuit 40 (the right end in FIG. 4).
Depending on the OR signal, the frequency-division stage flip-flop FF1 (FIG. 4), the clock generator flip-flop FF2 (FIG. 6) of the segment driver unit 24, the data latch circuit 23 flip-flop FF3, and the latch LT1
(FIG. 7), the start-up FET 27b (FIG. 24) of the voltage generator 27 is set to the initial state. In the latch LT1, the data terminals are j10 = "Low" and j11 =
Set to “High”. The flip-flops FF1 and FF2 set the output state to Q = “Low” = “High”. F
In F3, the output state is set to Q = "High", = "Low". In the voltage generator 27, when the FET 27b is momentarily turned on, the capacitor C ₂ is charged and VLC
The level of D1 becomes GND level. In this state, the crystal oscillator XL2 of the oscillating unit 41 (FIG. 4) has not started oscillating, so there is no circuit-like operation, and the oscillation start-up of XL2 ( =
Waiting for oscillation of φ ₀ ). On the other hand, VDD, VLD2, and VLD0 are given in an indefinite state through the COM and SEG terminals to the LCD display side of the external display units 4 and 6, but (COM1 is VLCD2, COM2 is VLCD0, SEGn.
Is VDD or VLCD depending on the state of S2n and S2n-1.
2) OFFVLCD input to the voltage generator 27 is j10 =
Since "High" is set through the AND gate A50, the inverter I50, and the OR gate O50 by initial setting of "Low" and j11 = "High", VLCD2 = VLCD0 = VDD is set inside and outside by the switch circuit of FIG. Display 4, 6
Since the voltage applied to each terminal of the LCD display is the same, there is no DC voltage application state harmful to the liquid crystal.

Next, the crystal oscillator XL2 starts to oscillate, and when a clock enters the flip-flop FF1 of the frequency dividing stage from φ ₀ , all the parts start operating together.

The clock φ ₂ enters the flip-flop FF3 of the data latch unit 22, and when serial data communication from the CPU 10 starts, it operates to generate an LTCH pulse.

The clock φ ₆ enters the booster circuit of the voltage generator 27,
A boosting operation is performed by switching the capacitors C ₁ and C ₂ .

The clocks φ ₉ and φ ₁₀ enter the common driver section 25 and the segment driver section 24 and serve as clocks of liquid crystal drive waveforms.

The clock φ ₁₄ is input to the output control unit CTL1 of the decoder unit 23 and used to control the blinking state of the display contents.

The operation of the crystal oscillator XL2 after the oscillation starts is as follows. First, the voltage generator 27 will be explained. The clock φ _{6 that} has entered the booster circuit 27a in FIG. 24 starts boosting operation and the initial VLCD1 terminal is at the GND level. To the level of (VDD-2VLCD) to stabilize. After that, depending on whether the power supply voltage is lowered to stop the operation or the oscillation circuit is stopped, the operation continues continuously until the lifting operation is stopped.
On the other hand, the data latch circuit 22 started by the clock φ ₂ causes the terminals j10 and j11 to have “Low” and “High”.
OFFV at the moment when a signal other than is input and latched
The LCD becomes "Low" and the analog switch at the right end of FIG. 24 is switched to wait for the output of VLCD2 = VLCD1 and VLCD0 = VLCD. These are respectively guided to the common driver 25 and the segment driver 24 and applied to the LCD displays of the internal and external display sections 4 and 6 as liquid crystal driving voltages, and liquid crystal display is performed based on the latched data.

Next, referring to FIG. 26, the data latch unit 22 will be described. When both the ▲ ▼ and ▲ ▼ signals become "Low", this circuit starts its operation. ▲ ▼ is, for example, a timing signal for supplying power to a photometric circuit of a camera (not shown), and the photometric circuit starts to operate when ▲ ▼ = "Low". Further, ▲ ▼ is a signal for determining the other party of serial data communication, and one signal is output from the CPU 10 to other circuits in the camera (not shown). ▲ ▼ ＝ “Low” selects the partner of serial data communication.

When either ▲ ▼ or ▲ ▼ is "High", P
The CS signal is "High", the counter decoder CD is set, and the outputs BS1 to BS7 are all "High". The output φ _{s of the} OR gate OR1 is "High".
The output ▲ ▼ of the NAND gate NA8 is also "Hi
gh ”. Both ▲ ▼ and ▲ ▼ are“ Low ”
At the same time, the counter decoder CD is activated and the OR gates OR1 and OR2 are opened, and the signals of SCK and BS7 can be detected. At the rising edge of the first pulse of SCK, BS1 goes "Low" and NOR gate NR3 opens. Since the φ input of the shift register SR1 rises at the falling edge of the first pulse, the shift register SR1 fetches only one content of SDATA at that time. The data at this time is j10. Next, the second pulse comes and the same operation is repeated. At the falling edge of the eighth pulse, eight pieces of data have been taken into the shift register SR1.
The th data is called j17. Until this time, the signal BS1 is "Low". When the next 9th pulse rises, BS1 becomes "H
It becomes "igh", BS2 becomes "Low", NOR gate NR3 closes, and NOR gate NR4 opens. Since the φ input of shift register SR2 rises at the falling edge of the ninth pulse, S at that time occurs.
The shift register SR2 fetches only one content of DATA. The data at this time is j20. After that, in the same way, BS6 becomes "High" at the rising edge of the 49th pulse,
BS7 becomes "Low", NOR gate NR8 closes, and NOR gate NR9 opens. Further, the output of the OR gate OR2 becomes "Low". The contents of the shift register SR7 are loaded with the data of j70 to j77 by the 56th pulse after that, but by the 56th pulse after the first pulse,
▼ The output remains "High" and each shift register SR
Data is not fetched from the latch to the latch LT. That is, the output of the OR gate OR2 becomes “Low” by the OR gate OR2 opened at the 49th pulse, but the clock φ ₂
The flip-flop FF3 takes in the "Low" level of the D input at the rising edge of and the output becomes "High" level. However, the other input of the NAND gate NA8 becomes "Low" sooner than the output changes.
The output remains "High".

Here, the output of the OR gate OR2 becomes "High" depending on whether the 57th pulse comes, or whether one of ▲ ▼ and ▲ ▼ becomes "High". Since the output of the flip-flop FF3, which is the other input of the NAND gate NA8, is also "High" at this moment, the output of the NAND gate NA8
▼ becomes “Low”. This falling of “High” → “Low” serves as a signal of the latch and shift registers SR1 to S
The data stored at 1 o'clock in R7 is latched in the data memory of the latches LT1 to LT7. Flip-flop FF3 by subsequent clock phi ₂ of the rising of the D input "Hi
gh ”is taken in, the output becomes“ Low ”, and the counter decoder CD is set at either“ High ”of ▲ ▼ or ▲ ▼, and each returns to the initial state.

The above is the outline of the data latch operation. If the number of serial data communication clock bytes is insufficient, no data error will occur because the last latch pulse ▲ ▼ will not be output. Even if the clock byte count is exceeded, it will be automatically cut at the 57th pulse. Naturally, no abnormality occurs. Also, the clock within the same pulse sends out the CPU
Since the processing is performed so that there is no interruption on the side, abnormalities due to data communication are safely prevented.

On the other hand, external signals ▲ ▼, ▲ ▼, SCK, SDA
Even if the TA operates normally, if the internal φ ₂ is not operating, the ▲ ▼ pulse will not be output, and the data captured in the shift registers SR1 to SR7 will be latched LT1 to LT1.
It cannot be latched to LT7. This means that when it is considered that the liquid crystal drive waveform does not operate when φ ₂ is not operating, a DC voltage is applied to the liquid crystal. Therefore, at that time, j10 = "Low", j11 = "High"
It is necessary to maintain OFFVLCD = “High” without applying voltage to the liquid crystal. Therefore, the external data is not taken in when the clock φ ₂ is not operating.

Next, the common driver section 25 and the segment driver section 2
4 will be described.

In FIGS. 5, 6, and 27, the NAND gate N
A1, NA2, NOR gates NR1 and NR2, inverters IN3 and IN4, and a gate circuit composed of analog switches AS1 to AS4 and Pch FETs FP1 and FP2
Control each switch. The input signals of the gate circuit are φ ₉ and φ ₁₀ , and at this timing, COM
2, the output of COM1 changes as shown in FIG. The signals COM2 and COM1 have the same period as the clock φ ₁₀ and have a deviation of 1/4 period from each other.
The output value has three levels of VDD, VLCD0 and VLCD2.

In FIG. 6, four kinds of clocks generated by the clocks φ ₉ and φ ₁₀ processed by the clock generator constituted by the inverter IN5 and the flip-flop FF2 are selected by the clock selector constituted by the NAND gates NA3 to NA7. The conditions to select are S2n,
Two signals of s2n-1, and by this condition, SE
The output waveform of Gn is determined.

This situation is shown in FIG. 27, which differs depending on the four types of states determined by S2n and S2n-1.
The cycle is the same as that of the clock φ _10, and there is a deviation of 1/4 cycle from each other. Output values are VDD and VLC
Has a binary level of D2. The LCD display is turned on by the waveform of the portion where the potential difference between the signals COM1, 2 and the segment signal SEGn becomes 2 × VLCD2. The segment of the LCD display to which the voltage of SEGn (LH) and SEGn (HN) is applied to COM1 lights up, and COM2
On the other hand, the segment of the LCD display to which the voltages of SEGn (HL) and SEGn (HH) are applied is turned on.
SEGn (LL) does not light the segment even for COM1 and COM2.

That is, the S2n-1 signal is a signal for controlling the lighting of the segment with respect to COM1, and is OFF when S2n-1 = "Low" and ON when S2n-1 = "High".
The S2n signal is a signal for controlling the lighting of the segment with respect to COM2. When S2n = "Low", it is OFF, S2n =
When "High", it is turned on.

The data j10 to j17 and j20 to j latched in FIG.
27, j30 to j37, j40 to j47, j50 to j5
7, j60 to j67 ,. 70 to j77 are j17 and j3
All the bits except 0 and j31 are input to the decoder section shown in FIG. SW1, SW2, DC1 to DC4, S
D1 to SD6 are merely gate circuits and have no timing relationship.

The explanation will be given below.

First, the contents of serial data will be described.

j10 and j11 are signals for controlling the supply of the liquid crystal drive voltage, and the liquid crystal drive voltage is stopped and the voltage applied to the liquid crystal becomes 0 only when j10 = "Low" and j11 = "High".

j12 to j16 are data signals (see FIGS. 9, 14, 15, and 20) related to the aperture value of the camera, and there are 23 types. Also, j12 to j16 are all "High"
When is, nothing is displayed.

j20 is a signal (see FIG. 22) relating to an unexpected warning of the battery voltage in the camera, and all the displays displayed when j20 = "High" repeats blinking in a cycle determined by φ ₁₄ .

j21 is a camera shake (camera shake) warning signal (see FIG. 23), which becomes “High” when the shutter speed value becomes slower than the vicinity of the limit of causing camera shake (camera shake). At this time, the shake marks CA1 and CA2 on the internal display section 6 in the finder are alternately turned on.

j22 to j27 are data signals (see FIGS. 9, 13, 17, and 18) relating to shutter speed values, and there are 36 types. Also, j22 to j27 are all "High"
When is, nothing is displayed.

j32 to j37 are data signals relating to the ISO value of film sensitivity (see FIGS. 9, 13, 17 and 18)
There are 31 types. When j32 to j37 are all "High", nothing is displayed.

j40 to j47 are data signals (see FIGS. 9, 13, 17, and 18) relating to the timer time value, and there are 100 types from 0 to 99.

When j40 to j47 are all "High", nothing is displayed.

j50 to j53 are data signals (see FIG. 11, FIG. 12, FIG. 19, and FIG. 20) relating to the override value and the deviation amount of the metered manual, and 9 types of the override value and the meter depending on the displayed contents. The 14 manual deviation values are switched and sent from the CPU. When j50 to j53 are all "High", nothing is displayed. For switching display contents, see j55,
The j56 signal (described later) takes charge.

j54 to j56 are override values, the sign of the deviation amount of the metered manual, and a SIGN signal (see FIGS. 21, 22, and 23) relating to signal switching, and j54 is “+” or “+”. A signal associated with the sign "-", j
55 and j56 are signals for switching data switching between the override value and the deviation amount of the metered manual for each external display and internal display.

j57 is a signal (see FIG. 22 and FIG. 23) used for display during so-called preview to confirm the depth of field by narrowing down the lens aperture before shooting. The signal becomes "High", and the aperture mark F on the external display unit 4 blinks and the bar of the set numerical band instruction marks TA1 and TA2 is controlled to light.

j60 is an ISO display priority signal ISOPRI. This is because the main switch SM is off and OFFVLCD
Even if the signal is "High" and the liquid crystal drive voltage is stopped, when this signal becomes "High", the OFFVLCD signal is set to "Low" so that the liquid crystal drive voltage is supplied to the segment driver 24 and the common driver 25. . (Refer to FIG. 21) This signal is not used by itself, but at the same time as this signal, ISO
The display mode and ISO value data are sent from the CPU 10. In terms of camera operation, this is the state immediately after the battery is installed.

j61 is a blinking signal of the deviation amount of the metered manual M'dMOVER (see FIG. 22), and this signal is "High".
The deviation value of the metered manual flashes with.

j62 is a shift signal SHIF for blinking the program mode mark during the shift of the program mode of the camera.
T (see FIG. 22), j62 is "High", and this mark blinks. Here, the shift means a state in which the combination of the aperture value and the shutter speed value in the program mode is changed to operate. It should be noted that, if necessary, all the AE modes can be blinked regardless of the program mode.

j63 is an out-of-control warning signal Not.CONT (refer to FIG. 22), which becomes “High” when the exposure value that exceeds the aperture value and second value that can be controlled by the camera is required. Depending on the AE mode, the value and / or second value flashes the numerical value on the calculation control value side to warn.

j64 is a brightness-outside warning signal BV (see FIG. 22). When the brightness value exceeds the brightness value that can be measured by the camera, this signal becomes “High”, and AS1 and AS2 are displayed in the metering mode display. Flashes to alert you.

j65 is a bulb signal BULB (see FIG. 21), which is a signal for switching the display content of the 4-digit 7-segment during bulb exposure from the shutter time (buLb) to the bulb exposure time count display by the camera. ", The valve count is displayed and the contents of j40 to j47 are displayed.

j66 is an all-off signal ▲ ▼ (see FIG. 21)
Is a signal for controlling all the waveforms of the driving SEG terminals to be OFF waveforms (see SEGn (LL) in FIG. 27), and all are OFF display at "Low". However, the camera marks CA1 and CA2 cannot be controlled.

j67 is the all-lighting signal ALLON (see FIG. 21), and all the waveforms of the driving SEG terminals are ON waveforms (second waveform).
7) See SEGn (HH)). It is a signal to control to "ON" and all are ON display.

However, the camera marks CA1 and CA2 cannot be controlled.

j70 and j71 are camera operation mode signals CALL M
ODE (see FIGS. 19, 20, 21),
Normal AE mode, STANDBY mode in which the camera is not operating even if the main switch SM is ON, ISO mode for ISO setting / display, +/- for setting / display +/-
There are four modes, and the display contents are switched according to each mode. (See FIGS. 28 to 35) j72 and j73 are AE mode signals AEMODE of the camera.
(See FIGS. 22 and 23), there are four states of the program mode, the aperture priority mode, the shutter speed priority mode, and the manual setting mode, and the display contents are switched according to each signal.

j74 is the ISO output when prompting the setting of the ISO value
This is a warning signal ISO ARM (see FIG. 22), and when this signal becomes "High", the ISO mark and the ISO value in the inner and outer display sections 4 and 6 blink.

j75 is a mode extinguishing signal MODE OFF (see FIG. 23). When this signal becomes “High”, the AE mode display being displayed is extinguished. Set the mode display to OFF when the film is being skipped when loading the film into the camera.

j76 and j77 are photometry mode switching signals AVE / SPOT
(See FIG. 23), and when the partial metering mode of the two metering modes of the average metering mode and the partial metering mode is set (either j76 or j77 or one becomes "Low"), the viewfinder internal display section The AS2 of 6 is turned on. A
S1 is always lit during the AE mode.

The DC 4 also uses the external signals SM and ▲ ▼ as data, and the data code conversion unit (FIG. 23) and the LCD indicators of the display units 4 and 6 relating to the display other than the numerical band such as the shutter speed value and the aperture value. A decoding unit (FIG. 22) relating to blinking control of each display segment, and a signal switching unit SW1 at two places
It is divided into three decoding units (FIG. 21) related to SW2.

In FIG. 21, the switching signals of SW1 and SW2 are mainly created, and the FOM, CTR, ISO, and SS signals are SW1.
The MON and +/- ON signals control SW2. In addition, ▲ ▼ and OFF signals are commands for controlling CTL1 and displaying ON and OFF for all segments. Furthermore, this signal is "H" for the OFFVLCD signal.
At the time of "igh", it works by turning off the liquid crystal drive power supply and the liquid crystal drive circuit. The purpose is to prevent the DC voltage applied to the liquid crystal when the original oscillation of XL2 is stopped and to turn off the main switch SM of the camera. Reduction of power consumption, while CA
The j70 and j71 of the LL MODE signal represent four camera operation modes, and when j70 · j71 = “High”, it is called the normal shooting AE mode. j70 / j71 =
When it is "High", it is called ISO mode for setting ISO sensitivity. When j70 · j71 = “High”, it is called the STANDBY mode in the camera standby state. j70 ・ j71 = "Hig
When h ”, it is called +/- mode for setting the override amount.

The signals for SW1 and SW2 will be described according to the above four modes (see FIG. 21).
▼ becomes “Low” (camera starts operation)
Then, the FON signal becomes "High", SW1 operates, and the aperture value information j12 to j16 is selected and decoded and displayed. When ▲ ▼ becomes "High" (the camera is in a standby [standby] state), the FON signal becomes "Low" and the aperture value information is erased by SW1.

On the other hand, when ▲ ▼ is "Low" and j65 is "Low" (normal time), the SS signal becomes "High" and the shutter time information j22 to j27 is selected and displayed in decode. At this time, other CTR signals and ISO signals are "Low", and timer count information and ISO value information are erased by SW1.

When ▲ ▼ is “Low” and j65 is “High” (at the time of valve counting), the CTR signal becomes “High”, and the timer count information j40 to j47 is selected and decoded and displayed. At this time, the other SS and ISO signals are "Lo".
w ”, and shutter speed information and ISO value information are SW
Turned off by 1.

Also, +/- ON signal is "Low", but MON signal is ▲
▼ is “Low” and j50 or j56 data is “High”
If so, the value information of the deviation amount of the metered manual is selected and decoded and displayed by SW2, but all the override value information is erased.

During ISO mode, SS, CTR, FON, MON, +
/ -ON signals are all "Low", only ISO signals are "H"
igh ”, SW1 operates, and ISO value information j32-
The selected j37 is decoded and displayed. At this time, other numerical bands are erased.

During STANDBY mode, SS, CTR, FON, I
SO, MON, +/- ON signals are all "Low",
All numerical bands are erased.

During +/- mode, SS, ISO, CTR, FON, M
The ON signals all become "Low", and the +/- ON signals become "High" when ▲ ▼ is "Low". At this time, the override information j50 to j53 is selected and decoded and displayed.

FIG. 22 shows a control signal for blinking display of each display segment. When the output B1 to B8 becomes "High", if the corresponding segment (see Table 1) is lit, that segment is Flashes.

The B8 signal is a signal for blinking the F mark on the external display unit 4, and is mainly controlled by the j57 data.

The B7 signal is the 7th segment of the 7th segment of the LCD of the internal display section 6.
No. 8 and No. 8 and a signal for blinking the second digit of col.2 between them, which is mainly controlled by the data of j55, j56, j61.

The B6 signal is a signal for blinking AS1 and AS2 of the internal display unit 6, and is mainly controlled by j64 data.

The B5 signal is a signal for blinking No. 5 and No. 6 and col.1 of 7 segments in both the external and internal display sections 4 and 6, and mainly j6.
Controlled by 3 data.

The B4 signal is a signal for blinking Nos. 1 to 4 of 7 segments in both the external and internal display units 4 and 6, and is controlled mainly by the data of j63 and j74.

The B3 signal is a signal for blinking the AE mode display section in both the external / internal display sections 4 and 6, and is mainly controlled by j62 data.

The B2 signal is a signal for blinking the ISO mark of the external display unit 4, and is mainly controlled by the data of j74.

The B1 signal is a signal for blinking all the segments except CA1 and CA2 among the segments other than those generated in B8 to B2, and there is no particular data signal. However, blinking control is performed by j20 data from B2 to B8 including B1.

FIG. 23 shows a decoder for the segments 1 to 8 and col.1 and col.2 of the seven segments for displaying the numbers in the inner and outer display parts 4 and 6. Serial data j54 to j57, j
70 to j73, j75 to j77, j21, an external signal ▲ ▼, and a decoded DC2 output signal q40.
The output is controlled by each signal of, and the output is r51 to r6.
There are up to 9, and when each output becomes "High", each segment corresponding thereto lights up.

FIG. 9 shows SW1 for selecting signals.

The input signal is the aperture value of j12 to j16, j22 to
shutter speed value of j27, ISO value of j32 to j37,
The timer count values are j40 to j47, and there are a FON signal, a CTR signal, an ISO signal, and an SS signal for selecting each. When each of the selection signals is "High", the NAND gate opens and the output data p = input data j. On the other hand, “Lo
When w ”, the NAND gate is closed and output data p =“ Hig
h ”.

(Example) When FON = "High", outputs p12 to p16 are input j1.
Pass 2-j16 as it is.

When FON = "Low", all outputs p12 to p16 are "Hig"
h ”.

Next, DC1 will be described, although there is no detailed drawing.

DC1 is serial data j2 processed by SW1
2 to j27, j32 to J37, j40 to j47 corresponding to p22 to p27, p32 to p37, p40 to p47, and q1 to q3 corresponding to a 7-segment 4-digit part
9 is a data converter (decoder) that outputs 9 data. FIGS. 17 and 18 are for explaining the concept of DC1, but the input data is 36 kinds of shutter speed values (SS values) corresponding to p22 to p27 (buLb to 1/400).
0) and ALLHigh, 31 ISO values corresponding to p32 to p37 (ISO6 to ISO6400) and ALLHigh, p
Timer count value (CTR value) corresponding to 49 to p47
There are 100 types (0 "to 99") and ALL High.

For example, data p27 to p2 corresponding to the SS value "buLb"
When 2 = “LLLLLL” is input (the other data p32 to p37 and p40 to p47 at that time are processed by DC4 and SW1 so as to be ALL High), the output data is q7 data for the segment decoder SD1. b ”
The q18 data is “L” for SD2, the q29 data is “u” for SD3, and the q39 data is “b” for SD4.

In addition, data p37 to p corresponding to the ISO value "200"
When 32 = “LHHHLL” is input, the other data p22 to p27 and p40 to p47 at that time are processed by DC4 and SW1 so as to be ALL High. ) Output data is q1 data, S for the segment decoder SD1.
It outputs q8 data for D2, q21 data for SD3, and does not output data for SD4.

Also, p22 to p27, p32 to p37, p40 to p47
Are all "High", the segment decoder SD1 ~
There is no output for SD4. All the segments corresponding to SD1 to SD4 are turned off.

The gate circuit is configured as described above.

Next, the segment decoders SD1 to SD4 shown in FIG.
Will be described. The data signals q1 to q39 obtained in the previous section are SD1 for q1 to q7 and SD for q8 to q18.
2, q19 to q29 are SD3, q30 to q39 are S
Enter in D4. Although the internals of SD1 to SD4 are basically the same, the terminals to which the corresponding data signal is not input among the 14 inputs are pulled up to the + power supply side in each block. The input of this circuit is configured so that a valid output can be obtained when it goes "Low". For example SD1
To q7 data signal (b of buLb), Input becomes “Low”. At this time, input q1 of other SD1
Outputs (c), (d), which are related to the line which went to "Low" though the input which is ~ q6 and pull-alp is "High",
(e), (f), (g) are all "High" and other (a), (b), (h)
The line is "Low". This output (c), (d), (e),
Although (f) and (g) correspond to r3 to r7 in terms of SD1 terminals, these are input to the CTL1 in the next stage and connected to the liquid crystal display. This r output has a one-to-one correspondence with the liquid crystal segment (see FIG. 16a, FIG. 2b, c, and Table 2). The outputs (c), (d), (e), (f), and (g) here correspond to the segment names of the numbers of 7 segments each (see Fig. 2b), and the character "6" is used. Represent.

Further, for example, q21 data signal (“2”) for SD3
Appears, The input becomes “Low” and (a), (b), (d), (e), and (g) become “Hig.
It becomes "h". Then, the character "2" is displayed.

P12 to p16 obtained by SW1 enter the decoder DC2 shown in FIG. The output when p16 to p12 = "LLLLLL" is q40, and the output of "Low" is output. q4
The output of 0 goes to the segment decoder SD5 while going to the decoder DC4. The other outputs are exclusively connected to SD5.

The contents of the outputs of q40 to q62 based on the data of p12 to p16 include 23 kinds of aperture values shown in the concept of SD5 shown in FIGS. These are segment-decodered at a part of SD5 (input section of q40 to q62) shown in FIG. 15, and outputs of r30 to r43 are obtained.

The decoder D of FIG. 11 is applied to the data j50 to j53.
There is C3. j50 data is data with a decimal number or less,
A p1 output and a p2 output are obtained. The data of j51 to j53 represent the information of 0 to 6, the output is p3 to p9, and the output is in the active state at "High". This output is the first
Input to the switch SW2 in FIG. 2 and the selection information MON, +
Output destination is switched by / -ON. MON is “High”
At this time, +/- ON is "Low", and the outputs of p2 to p9 are inverted and output to q82 to q89.
All of q78 become "High". On the other hand, when +/- ON is "High", MON is "Low" and the outputs of p1 to p7 are inverted and output to q71 to q77.
2 to q89 are all set to "High". Also, q78 is "Lo
w ”. When both MON and +/- ON are“ Low ”, the outputs of q71 to q78 and q82 to q89 are all“ High ”.
become.

The output of SW2 is q71-q78 to SD5, q82-q
89 is output to SD6.

The contents of q71 to q78 and q82 to q89 output by SW2 are as shown in FIGS. 19 and 20, q71 to q78 are seven numerical values for the override value and one decimal point, q82 to
q89 is 7 integer numeric values for metered manual values (including override values) and a decimal display 1
Corresponds to each species.

Although the contents of SD6 are not shown, the basic idea is the same as SD1 to SD4 in FIG. 13, and the gate configuration is such that the data shown in FIGS. 19 and 20 and the output display examples are related. ing.

Finally, r created by SD1-SD6 and DC4
1 to r69 and B1 to B8, ▲ ▼, OFF signals, and the clock of φ ₁₄ are input, the output control unit CTL1 will be described.

The internal structure of CTL1 is shown in FIG. 16b.

Except for the structure of r69 → S69 and S70, the structure is basically as shown in FIG. 16a. First, in FIG. 16b,
When the "High" signal is input to r69, the gates for S69 and S70 open and the clock of φ ₁₄ causes "Hig
While h "and" Low "are repeated, S69 and S70 output in opposite phases, and the corresponding CA1 and CA2 marks are alternately lit to give an image in which the camera mark is blurred. Table 1 shows a logical expression and a truth table showing the relationship between the output S and the input r of the circuit for signals other than r69.

As shown in this table, when the signal ▲ ▼ becomes "Low", all the outputs S except "S69" and "S70" are "High", and the display contents are all lit except CA1 and CA2.

Next, when the OFF signal becomes "High" when the signal ▲ ▼ is "High", all the outputs S become "Low" except S69 and S70, and all the displays excluding CA1 and CA2 are turned off. .

▲ ▼ When the Bm (B1 to B8) becomes “Low” when the signal is “High” and the OFF signal is “Low”, the output S =
It becomes r, and the display contents are lit up and displayed according to the display information given by the serial data.

▲ ▼ signal is “High”, OFF signal is “Low”, Bm
When any part of (B1 to B8) becomes “High” by DC4, B and r under the truth table of Table 1
, The output S corresponding to r in the same group blinks in accordance with the clock of φ ₁₄ according to the display contents at that time.

For example, when the B6 signal is “High”, the other B1 to B5
When the B7 and B8 signals are "Low", the corresponding outputs S59 and S60 of r59 and r60 in the B6 signal group repeat "High" and "Low". However, when the state of r59 and r60 is "Low", S59 and S60 are "Hig".
It cannot be h ”. Therefore, S59 and S6
If AS2 and AS1 corresponding to 0 are lit, it changes to blinking.

The outputs S1 to S70 obtained by the above CTL1 are respectively input to the segment driver (FIG. 6) and are output as liquid crystal drive waveforms (see FIG. 27) to the SEG terminals (SEG1 to SEG35), which are the final outputs. .

Table 2 shows the relationship between the CTL1 output S and the SEG terminal.
The names of the segments shown in this table are the same as the names of all segment diagrams shown in FIGS. 2b and 2c.

-At the time of starting the camera-When the camera is started by turning on the main switch SM, the CPU 10 is interrupted, the CPU 10 is released from the stopped state, and the operation starts according to the program in the internal ROM. At the same time, a voltage is supplied to a photometric circuit (not shown) or the like, but it takes several tens of milliseconds until the photometric circuit or the like operates reliably and gives necessary data to the CPU 10. . However, a CPU that operates at high speed
In this case, serial data communication with the display circuit section is performed once or more at 10. The content of serial data communication (see Fig. 36) is mainly shutter speed and aperture value which are exposure information, but when the photometric circuit etc. are not operating normally, the accurate value of these exposure information Can't get Therefore, it is not good to carry out serial data communication in this state, as it not only makes sense but also causes an erroneous display. Therefore, at the time of start-up, until the CPU 10 takes in accurate information and finishes the arithmetic operation, sending off data or data for standby display prevents the display unit from displaying annoying inaccurate values. I can do things. The display unit of the embodiment has a structure for holding the previous display unless new serial data communication is performed. There is no particular problem if serial data communication is not performed until the calculation is completed using this, but since the program of the CPU 10 is designed to create a program flow that does not issue special cases as much as possible, serial data is generated at a fixed cycle. The communication method is better in that it does not increase the capacity of the ROM for the program. Therefore, the above method is better.

-At the time of mounting the battery- Immediately after mounting the battery on the camera, a voltage of + E is applied to the CPU 10 and the display circuit unit 20 to start the operation of each. The crystal oscillators XL1 and XL2 are separately provided to the respective circuits.
And starts to operate independently, but in this case XL1
Is higher in frequency than XL2, so generally XL
1 starts oscillation earlier. After the oscillation is started, the CPU 10 starts the operation according to the program of the internal ROM, but since there is little work to be done immediately after the battery is installed, the CPU 10 becomes in the stopped state in several tens of msec to stop the function and wait for it to be woken up again. . Generally, at this point, the oscillation rising of XL2 of the display circuit unit 20 (generally about 100 msec to 1 sec) is not guaranteed. When XL2 of the display unit is not oscillated, serial data communication with the CPU 10 is not accepted, and the clock φ _{2 in} FIG. 7 does not occur.
Do not operate like the time chart shown in the figure ▲
▼ No pulse is generated. Even if XL2 is oscillating, the data in the display circuit section 20 is not rewritten unless serial data is communicated. (▲ ▼, ▲ in Fig. 7
Since ▼, SDATA and SCK do not come, BS7 does not occur and ▲ ▼ pulse does not occur. ), The above-described operation of the CPU 10 is not good because the display content continues to remain undefined display of the battery mounting state. Therefore, j10 reset, j11 set, FIG. 24, FIG.
As shown in Fig. 5, one measure is to turn off the LCD driving power supply by the power-on reset circuit so that the initial undefined display is not performed. Further, if the power-on reset circuit does not work in some state or if it is not good that the off display continues, the serial data communication from the CPU 10 should be continuously performed until the XL2 oscillation start-up guaranteed time after the battery is mounted. Then, as soon as the oscillation of XL2 rises, the normal operation is performed and the displayed contents are switched immediately. The contents of the serial data at this time may be data for turning off, data for standby display, or any other data. Therefore, as the operation of the CPU, serial data communication is performed using the display data until after the necessary processing is performed immediately after the battery is installed and until the XL2 oscillation start-up guaranteed time, and after a predetermined time has elapsed, if the serial data communication is not necessary. It may be stopped and the function may be stopped. However, within the XL2 oscillation rising guaranteed time, C
The PU 10 must prohibit the interrupt operation.

-Before CPU 10 Stops- Immediately before CPU 10 stops operating, CPU 10 sends display data in the standby mode to the display. After that, until the CPU 10 is activated again, since there is no data transfer, the display does not change and the standby mode display continues. Immediately before the main switch SM is turned off and the CPU 10 stops operating, display data in the light-off mode is sent from the CPU 10 to the display in the same manner as above. After that, there is no data transfer until the main switch SM is turned on again, so the display does not change and the off state continues.

-ALLON and ALLOFF- The serial data j10 and j11 are the highest priority data that cut off the LCD power supply from the root.

▲ ▼ ・ Turns off when j11 = "High".

On the other hand, the data of j66 and j67 are prepared for the connection check and are the data of the second priority. j67 =
Waveform that all segments light up when “High”, j6
When 6 = “Low”, waveforms that turn off all segments are output from the COM and SEG terminals, respectively. When each waveform is applied to the normally connected LCD, it is displayed whether all the lights are turned on or all lights are turned off. However, if the connection with the LCD is misaligned, a part of the LCD may be turned off, turned on, or have a different brightness from other segments, and it may be apparent that the connection is abnormal. .

Also, as a method of giving a signal of serial data communication, SDA
By connecting the TA line to + E through a small resistance, that is, when pulling up, all the serial data becomes "High" information, the priority bit j67 comes alive, and the all-lighting mode is set. On the other hand, if it is pulled down by connecting to GND, all serial data will be "Lo".
It becomes w "information, and the priority bit j66 comes alive to enter the all-off mode. This is a check that can be performed even after the camera is assembled, and is a very easy check method.

Furthermore, there is no need to provide a dedicated terminal, which is ideal.

-Extinguishing Mode and Standby Mode- Fig. 35 shows the display of the external display unit 4 in the standby mode. Only the bar is lit up and all other external displays,
Turn off the internal display and. As the camera body, CPU1
0 is a stopped state and is waiting for an input corresponding to an interrupt instruction. Also, although power is supplied to the display circuit 20,
No power is supplied to other circuits (not shown) other than the CPU 10. However, when an interrupt input such as a photometric switch is input to the CPU 10, power is supplied, other circuits also work, and the function as a camera is started.

On the other hand, the display in the off mode erases all the displays. As a method, turn OFFVLCD to "High" to turn off the liquid crystal drive power.
To The operation of the camera body at this time is performed by the CPU 10 SM
Power is not supplied to all other circuits (not shown) except the display circuit only in the stopped state waiting for an input interrupt from the terminal.

The difference between the standby mode and the off mode camera is that only the main switch SM is alive in the off mode. On the other hand, in the standby mode, other operation start switches such as a photometric switch (not shown) come alive. Further, the current consumption is smaller in the light-off mode and energy saving is performed, and the voltage applied to the liquid crystal is zero in the light-off mode, so that the liquid crystal has good storage stability.

-Manually settable data indication mark-Mark on aperture value side because aperture can be set in A mode of Figs. 29a and 29b When TA2 is turned on and the shutter speed is The mark TA1 is turned off.

Similarly, in the S mode of FIGS. 30A and 30B, that is, in the shutter priority mode, since the shutter time can be set, the shutter time on the shutter time side is set. The mark TA1 is turned on and the aperture value that cannot be set The mark TA2 is turned off.

Figures 31a and 31b show that both values can be set in the manual (M) mode, so both Marks TA1 and TA2 are lit to indicate that both can be set.

In the P mode of FIG. 28, since there are no settable numerical values, both marks are extinguished, and the meaning is clearly shown.

The turning on and off of these marks is controlled by using the AE mode information by j72 and j73 as they are.

However, if it is determined that there is no lens by the function for determining the presence or absence of a lens (not shown), the aperture of the lens cannot be set. Therefore, in this case, the setting mark TA2 regarding the aperture is specially set not to light regardless of the mode. This is controlled by the q40 signal shown in FIG.

-Open F-number display-The aperture value display is a numerical display of 7 segments as shown in FIGS. 28 to 31. The details of the aperture value are shown in FIG. Here, the “q40” signal indicates a state equivalent to that without a lens in −− display. 0.5E for "q43" to "q62"
The aperture value is rounded for each V. On the other hand, as the lens open F value, there are numerical values such as 3.5 and 4.5 that have been popular since the past. However, these values are values that do not ride on the aperture value for each 0.5 EV, so these values are treated specially and are prepared as the "q41" and "q42" signals. In this way, the result of the calculation by the CPU 10 or the set aperture value is the open value (the determination is made by the open signal (not shown)). In some cases, the normal display of 3.
A display signal is given from the CPU 10 so as to display 3.5 or 4.5 instead of 4 or 4.8. or,
When the result of the calculation by the CPU 10 or the set aperture value is not the open value, the normal display is 3.4 or 4.8.
Etc. are displayed.

The above two series of display modes are provided.

As an example, a display example of the open F value is shown in FIGS.

The determination of the open F value is performed as follows, for example.

As shown in FIG. 40, in step S1, the control CPU 10
Reads the open F value Avo from the lens 3 and stores it in the internal register. On the other hand, the CPU 10 determines Avo = Av in step S3 by using the calculated F value Av calculated in step S2 based on the setting value of the camera and the value obtained from the photometric result. If Avo = Av, the open F value Avo is obtained. (Step S4), if Avo ≠ Av, the calculated F value Av is 0.5E
Each V is rounded and taken out (step S5), j12 to j
The 16 pieces of data (AvDSP) are determined, and the extracted outputs are displayed on the display units 4 and 6 (step S6).

-Dual display of override amount and metered manual amount- + 6.5 in Fig. 31b is the deviation amount of the metered manual, and is always lit when the manual is the internal display of the finder. The range displayed is +6.5.
It is ˜−6.5 EV (see FIG. 20), and when the amount is exceeded, +6.5 and −6.5 flash and display. As the data at the time of blinking, M'dMOVER of j61 data is "H
igh ”.

Further, +1.5 in FIG. 33b is the override amount,
It always appears depending on the setting in AE mode other than manual mode. Similarly, it is only the internal display of the finder.
The range to be displayed is +4.0 to -4.0 EV (see FIG. 20) and cannot be set beyond that amount. At this time, the display of the override is constantly blinking, and at the same time as distinguishing it from the metered manual, attention is paid to the setting of the override.

On the external display, +/- symbols (OR +,
OR-, ORS) is turned on, but the +/- symbols (OR +, OR-, ORS) are turned off and not displayed during metered manual.

Since the data of each quantity of the override and metered manual is received using the same register,
A separate identification signal is required. The signal is j54
.About.j56 data SIGN signal.

Table 3 shows the relationship between the data contents of j54 to j56 and the output display state thereof. This is to make the parts relating to j54 to j56 in FIGS. 21 to 23 easier to understand.

-Mode display of S and A-Display modes are shown in Figs. 29b and 30b. FIG. 29b shows the display in the A mode, and the A mode display portion with an arrow is turned on toward the display of the manually set aperture value. FIG. 30b shows the display in the S mode, in which the S mode display portion indicated by an arrow is turned on toward the manually settable shutter speed value. By doing so, the meaning of the mode display and the meaning of the numerical value display can be understood at a glance, and the mode display is very easy to use.

38A and 38B show the display contents at the time of initial loading after the film is mounted. During film initial feeding during the initial load period, the shutter speed is controlled to 1/4000 second and the aperture value is controlled to the minimum (F22 in this case). At that time, all the display of the exposure mode has disappeared, but this sets the j75 bit to "High" to erase the mode display.

39a and 39b show the display contents when the lens is not attached. When the CPU 10 detects that there is no lens by a mechanism (not shown), all of j12 to j16 for display are set to "Low". This is done in step S18 of the flow chart of FIG. 41, and the decoder of the display which received it outputs the q40 signal of FIG. 20 and sets r62 of FIG.
Therefore, “-” is displayed as the aperture value, and the aperture value side mark TA2 of the settable mark disappears.

Note that FIG. 42 shows another embodiment for displaying the camera shake of the internal display section 6. In this case, as shown in (a) of the figure, 3
It consists of two segments, and two of these segments are lit to indicate the camera type. There are two types of selection of these two segments, (b) and (c).
The camera shake is displayed by alternately lighting the seeds.

An outline of the operation of the control CPU 10 is shown in FIG. When the battery is installed, the CPU 10 starts operation from reset start (step S0). At the same time, the voltage is applied to the display circuit. First, the camera is initialized both inside and outside the CPU 10 (step S10), and subsequently, display data, turn-off data, standby data, ISO data, etc. are sent out n times for the display circuit (step S11). (N is a value determined according to the time until the display circuit guarantees a normal operation) When the sending is completed, the interrupt from the switch group (not shown) is permitted (step S12). If there is nothing, the internal operation clock is stopped to enter the stop state (step S1).
3). Of the switch group (not shown), the photometric switch S1
Or, the initial load switch SB is the main switch S
There is a relationship with M as shown in FIG. 44, and the other switch groups have the same configuration as S1 and SB. When the main switch SM is off, S1 and SB inputs are pulled down and S
1, S2 input is dead. In this state, only the SM signal generates the INTset signal which generates an interrupt. When the main switch SM is turned on and an INT set signal is generated, an INT flip-flop (not shown) is set, and the CPU 10 causes the interrupt operation INT (step S1).
4) Enter. This INT flip-flop is designed to be set at the rising edge, and interrupts are enabled (step S1
At 2), the INT flip-flop is reset and waiting for another interrupt.

When the switch enters the INT (step S14), the switch SB for detecting the initial load state is checked (step S15). If the switch SB is OFF (not in the initial state), power is supplied to a photometering circuit (not shown) or the like to perform step S15.
Start photometry at 16. After that, AE calculation is performed in step S17, display DATA required for the display circuit is prepared, and it is sent out in step S18. After that, main switch S
If M is checked in step S19 and turned off, data for turning off is sent as display DATA in step S20, power supply is stopped, and photometry is stopped in step S21. After that, the process proceeds to steps S12 and S13. If the main switch SM is turned on in step S19, the switch S1 is checked (step S26). When the main switch SM is turned off, data for standby display is sent as display DATA and the process proceeds to steps S16, S21, S12 and S13.
If it is turned on in step S26, the release switch S2 is checked in step S22. If it is ON, exposure control (step S23) is performed, and step S17
If it is OFF, the process proceeds to step S17 without doing anything, and the AE calculation is performed again.

On the other hand, if the switch SB for detecting the initial load state is ON in step S15, the second value and aperture value for initial load and MODE OFF information j75 data = “High” are sent out in step S24. Then, the initial load for controlling the shutter mechanism is performed by the time value and the aperture value (step S25). After that, the operation of checking the switch SB is performed again in step S15, and depending on the state of the switch SB, the photometric start of step S16 is started.

To move from step S13 to step S14, as shown in FIG. 44, although SM, S1, and SB switches are used, SM is OF
When F, S1 and SB switches are in "Low" state,
Dead as a switch signal. Therefore, the INTset signal is generated only when SM is turned on, and the interrupt (INT) operation is started. Also, when SM is ON, S1, S
B switch comes alive and INTse by S1 or SB
A t signal is generated and an interrupt (INT) operation starts.

Although not shown, the SB switch turns on when it detects the presence of a film and when the back cover is closed, and turns off when the film counter (not shown) becomes 1.

FIG. 43 is a flow chart showing the operation for detecting camera shake, and in step S31 the CPU 10 reads necessary information such as the focal length from the lens. Then, in step S32, the TV value for shutter control is calculated by the exposure calculation, and the TVL value of the camera shake warning limit is calculated from the lens information. Then, in step S33, TV and T
If it is TV <TVL, YES is selected and the operation proceeds to step S34 if TV > TVL, and NO is selected and the operation proceeds to step S35. In step S34, the LOWSS signal is set to "High" to vibrate the marks CA1 and CA2 to give a hand shake warning. In step S35, the LOWSS signal is set to "Low" to turn off the marks CA1 and CA2.

FIG. 44 shows the CPU 10 and the switches S1, S2, SB, S
The relationship with M is shown.

<Combination of r2n and Bm> B1-r51-r53, r61-r65 B2-r54 B3-r55-r58, r67, r68 B4-r1-r29 B5-r30-r43 B6-r59, r60 B7-r44-r50 B8- r66 As described above, according to the present invention, when the aperture value is displayed on the display device of the camera, when the aperture value determined by calculation or setting is the open aperture value of the lens, the predetermined E
It is not displayed using the aperture value for each unit of V, but is displayed using the open aperture value of the lens at that time. With this configuration, when the lens is operated to open, an aperture value different from the aperture value data for that lens will not be displayed, and an aperture that cannot be achieved with that lens will actually be achieved. Since the value is not displayed, the photographer is not confused by the displayed data, and the photographing is not interrupted by misunderstanding that a failure has occurred.

Further, when the aperture value determined by the calculation or setting is the open aperture value, it can be clearly understood from the displayed aperture value, so that a more reliable display device can be provided.

[Brief description of drawings]

1 is a perspective view showing an example of a camera to which the present invention is applied, FIG. 2a is a front view of a viewfinder of the camera of FIG. 1, and FIG. 2b is an external display portion of a display device of the present invention. 2c shows an example of all segments displayed, FIG. 2c shows an example of all segments displayed on the internal display section of the display device of the present invention, and FIG. 3 is a block diagram showing one embodiment of the present invention. , FIG. 4 is a detailed circuit diagram of the oscillation frequency divider of FIG. 3,
FIG. 5 is a detailed circuit diagram of the common driver of FIG. 3, FIG.
FIG. 7 is a detailed circuit diagram of the segment driver shown in FIG.
FIG. 8 is a detailed circuit diagram of the data latch unit of FIG. 3, FIG. 8 is a detailed circuit diagram of the decoder unit of FIG. 3, and FIG. 9 is a detailed circuit diagram of the switch circuit SW1 of FIG. FIG. 11 is a circuit diagram showing details of symbols in the circuit, FIG. 11 is a detailed circuit diagram of the data conversion section, and FIG. 12 is a switch circuit SW2 of FIG.
Detailed circuit diagram of Fig. 13, Fig. 14, Fig. 15 and Fig. 8 are
16 is a detailed circuit diagram of the segment decoder shown in FIG. 16, FIG. 16a is a detailed circuit diagram of the output control unit shown in FIG. 8, and FIG. 16b is a detailed circuit diagram of a part of the circuit shown in FIG. To FIG. 20 are diagrams showing the relationship between the input signal and the display, FIG.
FIGS. 23 to 23 are detailed circuit diagrams of the data conversion unit shown in FIG. 8, FIG. 24 is a detailed circuit diagram of the voltage generation unit shown in FIG. 3, and FIGS. 25 to 27 are circuit diagrams shown in FIG. Waveform diagram of the main part,
28a, 28b to 34a, 34b, 35 show various modes of display, FIG. 36 shows the relationship between signals and registers, FIG. 37. a, b,
c, FIGS. 38a and 38b, 39a and 39b are views showing various modes of display, and FIG. 40 is a CPU showing a display selecting operation.
41, FIG. 41 is a flowchart showing the operation of the CPU of FIG. 3, FIG. 42 is a view showing another mode of the camera shake display, FIG. 43 is a flowchart of the CPU showing the operation of the camera shake display, and FIG. FIG. 4 is a circuit diagram showing details of part of the CPU in FIG. 3. 4 ... External display unit, 6 ... Internal display unit, 10 ... CPU, 22
... data latch, 23 ... decoder, 24 ... segment driver.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akihiko Fujino 2-30 Azuchi-cho, Higashi-ku, Osaka City, Osaka Prefecture Osaka Osaka Building Minolta Camera Co., Ltd. (72) Inventor Kunio Kawamura 2-chome, Azuchi-cho, Higashi-ku, Osaka City, Osaka Prefecture No. 30 Osaka International Building Minolta Camera Co., Ltd. (72) Inventor Yutaka Zaibu 2-chome, Azuchi-cho, Higashi-ku, Osaka-shi, Osaka No. 30 Osaka University Building Minolta Camera Co., Ltd. (72) Inventor Masatake Niwa Osaka-shi, Osaka 2-30 Azuchi-cho, Osaka, Osaka International Building Minolta Camera Co., Ltd. (56) Reference JP-A-51-37640 (JP, A)

Claims (1)

[Claims] 1. A camera comprising a taking lens, an aperture value determining means for determining an aperture value of the taking lens by calculation or setting, and a display means for displaying the aperture value determined by the aperture value determining means. Data output means for outputting data indicating the open aperture value of the taking lens, comparison means for comparing the aperture value determined by the aperture value determination means with the aperture value output from the data output means, When the determined aperture value is different from the open aperture value according to the comparison result of the comparison means, the determined aperture value is displayed by using the aperture value in units of a predetermined EV, while the determined aperture value is determined. When the aperture value is equal to the open aperture value, display control means for controlling the display means to display the open aperture value is included. Display devices.