JPH0693174B2 - Digital control display monitor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a digital control display monitor that performs an automatic tracking operation according to the frequency of an input video signal and other input conditions, and particularly relates to a frequency automatic operation without using a variable resistor. It is related to what was made to follow.

[Prior Art] FIG. 11 is a circuit diagram showing a control circuit of a conventional frequency automatic tracking type display monitor. In FIG.
FV conversion circuit, (2) and (3) are comparator ICs connected to HAFV conversion circuit (1), (4) and (5) are feedback resistors, (6), (7) and (8) are reference voltage setting Resistor, (9) and (10) are transistors for current amplification connected to the outputs of the comparator ICs (2) and (3),
(11), (12), (13) and (14) are voltage dividing resistors, (15)
Is a transistor for switching the base potential of the transistor (9), (16) and (17) are voltage dividing resistors that determine the base potential of the transistor (15), (18) and (19) are pull-up resistors, (20) Is a transistor, (21) is a load resistance of the transistor (20), (22) and (23) are voltage dividing resistors for determining the base potential of the transistor (20), and one end of (22) is a diode (24) and ( 25) connected to the emitters of transistors (9) and (10). (2
6) is a current amplification transistor, and (27) is its emitter resistance. Also, (28) and (29) are analog switch ICs driven by transistors (9), (10) and (26), (30), (31), (32), (33) and (34).
Reference numerals and (35) are variable resistors connected to the analog switch ICs (28) and (29), and reference numerals (36) and (37) are voltage dividing resistors with the variable resistors.

FIG. 12 is a block diagram of a conventional frequency automatic tracking type display monitor. (38) is a CRT, (39) is a video circuit including a sync separation circuit, (40) is a deflection circuit, (41).
Is a high voltage circuit, (42) is a power supply circuit, and (43) is a control circuit.

Next, the operation will be described. A horizontal or vertical synchronizing signal is applied to the input terminal I of the FV conversion circuit (1). In this circuit, the case where the horizontal synchronizing signal is applied will be described, but the same applies when the vertical synchronizing signal is applied. From the output terminal O of the FV conversion circuit (1), the frequency of the horizontal synchronizing signal applied to the input terminal I is converted to the voltage V ₁ and output.
It is input to the comparators (2) and (3). Further, the voltages V ₂ and V ₃ divided by the resistors (6), (7) and (8) are applied to one of the input terminals of the comparators (2) and (3). Here, the divided voltage is V ₂ > V ₃ .

When the voltage is V ₁ <V ₂ <V ₃ , the output voltage of the comparator (3) becomes “H” and the emitter voltage of the transistor (10) connected to the output terminal of the comparator (3) rises.
Therefore, the midpoint potential of the resistors (16) and (17) also rises and the transistor (15) is turned on, so that the base voltage of the transistor (9) drops and the emitter voltage drops. The emitter voltage of the transistor (10) is applied to the resistors (22) and (23) via the diode (25), the midpoint voltage rises, and the transistor (20) turns on. As a result, the base voltage of the transistor (26) drops and the emitter voltage also drops. Therefore, in this case, among the emitter voltages of the transistors (9), (10), and (26), only the emitter voltage of the transistor (10) becomes “H”, so that the resistance (13) and (14) are The point voltage is applied to the input terminals of the analog switch ICs (28) and (29). As a result, the corresponding variable resistors (31) and (34) are connected to the resistors (36) and (37), respectively, and the output terminals A and B respectively have the variable resistor (31) and the resistor (31). 3
6), the voltage determined by the variable resistor (34) and the resistor (37) is output.

When the voltage is V ₃ <V ₁ <V ₂ , the output voltage of the comparator (3) becomes “L”, the emitter voltage of the transistor (10) decreases, and the transistor (15) turns off.
Further, since the output of the comparator (2) becomes "H", the emitter voltage of the transistor (9) also rises, this voltage is applied to the resistors (20) and (23) through the diode (24), and the transistor (9) is applied. (20) turns on, and the transistor (2
The emitter voltage of 6) also drops. Therefore, in this case, among the emitter voltages of the transistors (9), (10) and (26), only the emitter voltage of the transistor (9) becomes “H”, so that the midpoint voltage of the resistors (11) and (12). Is applied to the input terminals of the analog switch ICs (28) and (29). As a result, the corresponding variable resistors (30) and (33) are connected to the resistors (36) and (37), respectively, and the output terminals A and B are respectively connected to the variable resistor (30) and the resistor (3).
6), the voltage determined by the variable resistor (33) and the resistor (37) is output.

On the other hand, when the voltage is V ₃ <V ₂ <V ₁ , the outputs of the comparators (2) and (3) are both “L” and the transistor (9)
The emitter voltage of the transistors (10) becomes "L", the transistor (20) is turned off, and the base voltage and the emitter voltage of the transistor (26) rise. Therefore, in this case, of the emitter voltages of the transistors (9), (10) and (26), only the emitter voltage of the transistor (26) becomes "H", and this voltage is the analog switch IC (28).
And (29) input terminals. As a result, the corresponding variable resistors (32) and (35) are connected to the resistors (36) and (37), respectively, and the variable resistors (32) and the resistors (36) are respectively connected to the output terminals A and B. , A voltage determined by the variable resistor (35) and the resistor (37) is output.

The outputs from the output terminals A and B are used to control circuits such as the deflection circuit (40), the high voltage circuit (41) and the power supply circuit (42) via the video circuit (39). That is, the horizontal synchronizing signal frequency is classified by the frequency thresholds determined by the resistors (6), (7) and (8), and the variable resistors (30) to (35) are switched according to the classified frequency region. By adjusting in advance, each controlled circuit can perform an optimal operation in each frequency region.

[Problems to be Solved by the Invention] Since the above frequency auto-following display monitor is configured as described above, the number of variable resistors must be increased in order to increase the control target and control items of the control circuit. However, since it is necessary to mechanically adjust each variable resistor, the adjustment time becomes long, which is disadvantageous in terms of production efficiency. Also,
The interface of the automatic adjustment device becomes large,
There are problems that the operation near the frequency discrimination threshold becomes unstable and it is difficult to prepare different operating conditions at the same frequency.

Therefore, there is a problem that the above problems must be solved.

The present invention has been made to solve such a problem, and can perform automatic frequency tracking without using a variable resistor, and can also be connected to an automatic adjustment device by a simple interface, and can also input signals. An object of the present invention is to obtain a digital control display monitor capable of performing stable control even near the frequency threshold value, preparing different operating conditions at the same frequency, and selecting the content thereof.

[Means for Solving the Problems] A digital control display monitor according to the present invention is provided with a non-volatile memory for storing control data in a control circuit, and a counting means for counting a sync signal frequency,
A means for reading control data into the built-in RAM, a means for changing control data in the built-in RAM, a means for writing control data to a non-volatile memory, an output means for an external output IC, and an external measurement control device. And a communication means.

[Operation] In the digital control display monitor according to the present invention, the microcomputer in the control circuit measures the frequency of the synchronizing signal of the input video signal, classifies the results,
It has a means for accessing the non-volatile memory corresponding to the classification result and a means for accessing the non-volatile memory for the data corresponding to the data input using the input means such as the rotary switch from the input port. It outputs control data determined by the frequency and communicates with an external measurement control device.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, (44) is a microcomputer in a control circuit, (45) is a connector connected to the microcomputer (44), (46) is a connector paired with the connector (45), and (47). Is a light emitting diode connected to the input terminal D ₀ of the microcomputer (44) via the connectors (45) and (46), and (48) is a light emitting diode of the microcomputer (44) via the connectors (45) and (46). Input terminal
Switch connected to D ₁ , (49) is input terminal of microcomputer (44) via connectors (45) and (46)
Rotary switch connected to R _{01 to} R ₀₄ , (50) is a rotary switch connected to input terminals R _{11 to} R ₁₄ of the microcomputer (44) via connectors (45) and (46), (51) , (52), (53) and (54) are connected to the microcomputer (44) via the connectors (45) and (46).
Tact switch connected to the input terminals R _{21 to} R ₂₄ of the (5
5) is the output terminal D ₈ , D ₁₀ , of the microcomputer (44),
Non-volatile memory connected to input terminal D ₉ and input / output terminals R _{51 to} R ₅₄ , (56) is a D / A converter IC connected to output terminals D ₅ , D ₆ and D ₇ of the microcomputer (44) ,(Five
7) is the output terminal R ₄₁ ~ of the microcomputer (44)
A latch IC connected to R _4n and D ₄ (58) is a latch IC connected to the output terminals R _{41 to} R _4n and D ₃ of the microcomputer (44). In addition to the ROM in which the control program is written, the microcomputer (44) has a built-in RAM, an external event counter, an internal timer and the like.

Next, the operation and operation of the embodiment will be described with reference to the flowcharts of FIGS. 2A and 2B.

After the power is turned on, the microcomputer (44) operates according to the control program written in the internal memory. First, I /
Initializes the O port, RAM, various timers, interrupt control flags, masks, etc., D / A converter (56), latch IC (5
7) and (58) etc. Initialize the peripheral output devices. Next, the non-volatile memory (55) is accessed and basic data such as screen brightness and a horizontal sync signal frequency discrimination flag described later are read into the internal RAM. Next, using the internal external event counter and internal timer, the signal frequency of the horizontal sync signal input to the EXCT pin (external event counter input pin)
Signal frequency of vertical sync signal input to F _H and INTO pins
The f _V, counted by the following method.

That is, FIGS. 3 (a), (b) and (c) are schematic diagrams showing the counting method. Specifically, the vertical synchronizing signal shown in FIG. 3 (a) is input to the microcomputer (44) INTO.
The horizontal synchronizing signal shown in FIG. 7C is input to the input EXCT terminal of the microcomputer (44).
Inside the microcomputer (44), the frequencies f _H and f _V of the vertical synchronizing signal and the horizontal synchronizing signal are respectively counted by using the internal pulse of FIG. 3 (b) depending on the system clock which is the operation reference. To do. That is, by counting the number of internal pulses of the microcomputer (44),
The frequency f _V of the vertical synchronizing signal is counted, and a certain period T in one cycle of the vertical synchronizing signal is designated by an internal pulse of the microcomputer (44), and the horizontal synchronizing signal input to the input EXCT terminal during that period. The frequency f _H of the horizontal synchronizing signal is counted by counting the number of pulses of. here,
Horizontal sync signal frequency f _H and vertical sync signal frequency f _V
Is counted, and the stability of the signal is determined by confirming that the variation falls within a certain value. Next, the horizontal synchronization signal frequency f _H and the vertical synchronization signal frequency f _V are counted again by the above method, and it is determined whether or not the values are within a preset frequency range, and the count result is normal or abnormal. To judge. Here, if it is determined to be normal, the process proceeds to the next step, and if the result is abnormal, the process returns to the confirmation of signal stability again.

Next, HMODE1 is determined by classifying the count results of the horizontal sync signal frequency f _H in order of magnitude, and the determined HMODE1 data is shifted to the right by a certain number of bits to determine MSUB. FIG. 4 is a flow chart showing a means for obtaining HMODE1 from the horizontal synchronizing signal frequency f _H , and FIG. 5 is a schematic diagram thereof. That is,
The frequency count result of the horizontal sync signal and HMODE1
The table showing the correspondence relationship with is prepared in the memory inside the microcomputer, the count result is stored in the address modification registers X and Y, and the corresponding memory contents are stored in HM.
Store in ODE1. Similarly, VMODE1 is obtained from the frequency count result of the vertical synchronizing signal.

Next, depending on the contents of the input terminals R _{01 to} R ₀₄ of the microcomputer (44) to which the rotary switch (49) is connected,
Determine the channel to select the control operating state. here,
Channel 0 is called a lower channel, and 1 to n are called upper channels. n is an arbitrary constant whose upper limit is determined by the number of output bits of the rotary switch (49). If the content of the input terminal is 0 channel, it is determined to be the lower channel, and HMODE1 is corrected by the procedure described below. FIG. 6 is a schematic diagram showing the relationship between HMODE1 and MSUB and control data. In the figure, the memory A is a part of the non-volatile memory (55) and has a one-to-one correspondence with HMODE1. Memory B and memory C are also external non-volatile memory (55)
The memory B corresponds to HMODE1 in a one-to-one correspondence, and the memory C corresponds to a plurality of HMODE1 and also corresponds to MSUB in a one-to-one correspondence. The memory A is a horizontal synchronization signal frequency discrimination flag for preventing the screen control data from fluctuating due to the external environment or variations in the input signal frequency when switching the control operation, including when the power is turned on. Stores control data. When the power is turned on, the contents of the memory A are all read by the nonvolatile memory (55) into the built-in RAM of the microcomputer (44), and when the control data is changed by the external device or the user, it is corrected by the method described later. Later non-volatile memory (55) from the internal RAM of the microcomputer (44)
Is written to. Here, ± m (m is a constant, m = 2 in the case of FIG. 6) of the part where “1” stands in the memory A
The range (a) becomes the forced pull-in range, and the fluctuation of HMODE1 due to the minute change of the horizontal synchronizing signal frequency f _H is corrected.
In the case of FIG. 6, when the content of the memory A corresponding to HMODE1 = 4 is determined by the horizontal synchronizing signal frequency input when changing the screen control data, the HMOD
It is corrected to HMODE1 = 4 in the range of E1 = 2-6. After HMODE1 is modified, MSUB is obtained by shifting the contents of HMODE1 to the right (in the case of FIG. 6, right 2 bits are shifted). MS
When UB is determined, the screen control data is stored in the microcomputer (44) from the corresponding memory B and memory C.
Read into RAM. V in memory C when screen control data is changed
MODE1 is stored and VMODE1 ′ read here
And VMODE1 determined by the count result of the vertical synchronizing signal frequency f _V are compared, and if the difference is within a certain range, the content of the memory C is set to VMODE1.

Further, it is determined as the upper channel by the contents of the input terminals R _{01 to} R ₀₄ of the microcomputer (44) to which the rotary switch (49) is connected. When the channel is “1”, it is horizontal (H).
And the vertical (V) sync signal polarity is determined by the sync signal polarity determination signal input to the D ₁₁ port and the D ₁₂ port. Further, in FIG. 7, the memory D is a non-volatile memory (55).
Which is a part of, and stores screen control data. The memory D is classified by the combination of H and V sync signal polarities, and the contents of the memory corresponding to the combination of H and V sync signals are read into the internal RAM of the microcomputer (44).

On the other hand, in the case of upper channels other than "1", the memory E corresponding to the channel is accessed as shown in FIG. The memory E is also a part of the non-volatile memory (55),
Screen control data is stored, and the data in the area designated by the channel is read into the internal RAM of the microcomputer (44).

The memory D and the memory E store HMODE1 'and VMODE1' when the screen control data is changed.
ODE1 ′ is compared with the value of HMODE1 determined by the count result of the horizontal sync signal frequency f _H , and if the difference is within a certain range, it is treated as the upper channel, and if the difference exceeds the certain range, it is treated as the lower channel. To do. If it is determined to be the higher channel, HMODE1 ′ is set to HMODE1 and VMOD is determined by the count result of the vertical sync signal frequency f _V.
Compare E1 with VMODE1 'in memory D or memory E,
If the difference is within a certain range, set VMODE1 ′ to VMODE1.

After the screen control data is read into the built-in RAM of the microcomputer (44) by the above procedure, the D / s connected to the output terminals R _{41 to} R _4n and D _{3 to} D _{7 of} the microcomputer (44).
The control data is output to the A converter (56) and the latch ICs (57) and (58).

The next step is the built-in microcomputer (44)
It is determined whether to write data to the non-volatile memory (55) by referring to the data write request flag in RAM and the input of the D ₁ port and D ₉ port. That is, the data write request flag is “1”, the input of the D ₁ port is “L”, and the D ₉ port to which the BUSY output of the nonvolatile memory (55) is connected is “H”.
Data is written only when. Here, the data write request flag is set in the data change process described later, and is reset when the predetermined data write process is completed.

Next, the contents of the input terminals R _{01 to} R ₀₄ of the microcomputer (44) are read to determine whether the channel has changed, and if a change is detected, return to the signal stability check. Further, the sync signal polarity discrimination signal is read from the D ₁₁ and D ₁₂ ports, and if a change is detected, the process returns to the signal stability check.
Next, the horizontal sync signal frequency f _H and the vertical sync signal frequency f _V
Based on the result of (1), HMODE1 ″ and VMODE1 ″ are determined, HMODE1 and VMODE1 determined in the previous stage are compared, and when the respective differences exceed a certain range, the process returns to the signal stability check.

Next, input terminals R _{21 to} R _{24 of} the microcomputer (44)
Is read to determine the key input, and when it is determined that the key is pressed, the data change process is performed. The procedure of this data change process is shown in the flowcharts of FIGS. 9A and 9B. In the figure, when the content of the D ₁ port is "H", that is, when the switch (48) is off, the switch (5
1) to (54) are switches for contrast control and bright control. That is, the switch (51)
When is on, the contrast data in the control data output RAM in the internal RAM is incremented and the switch (5
When 2) is ON, the same data is decremented. Similarly, when the switch (53) is on, RA for control data output
Increment the bright data of M and switch (5
When 4) is on, the data is decremented.

When the content of the input terminal D ₁ of the microcomputer (44) is “L”, that is, when the switch (48) is on, the switches (51) to (54) serve as a switch for increasing / decreasing control data and a memory switch. Become. Further, in this case, the switch (50) serves as a control data type selection switch. That is, the switch (51)
When turned on, the built-in RA specified by the switch (50)
Increment control data on M and switch (52)
When is turned on, the same data is decremented. When the switch (54) is turned on When the channel designated by the rotary switch (49) is "0", the horizontal sync signal frequency determination flag setting process is performed. The processing means in this case is the tenth
It is shown in the flow chart of the figure. First, the horizontal sync signal frequency
HMODE1 is determined by the count result of f _H , and then this HMOD
Check the horizontal sync signal frequency discrimination flag (in the built-in RAM) corresponding to the range of E1 ± 2m. If "1" is set in any of them, it means that the corresponding memory area is occupied by control data other than the target operating state.
Check the LED blinking flag on the RAM, and if the flag is "0", set it to "1" and blink the light emitting diode (47) to issue a warning and end the processing. If the LED blinking flag is already set, all horizontal synchronization signal frequency discrimination flags corresponding to the range of HMODE1 ± 2m are set to “0”. Then, the horizontal sync signal frequency flag corresponding to HMODE1 is set to "1", the LED blinking flag is set to "0", and the processing ends.

The flowchart of FIG. 9 will be described again. After the horizontal sync signal frequency discrimination flag setting process of the channel "0" is completed, the address in the memory C of the nonvolatile memory (55) is determined by the MSUB and the data write request flag is set. When the channel is "1", the address in the memory D determined by the channel and horizontal and vertical sync signal polarities is determined,
Set the data write request flag. At this time, HMODE1 and VMODE1 at the time of writing to memory D are HMODE
Written as 1 ', VMODE1'. When the number of channels is "2" or more, the address in the memory E is determined by the designated channel and the data write request flag is set. At this time, HMODE1 and VMODE1 are written in the memory E as in the case of channel "1".

When the switch (48) is on, HMODE1 determined by the count result of the horizontal sync signal frequency f _H and VMODE1 determined by the count result of the horizontal sync signal frequency f _V are positive, and HMODE1 and VMODE1 are not corrected. I shall. When the switch (48) is turned on, the above HMODE1, VM
The control data in the memory area of the non-volatile positive memory (55) determined by either the channel designated by the ODE1 or the rotary switch (49) and the polarity of the synchronization signal is read into the built-in RAM.

Returning to FIG. 2 again, description will be made. After the above data change processing is completed, the screen control data is latched by ICs (57), (58)
And to the D / A converter (56). If the LED blinking flag is "1", the light emitting diode (47) is blinked, and if the data write request flag is "1", the light emitting diode (47) is turned on. In this case, the first
When the connector (46) is removed from the connector (45) shown in the figure and an external measurement control device is connected instead, automatic adjustment can be performed, but in the next step, communication processing therefor is performed. Then, the process returns to the previous step and the process is started by checking the data write request flag.

The control operation is performed in the above procedure.

In the above embodiment, the polarity of the synchronization signal is determined and the channel for switching the control state is only "1", but other channels may be similarly processed.

[Effects of the Invention] As described above, the present invention uses a control circuit such as a microcomputer, a non-volatile memory, a D / A converter, a latch IC, and a control operation selection switch to make the operation state uncertain when changing control data. By storing it in the memory, the operation following various input conditions can be stably performed, and automatic adjustment can be performed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a control circuit of a digital control display monitor according to an embodiment of the present invention, and FIGS. 2A and 2B are flow chart diagrams showing an entire flow of a control program of a microcomputer according to the present invention.
The figure is a timing chart showing the relationship between the vertical sync signal, the horizontal sync signal, and the pulses used to count them. Fig. 4 shows the horizontal sync signal frequency to HMOD in the control program.
FIG. 5 is a flow chart showing a procedure for obtaining E1, FIG. 5 is an explanatory view of a table used at that time, FIG. 6 is a schematic diagram showing a nonvolatile memory corresponding to a lower channel, FIG. 7 and FIG. FIG. 9 is a schematic diagram showing a corresponding non-volatile memory, FIG. 9 is a flow chart showing the procedure of data change processing, FIG. 10 is a flow chart showing the procedure of setting the horizontal sync signal frequency discrimination flag, and FIG. 11 is a conventional input. Control circuit diagram of the frequency automatic tracking type display monitor,
FIG. 12 is a block diagram of a conventional frequency automatic tracking type display monitor. In the figure, (44) is a microcomputer, (45),
(46) is a connector, (47) is a light emitting diode, (48) is a switch, (49) and (50) are rotary switches, and (5
1) to (54) are switches, (55) is non-volatile memory, (5
6) is a D / A converter IC, and (57) and (58) are latch ICs. In the drawings, the same reference numerals indicate the same or corresponding parts.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04N 3/27 7337-5C 5/04 Z 9070-5C 5/44 Z

Claims (1)

[Claims] 1. A digital device having a control circuit for automatically controlling a synchronizing signal frequency of an input video signal and other input conditions to control each circuit such as a horizontal deflection circuit, a high voltage generating circuit, a video circuit and a power supply circuit. In the control display monitor, the control circuit includes a non-volatile memory for storing control data of each circuit, is connected to a D / A converter IC and a latch IC for outputting the control data, and controls A switch for selecting an operating state, an LED for displaying an internal state and the like, and a switch used for changing the control data and a counting means for counting horizontal and vertical synchronizing signal frequencies connected via a connector. And classify the results counted by the counting means, and correspond to the results and the state of the control operation selection switch stored in the nonvolatile memory. Built-in RA for the control data
Reading means for reading into M, changing means for changing control data in the built-in RAM, writing means for writing control data from the built-in RAM to the non-volatile memory, and control data in the built-in RAM A digitally controlled display monitor, comprising: output means for outputting the output to an external output IC; and communication means for communicating with an external measurement control device.