JPH0697307A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To facilitate the making of LSI packages with multi-pins, improve the heat dissipation, and reduce the noise due to the inductance of the leads. CONSTITUTION:A conductive plate 3 is provided on the bottom surface of a package main body 2 in which a semiconductor chip 5 is encapsulated, and the conducive plate 3 and the GND pad 6a of the semiconductor chip 5 are connected via a wire 7. In addition, the conductive plate 3 and a mounting substrate 9 are electrically connected through a solder bump 8 coupled with the underside of the conductive plate 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when applied to an LSI package encapsulating a semiconductor chip.

[0002]

2. Description of the Related Art Conventionally, in an LSI package such as a QFP (Quad Flat Package), a large number of leads (outer leads) are projected from the side surface of the package body encapsulating the semiconductor chip, and the semiconductor chip is connected via these leads. It has a structure for electrical connection with the mounting board. In this case, the electrical connection between the power supply pad and the GND pad of the semiconductor chip and the mounting board is performed through the leads, similarly to the electrical connection between the signal pad and the mounting board.

[0003]

In recent years, the number of pins of the QFP has been increased along with the higher functionality and higher speed of the logic LSI, and the lead width and pitch have become finer. Defects such as solder bridges and lead floating during board mounting are likely to occur.

Further, since the amount of heat generated by the semiconductor chip is increasing with the increase in functionality and speed, it is an important issue to improve the heat dissipation of the LSI package.

Furthermore, since the external dimensions of the package main body have become larger with the increase in the number of pins, the lead length from the semiconductor chip to the mounting substrate becomes long electrically, and the lead for power supply and the lead for GND are also increased. Since the inductance increases, the simultaneous switching noise of signals increases, and malfunctions are likely to occur.

Therefore, an object of the present invention is to provide a technique capable of promoting the increase in the number of pins of an LSI package.

Another object of the present invention is to provide a technique capable of improving the heat dissipation of the LSI package.

Another object of the present invention is to provide leads for power supply and G
An object of the present invention is to provide a technique capable of reducing noise caused by the inductance of the ND lead.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

The LSI package of the present invention has a semiconductor chip power supply pad or GN on the bottom surface of the package body.
A conductive plate electrically connected to the D pad is provided, and the power supply pad or the GND pad and the mounting board are electrically connected via the conductive plate.

[0012]

According to the above-mentioned means, by electrically connecting the pad for power supply of the semiconductor chip and the pad for GND to the mounting substrate through the conductive plate provided on the bottom surface of the package body, the conventional package is used. Power supply leads and GND leads on the side of the body are no longer required,
Since the number of signal leads can be increased accordingly, the number of pins of the LSI package can be increased.

According to the above-mentioned means, by electrically connecting the power supply pad of the semiconductor chip and the GND pad to the mounting board through the conductive plate provided on the bottom surface of the package body, Since the inductance of the wiring path from the power supply pad or the GND pad to the mounting substrate can be reduced, noise caused by this inductance can be reduced.

According to the above means, the heat of the semiconductor chip can be released to the outside through the conductive plate provided on the bottom surface of the package body, so that the heat dissipation of the LSI package can be improved.

[0015]

[Embodiment 1] A configuration of an LSI package according to an embodiment of the present invention will be described below with reference to FIG.

In the LSI package 1 of the first embodiment, a conductive plate 3 is provided on the bottom surface of a package body 2 made of a synthetic resin molded body. The conductive plate 3 is made of a metal plate such as Cu, and its lower surface is almost entirely exposed to the outside of the package body 2.

A semiconductor chip 5 is mounted on the center of the upper surface of the conductive plate 3 via an adhesive 4 or the like. The pad 6a for GND provided on the element forming surface of the semiconductor chip 5 and the conductive plate 3 are mounted. And are electrically connected via a wire 7 such as Au.

Solder bumps 8 are bonded to the lower surface of the conductive plate 3, and the GND footprint 10a of the mounting substrate 9 and the conductive plate 3 are electrically connected via the solder bumps 8. Has been done.

The solder bumps 8 are previously formed on the lower surface of the conductive plate 3 by the solder dipping method. Alternatively, the solder bumps 8 may be formed using a solder paste.
A solder resist 11 for preventing diffusion of solder is provided on the lower surface of the conductive plate 3.

On the other hand, in the periphery of the upper surface of the conductive plate 3,
A signal lead 13 and a power supply lead 13b are joined via an insulating film 12 such as a polyimide resin. The leads 13 and 13b are made of a lead frame material such as 42 alloy or Cu.

One end (inner lead) of the signal lead 13 is electrically connected to the signal pad 6 of the semiconductor chip 5 via the wire 7 and protrudes outward from the side surface of the package body 2. The ends (outer leads) are soldered onto the signal footprint 10 of the mounting substrate 9.

The inner lead of the power supply lead 13b is electrically connected to the power supply pad 6b of the semiconductor chip 5 via the wire 7, and the outer lead of the power supply lead 13b is mounted on the mounting substrate 9 by the power supply footprint 10b. Soldered on.

As described above, the LSI package 1 according to the first embodiment has the wires 7, the conductive plate 3, and the solder bumps 8.
The GND pad 6a of the semiconductor chip 5 and the mounting board 9 are electrically connected via the same, while the signal pad 6 and the power supply pad 6b are electrically connected to the mounting board 9 by the conventional method. It is performed via the wire 7 and the lead 13 (13b).

According to the first embodiment configured as described above, the following effects can be obtained.

(1) By electrically connecting the GND pad 6a of the semiconductor chip 5 and the mounting substrate 9 through the conductive plate 3 provided on the bottom surface of the package body 2, the side surface of the package body 2 is conventionally formed. Since the GND lead provided in the LS becomes unnecessary and the number of the signal lead 13 and the power supply lead 13b can be increased accordingly, the LS
The number of pins of the I package 1 can be promoted.

(2) By electrically connecting the GND pad 6a of the semiconductor chip 5 and the mounting substrate 9 through the conductive plate 3 provided on the bottom surface of the package body 2, the GND of the semiconductor chip 5 is connected. Since the inductance of the wiring path from the pad 6a to the mounting substrate 9 can be reduced, the noise caused by this inductance can be reduced.

(3) Since the conductive plate 3 is provided on the bottom surface of the package body 2, the heat of the semiconductor chip 5 can be released to the outside through the conductive plate 3.
The heat dissipation of the LSI package 1 can be improved.

(4) By supplying solder to the lower surface of the conductive plate 3 to control the amount of solder when the solder bumps 8 are formed, the contraction force of the solder bumps 8 is used to make the leads 13, 1
Since 3b can be pressed against the footprints 10 and 10b, the leads 13 and 13b and the footprint 1
The connection reliability of 0 and 10b can be improved.

[0029]

Second Embodiment As shown in FIG. 2, in an LSI package 1 of the second embodiment, the conductive plate 3 of the first embodiment is divided into two, and one side (3a) of a semiconductor chip 5 is connected via a wire 7. While being electrically connected to the GND pad 6a,
The other side (3b) is electrically connected to the power supply pad 6b.

Further, one conductive plate 3a is electrically connected to the GND footprint 10a of the mounting substrate 9 via the solder bumps 8, and the other conductive plate 3a.
b is electrically connected to the footprint 10b for power supply of the mounting substrate 9 via the solder bump 8.

According to the second embodiment, both the GND lead and the power supply lead, which have been conventionally provided on the side surface of the package body 2, are not required.
The number of 3 can be further increased, and the LSI package 1
It is possible to further promote the increase in the number of pins.

According to the second embodiment, the inductance of the wiring path from the GND pad 6a of the semiconductor chip 5 to the mounting board 9 and the inductance of the wiring path from the power supply pad 6b to the mounting board 9 are respectively set. Since the noise can be reduced, noise caused by the inductance of the wiring path can be further reduced.

[0033]

Third Embodiment As shown in FIG. 3, the LSI package 1 of the third embodiment has a GN of a semiconductor chip 5 via a wire 7.
Conductive plate 3 electrically connected to D pad 6a
a is directly connected to the GND footprint 10a of the mounting board 9, and the conductive plate 3b electrically connected to the power supply pad 6b of the semiconductor chip 5 via the wire 7 is used for the power supply of the mounting board 9. It is configured to be directly connected to the footprint 10b. Conductive plates 3a, 3b
And the footprints 10a and 10b are connected by solder 14
Done by.

Further, the LSI package 1 of the third embodiment
Is formed by molding the package main body 2 using a mold in which the upper mold is made smaller than the lower mold, so that the upper surfaces of the signal leads 13 protruding outward from the side surfaces of the package main body 2 are not covered by the package main body. It is exposed on the side of 2.

Further, the lead 13 is shortly cut in the vicinity of the side surface of the package body 2, and its tip end and the signal footprint 10 of the mounting substrate 9 are electrically connected via the wire 7.

According to the third embodiment, the conductive plates 3a,
Since 3b is directly connected to the footprints 10a and 10b, the inductance of the wiring path from the GND pad 6a of the semiconductor chip 5 to the mounting board 9 and the inductance of the wiring path from the power supply pad 6b to the mounting board 9 Can be further reduced, so that noise caused by the inductance of the wiring path can be further reduced.

According to the third embodiment, the conductive plates 3a,
By directly connecting 3b onto the footprints 10a and 10b, the heat dissipation of the LSI package 1 can be further improved.

According to the third embodiment, since the leads 13 and the signal footprints 10 are electrically connected by the wire bonding method, the LSI package 1 is mounted on the mounting substrate 9.
Even if the positioning accuracy is insufficient when mounting, the lead 13 and the signal footprint 10 can be reliably connected by using the wire bonding device with the recognition mechanism.

As a result, the LSI package 1 can be mounted on the mounting board 9 with high accuracy if the conductive plates 3a, 3b are aligned with the footprints 10a, 10b with high accuracy. It has the advantage that no on-board equipment is required.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

[0041]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

(1) According to the present invention, the power supply lead and the GND lead, which are conventionally provided on the side surface of the package body, are unnecessary, and the number of signal leads can be increased accordingly. It is possible to promote the increase in the number of pins of the LSI package.

(2) According to the present invention, the inductance of the wiring path from the power supply pad of the semiconductor chip or the pad for GND to the mounting substrate can be reduced, so that the noise caused by this inductance is reduced. be able to.

(3) According to the present invention, the heat of the semiconductor chip can be released to the outside through the conductive plate provided on the bottom surface of the package body, so that the heat dissipation of the LSI package can be improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing an LSI package that is an embodiment of the present invention.

FIG. 2 is a sectional view showing an LSI package which is another embodiment of the present invention.

FIG. 3 is a cross-sectional view showing an LSI package which is another embodiment of the present invention.

[Explanation of symbols]

 1 LSI Package 2 Package Main Body 3 Conductive Plate 3a Conductive Plate 3b Conductive Plate 4 Adhesive 5 Semiconductor Chip 6 Pad (for Signal) 6a Pad (for GND) 6b Pad (for Power Supply) 7 Wire 8 Solder Bump 9 Mounting Board 10 Footprint (For signal) 10a Footprint (for GND) 10b Footprint (for power supply) 11 Solder resist 12 Insulating film 13 Lead (for signal) 13b Lead (for power supply) 14 Solder

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location H01L 23/50 X 9272-4M Y 9272-4M R 9272-4M // H05K 1/18 H 9154- 4E (72) Inventor Minoru Kubozono 2326 Imai, Ome, Tokyo Metropolitan area, Hitachi Device Development Center (72) Inventor Hiroshi Kuroda 2326, Imai, Ome city, Tokyo Metropolitan area Device Development Center, Hitachi (72) Inventor Hiroyuki Shirai 2326 Imai, Hitachi, Ltd., Ome-shi, Tokyo (72) Inventor, Toshihiro Matsunaga Toshihiro Matsunaga 2326 Imai, Ome, Tokyo, Tokyo (72) Device, Development Center, Hitachi, Ltd. (72) Toshihiro Tsuboi, Kodaira, Tokyo 5-20-1 Jousui, Honcho, Ichi-Hitate Cho-LS Engineering Co., Ltd. (72) Inventor Hiroshi Kosaku 5-201-1, Josuihonmachi, Kodaira-shi, Tokyo Hirate RLS AI Engineering Co., Ltd. (72) Inventor Masayuki Kikuchi 5 Sanmizuhoncho, Kodaira-shi, Tokyo Chome No. 20-1 Hitate Super LSI Engineering Co., Ltd.

Claims (5)

[Claims] 1. A power supply pad or G for the semiconductor chip on the bottom surface of an LSI package encapsulating the semiconductor chip.
A semiconductor integrated circuit characterized in that a conductive plate electrically connected to a pad for ND is provided, and the pad for power supply or the pad for GND is electrically connected to a mounting substrate via the conductive plate. apparatus. 2. The semiconductor integrated circuit device according to claim 1, wherein a semiconductor chip is mounted on the upper surface of the conductive plate, and signal leads are bonded to the peripheral portion of the conductive plate via an insulating film. . 3. The semiconductor integrated circuit according to claim 1, wherein a solder bump is joined to the lower surface of the conductive plate, and the conductive plate and the mounting substrate are electrically connected via the solder bump. apparatus. 4. A conductive plate is divided into two or more parts, and one of them is electrically connected to a power supply pad, and
4. The semiconductor integrated circuit device according to claim 1, 2 or 3, wherein the other side and a pad for GND are electrically connected. 5. The semiconductor integrated circuit according to claim 1, wherein the signal lead protruding from the side surface of the package body and the mounting substrate are electrically connected via a bonding wire. apparatus.