JPH0697443A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the shift of a threshold and the drop of the mobility by forming an intrinsic semiconductor layer, in contact with the two stacked section of a p-type semiconductor layer and an n-type semiconductor layer, and besides, covering all the surface of the semiconductor layer made on a transparent substrate with an oxide silicon film, and then, heat-treating it. CONSTITUTION:A resist 13 is removed, and an oxide film to serve as a gate insulating film 15 is made to cover all the surface of an intrinsic semiconductor film 12 including the p-type semiconductor layer 11 and the n-type semiconductor layer 14 made on a substrate 2. Next, the residual section of the intrinsic semiconductor layer 12 becomes a polycrystalline semiconductor layer 16 being a channel region by performing the heat treatment for performing the activation of the n-type semiconductor layer 14 and the solid-phase growth of the residual part of the intrinsic semiconductor film 12, and then, patterning it. phosphorus or boron being the impurities of the n-type semiconductor layer or the p-type semiconductor layer do not diffuse into hot atmosphere during heat treatment by doing it this way, whereby the danger of such impurities mixing and diffusing into the channel region can be prevented.

Description

Detailed Description of the Invention

[0001]

[Industrial field of application] It has the electrical characteristics that one element can perform the same operation as a complementary field effect transistor.
There is a semiconductor device that is commonly called a “modified stacked gate semiconductor device”. When this semiconductor device is used in a liquid crystal display device or the like, clear gradation display can be obtained,
It is possible to obtain a display close to a natural image. The present invention presents a new fabrication method for improving the performance of the semiconductor device.

[0002]

2. Description of the Related Art "Modified stacked gate semiconductor device"
As has been known in "SID'91", its characteristic is that bidirectional current-voltage characteristics can be provided between the source and drain by changing the potential of the signal applied to the two gate electrodes. It is a device. The current-voltage characteristics are shown in FIG.

A device having such characteristics can be used for various purposes, but it is considered to be particularly effective when applied to a liquid crystal electro-optical device. Conventionally, the semiconductor device used in the liquid crystal electro-optical device is mainly an n-channel thin film transistor as shown in the circuit configuration of FIG. When an n-channel thin film transistor or a p-channel thin film transistor is used here, the forward characteristics of the n-channel thin film transistor can be used when the state changes from the OFF state to the ON state (direction in which the charge accumulated in the pixel electrode increases). , High-speed operation is possible. However,
At the time of transition from the ON state to the OFF state (direction in which the charge accumulated in the pixel electrode decreases), the operation is hindered because the characteristics are opposite to those of the n-channel thin film transistor.

Therefore, by using an n-channel type thin film transistor and a p-channel type thin film transistor in a complementary type, such as a "transfer gate type C / MOS thin film transistor" shown in FIG.
It is well known that high-speed operations can be performed even in both F, OFF to ON operations due to the fast movement of electric charges, and it is expected to be applied to a liquid crystal electro-optical device. .

As described above, there are many merits when the C / MOS device is used in a liquid crystal electro-optical device.
In consideration of an actual device, installing both an n-channel thin film transistor and a p-channel thin film transistor as an element in each pixel means providing twice as many elements as in the case of using a conventional n-channel thin film transistor alone. Therefore, when considering the improvement of yield, the idea was to improve the image quality, but it was against the idea of commercialization. Specifically, when considering a liquid crystal electro-optical device having pixels of 640 × 400 dots, the yield which is currently about 50% per panel is 25% even if simply calculated by doubling the elements. The following is inevitable. It goes without saying that as the number of masks increases, the factors that further reduce the yield are added up.

Further, not only the problem of yield, but also the problem of aperture ratio, which is an important factor in liquid crystal electro-optical devices. The aperture ratio reduced by providing one element is about 5
It is generally said to be about%, but it is 2 like C / MOS.
It is needless to say that when one element is produced, it is reduced by 10% or more. Therefore, an element that can perform the same operation even if the number of elements is reduced has been desired.

Therefore, the above-mentioned "modified stacked gate type semiconductor device" has been proposed as an element capable of compensating for these drawbacks.

The manufacturing method of the present element, which is seen in the publicly known example, includes steps as shown in FIG.

First, a p-type semiconductor film and an n-type semiconductor film are laminated on a transparent substrate 1 made of glass or the like by plasma CVD or low pressure CVD, and an island is formed by a mask as shown in FIG. 5 (A). Patterning to obtain a p-type semiconductor layer 2 and an n-type semiconductor layer 3. After that, an intrinsic semiconductor film is deposited, patterned using the following mask, and then solid phase growth is performed in a nitrogen atmosphere at 600 ° C. to crystallize from an amorphous phase to form a polycrystalline intrinsic semiconductor serving as a channel region. Layer 4
Then, FIG. 5B is obtained. After that, a SiO ₂ film serving as a gate insulating film is formed to 100 by using low pressure CVD or sputtering.
A phosphorus-doped Si layer to be a main gate electrode is deposited to 2000 Å by a low pressure CVD method or the like, and patterned by using the following mask to form a gate insulating film 5 and a main gate electrode 6 to obtain FIG. 5C. After that, low pressure CVD
Alternatively, the SiO ₂ film which is the interlayer insulating film 7 is deposited by 5000 Å using plasma CVD method or the like, and then Al is deposited by 3000 Å, and patterned by using the following mask to obtain the sub-gate electrode 8 as shown in FIG. 5 (E). , Is the method.

[0010]

In the case of using the above process, if solid phase growth is performed after patterning as shown in FIG. 5B, the p-type semiconductor layer or the n-type semiconductor layer is formed in a high temperature atmosphere. There is a risk that phosphorus or boron, which is an impurity, diffuses and mixes and diffuses into the intrinsic semiconductor layer 4 that serves as a channel region. In such a case, a high-performance channel cannot be formed, the OFF resistance required for the drive element for the liquid crystal electro-optical device cannot be sufficiently increased, and the field effect mobility is extremely lowered. . Also,
The interlayer insulating film 7 shown in FIG. 5D is thick in order to prevent short-circuiting of the three-dimensional cross wiring, so that a sufficient electric field cannot be applied unless the voltage applied to the sub-gate is increased.

[0011]

[Means for Solving the Problems] Therefore, the present inventors have attempted to solve the above problems by taking the following steps.
That is, after forming two stacked parts in which a p-type semiconductor layer and an n-type semiconductor layer are stacked and an intrinsic semiconductor layer provided in contact with the two stacked parts on a transparent substrate, a gate insulating film is formed. A layer, for example, a silicon oxide film is formed so as to cover the entire surface of the semiconductor layer on the transparent substrate, and then thermal annealing is performed to solid-phase grow the intrinsic semiconductor layer for polycrystallization. By doing so, phosphorus or boron, which is an impurity of the n-type semiconductor layer or the p-type semiconductor layer, does not diffuse into the high temperature atmosphere during the heat treatment, and the risk that such an impurity mixes into the channel region and diffuses is prevented. It is possible to prevent the shift of the threshold value and the decrease of the mobility.

After that, a gate insulating film is formed and patterned, a first gate electrode is formed of aluminum on the gate insulating film, and anodization is performed to insulate the surface of the first gate electrode, and then the second gate electrode is formed. A gate electrode is formed on the gate insulating film adjacent to the first gate electrode.

Through the above steps, it is possible to prevent impurities from being mixed during solid phase growth of the intrinsic semiconductor layer.
By forming the two gate electrodes on the same gate insulating film, the voltage applied to the second gate electrode can be reduced.

The following manufacturing method was devised as an application example of the above process.

First, as shown in FIG. 1A, the transparent substrate 1
A patterned p-type semiconductor layer 11 is formed on the substrate 0 using a mask. Then, the intrinsic semiconductor film 12 is formed,
A negative resist is applied thereon, and ultraviolet light is applied from the back surface of the substrate to expose and develop the resist 13 in a portion not having the p-type semiconductor layer 11 as a base as shown in FIG.

Next, as shown in FIG. 1C, p of the intrinsic semiconductor film 12 is formed using the resist 13 as a mask.
Ions of a Group 5 element such as phosphorus are implanted to form an n-type semiconductor layer 14 on the type semiconductor layer 11 to form an n-type semiconductor layer 14.

Next, the resist 13 is removed, and an oxide film to be the gate insulating film 15 is formed on the substrate to form the p-type semiconductor layer 1.
1 and the n-type semiconductor layer 14 are formed so as to cover the entire surface of the intrinsic semiconductor film 12, and then the n-type semiconductor layer 14 is activated and the remaining portion of the intrinsic semiconductor film 12 is solid-phase grown. By performing heat treatment for this purpose and then patterning, the remaining portion of the intrinsic semiconductor film 12 becomes a polycrystalline semiconductor layer 16 which is a channel region, as shown in FIG. By doing so, phosphorus or boron, which is an impurity of the n-type semiconductor layer or the p-type semiconductor layer, does not diffuse into the high temperature atmosphere during the heat treatment, and the risk that such an impurity mixes into the channel region and diffuses is prevented. It is possible to prevent the shift of the threshold value and the decrease of the mobility.

In FIG. 1 (E), the first gate electrode, that is, the main gate electrode 17 is formed of aluminum, and then the surface thereof is anodized to form an oxide layer 18 to insulate the electrode surface. To obtain a non-porous aluminum oxide film, we used a solution of pH 7.0 ± 0.5 diluted with tartaric acid in ethylene glycol or propylene glycol. After that, the source electrode 19 and the drain electrode 20
To form. Also, if possible depending on the electrode material, the source electrode 19 and the drain electrode 2 at the same time as the main gate electrode 17.
It is effective to form 0 and subject the surface thereof to anodization similarly to the main gate electrode.

Then, as shown in FIG. 1F, a second gate electrode, that is, a sub-gate electrode 21 is formed of aluminum. After that, the interlayer insulating film 22 is formed.

By providing the oxide film 18 directly on the surface of the main gate electrode 17 by the anodic oxidation method, the main gate electrode 17 and the sub-gate electrode 21 can be formed on the same gate insulating film 15. Therefore, not only was the threshold value reduced, but also the interface state density could be reduced.

Further detailed description will be given below with reference to examples.

[0022]

EXAMPLE In this example, a viewfinder for a video camera using a liquid crystal electro-optical device having a diagonal of 1 inch was manufactured and the present invention was carried out.

In this embodiment, a viewfinder is constructed by forming a device having a high mobility modified stacked gate device by a low temperature process with a structure of 387 × 128 pixels. FIG. 6 shows the arrangement of the active elements on the substrate of the liquid crystal display device used in this embodiment.
The fabrication process showing the -A 'cross section is depicted in FIG.

In FIG. 7A, an inexpensive glass substrate 3 that can withstand heat treatment at 700 ° C. or lower, for example, about 600 ° C.
An amorphous silicon oxide film as the blocking layer 31 is formed on the surface of the substrate 0 to a thickness of 1000 to 3000 Å by using a magnetron RF (radio frequency) sputtering method. Process conditions are 100% oxygen atmosphere, film forming temperature 150 ° C., output 400.
˜800 W and pressure 0.5 Pa. The deposition rate using quartz or single crystal silicon for the target is 30 to 100
It was Å / min.

A p-type Si (silicon) film is formed on this by LPC.
VD (vacuum vapor phase) method, sputtering method or plasma CVD
It was formed to a thickness of 1000 to 3000 Å, here 2000 Å. When forming by a low pressure vapor phase method, disilane (Si ₂ H ₆ ) or trisilane (Si ₂ H ₆ ) is added at 450 to 550 ° C., which is 100 to 200 ° C. lower than the crystallization temperature, for example, 530 ° C.
₃ H ₈ ) was supplied to the CVD device to form a film. Diborane (B ₂ H ₆ ) as an impurity source gas is added to the host gas in an amount of 0.5 to
3% mixed. The pressure in the reaction furnace was 30 to 300 Pa. The film forming rate was 50 to 250 Å / min.

In the case of the sputtering method, the back pressure before sputtering was set to 1 × 10 ^-5 Pa or less, the p-type single crystal silicon was used as the target, and the atmosphere was mixed with 20% to 80% of hydrogen in argon. For example, argon is 20% and hydrogen is 80%. The film forming temperature is 150 ° C., the frequency is 13.56 MHz,
The sputter output was 400 to 800 W and the pressure was 0.5 Pa.

When a silicon film is formed by the plasma CVD method, the temperature is, for example, 300 ° C., and monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used. Diborane (B ₂ H ₆ ) as an impurity source gas was mixed with the host gas in an amount of 0.5 to 3%. Introducing these into the PCVD equipment, 13.56M
A high frequency power of Hz was applied to form a film.

After patterning the p-type Si film into an island shape to form a p ⁺ Si layer 32 which is a p-type semiconductor layer,
An intrinsic Si film 33 is formed on top of this by LP as shown in FIG.
CVD (Low Pressure Vapor Phase) method, Sputtering method or Plasma CV
1000-3000Å by method D, here 2000Å
Formed to a thickness of. When forming by a reduced pressure vapor phase method, disilane (Si ₂ H ₆ ) or trisilane (Si ₃ ) is added at 450 to 550 ° C., which is lower than the crystallization temperature by 100 to 200 ° C., for example, at 530 ° C.
H ₈ ) was supplied to the CVD device to form a film. The pressure in the reaction furnace was 30 to 300 Pa. Deposition rate is 50 ~ 250Å /
It was a minute. In order to arbitrarily control the threshold voltage (Vth), boron is used in an amount of 1 × 10 ¹⁵ to 1 by using diborane.
It may be added as a concentration of × 10 ¹⁸ cm ^-3 during film formation.

When the sputtering method is used, the back pressure before the sputtering is set to 1 × 10 ^-5 Pa or less, the single crystal silicon is used as the target, and the atmosphere is mixed with hydrogen of 20 to 80% in argon. For example, argon is 20% and hydrogen is 80%.
The film forming temperature was 150 ° C., the frequency was 13.56 MHz, the sputter output was 400 to 800 W, and the pressure was 0.5 Pa.

When the silicon film is formed by the plasma CVD method, the temperature is, for example, 300 ° C., and monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used. These were introduced into a PCVD apparatus, and high-frequency power of 13.56 MHz was applied to form a film.

The coatings formed by these methods are
It is preferable that oxygen is 5 × 10 ²¹ cm ⁻³ or less. If this oxygen concentration is high, it is difficult to crystallize and the thermal annealing temperature must be high or the thermal annealing time must be long.
If it is too small, the backlight will turn off the light.
The current will increase. Therefore 4 × 10 ¹⁹ to 4 × 10 ²¹
The range was cm ^-3 . Hydrogen is 4 × 10 ²⁰ cm ^-3 and silicon 4
When compared with ^{x10 22} cm ^-3 , it was 1 atom%.

After that, a negative resist is applied on the surface,
When ultraviolet rays are radiated from the back surface of the substrate, the portions having the p-type semiconductor layer do not transmit the ultraviolet rays, so that they are not cured and removed at the stage of development, and the resist 34 remains. In this way
The mask used for the next step of ion implantation can be manufactured in the self-aligning step.

In FIG. 7C, phosphorus (P) is added to the intrinsic Si film 33 on the p ⁺ Si layer 32 at 1 to 5 × 10 ¹⁵ cm ^-2.
By adding by the ion implantation method with a dose amount of
An n ⁺ Si layer was formed.

Next, the resist 34 was removed, and a silicon oxide film was formed to a thickness of 500 to 2000Å, for example 1000Å. This is the same condition as the production of the silicon oxide film as the blocking layer 31. Add a small amount of fluorine during this film formation,
You may fix sodium ion.

After forming the silicon oxide film, 450 to 700
The temperature was kept at a temperature of 600C for 12 to 70 hours at a temperature of 600C in a non-oxide atmosphere at a medium temperature, for example, in a hydrogen atmosphere. Since a silicon oxide film having an amorphous structure is formed as the blocking layer 31 on the surface of the substrate under the intrinsic Si film 33, no specific nucleus exists in this heat treatment, and the whole is uniformly annealed by heating. That is, it has an amorphous structure at the time of film formation, and hydrogen is simply mixed therein.

Due to the annealing, the intrinsic Si film 33 shifts from the amorphous structure to a highly ordered state, and a part thereof assumes a crystalline state. In particular, a region having a relatively high degree of ordering after the film formation of silicon tends to be crystallized and become a crystalline state. However, since silicon existing between these regions is bonded to each other, the silicon members pull each other.
The peak of single-crystal silicon measured by laser Raman spectroscopy
A peak shifted to a lower frequency side than 522 cm ^-1 is observed. When the apparent particle size of it is calculated from the half width,
Although it is a microcrystal with a thickness of 50 to 500Å, in reality there are many highly crystalline regions with a cluster structure, and each cluster is a semi-amorphous structure in which silicon is bonded to each other (anchoring). Was able to be formed.

As a result, the coating is in a state in which it may be said that there is substantially no grain boundary (hereinafter referred to as GB). Since the carriers can easily move between the clusters through the anchored portions, the carrier mobility is higher than that of polycrystalline silicon in which so-called GB is clearly present. That is, hole mobility (μh) = 10 to ²⁰⁰ cm ² /
VSec, electron mobility (μe) = 15 to 300 cm ² / V
Sec is obtained.

On the other hand, the coating may be polycrystallized by a high temperature anneal of 900 to 1200 ° C. instead of the medium temperature anneal as described above. However, in such a case, the solid phase growth from the nuclei causes the segregation of impurities in the coating film, resulting in G
Although B has a large amount of impurities such as oxygen, carbon, and nitrogen, and has a high mobility in the crystal, it creates a barrier in GB and hinders the movement of carriers there. As a result, it is difficult to obtain a mobility of 10 cm ² / Vsec or more.

In this way, the polycrystalline intrinsic Si layer 37 was formed. This step also serves to activate the n ⁺ Si layer 35. After that, the silicon oxide film is patterned to form a gate insulating film 36, and FIG. 7D is obtained.

Then, in order to form the main gate electrode 38, the source electrode 40, the drain electrode 41 and the lead,
2 aluminum by sputtering or vapor deposition
A film having a thickness of μm was formed and patterned.

After that, phosphoric acid was diluted with ethylene glycol to obtain a solution having a pH of 5.0 ± 0.5, and the substrate was dipped therein. + To the lead extending from the main gate electrode 38, the source electrode 40, the drain electrode 41 and the respective electrodes,
A voltage of 25 V was applied to form a porous aluminum oxide film of about 1 μm. After thorough washing, tartaric acid was diluted with ethylene glycol to make a solution having a pH of 7.0 ± 0.5, and the substrate was immersed in the solution. Main gate electrode 3
A voltage of +75 V was supplied to 8, the source electrode 40, the drain electrode 41, and the leads extending from the respective electrodes. After about 30 minutes, the surface of the porous aluminum oxide can be transformed into a non-porous aluminum oxide film, and the non-porous aluminum oxide film can be formed on the main gate electrode 38, the source electrode 40, the drain electrode 41 and the lead. Aluminum oxide films 39 and 42 of 1 μm were obtained, and FIG. 7E was obtained.

Thereafter, as the sub-gate electrode 43 and the lead, an aluminum film having a thickness of 2 μm was formed by sputtering or vapor deposition and patterned.

An interlayer insulating film 44 of SiN _x film having a thickness of 2 μm is formed on this substrate by using the plasma CVD method, and after patterning holes, ITO (indium tin oxide film) which is a transparent conductive film is formed. Was deposited by a 1000Å sputtering method and then patterned to form a pixel electrode 45, to obtain FIG. 7 (F). Thus, the first substrate was obtained.

Next, as the second substrate, a color filter was formed on a substrate in which a silicon oxide film was laminated in 2000 liters on a soda lime glass by a sputtering method, and ITO was formed thereon by a sputtering method. This ITO is room temperature to 150
A film was formed at a temperature of ℃, and the second substrate was obtained by achieving oxygen at 200 to 400 ℃ or annealing in the air.

A polyimide precursor was printed on the first and second substrates by an offset method and baked at 350 ° C. for 1 hour in a non-oxidizing atmosphere such as nitrogen. After that, a known rubbing method was used to modify the surface of the polyimide, and at least in the initial stage, a means for orienting liquid crystal molecules in a certain direction was provided to obtain first and second substrates.

After that, the nematic liquid crystal composition was sandwiched between the first substrate and the second substrate, and the periphery was fixed with an epoxy adhesive. Since the pitch of the leads on the substrate was as fine as 46 μm, the COG method was used for connection. In this embodiment, the gold bumps provided on the IC chip are connected by an epoxy-based silver-palladium resin, and the IC chip and the substrate are embedded and fixed by epoxy modified acrylic resin for the purpose of fixing and sealing. I was there. After that, a polarizing plate was attached to the outside to obtain a transmissive liquid crystal display device.

[0047]

[Effects of the Invention] After forming two stacked parts in which a p-type semiconductor layer and an n-type semiconductor layer are stacked on a transparent substrate and an intrinsic semiconductor layer provided in contact with the two stacked parts, the transparent film is formed. An n-type semiconductor is formed during heat treatment by forming an insulating film so as to cover the entire surface of the semiconductor layer formed on the optical substrate and performing thermal annealing to solid-phase grow the intrinsic semiconductor layer to polycrystallize it. Phosphorus or boron, which is an impurity of the p-type semiconductor layer or the p-type semiconductor layer, does not diffuse into a high temperature atmosphere, and it is possible to prevent such impurities from being mixed in and diffused into the channel region, which may cause a shift in threshold and a decrease in mobility. I was able to prevent it.

Further, the first gate electrode is formed of aluminum on the insulating film, and the electrode surface is insulated by performing anodization, and then the second gate electrode is adjacent to the first gate electrode. The voltage applied to the second gate electrode can be reduced by forming it on the gate insulating film, that is, by forming the two gate electrodes on the same gate insulating film. This also made it possible to reduce the interface rank density.

As described above, the present invention is considered to greatly contribute to industrial development.

[Brief description of drawings]

FIG. 1 shows a structure of a modified stacked gate semiconductor device according to the present invention and a manufacturing process thereof.

FIG. 2 is a current-voltage characteristic of a modified stacked gate semiconductor device.

FIG. 3 is a circuit configuration of a liquid crystal electro-optical device using an n-channel thin film transistor.

FIG. 4 is a circuit configuration of a liquid crystal electro-optical device using a transfer gate type C / MOS thin film transistor.

FIG. 5 is a structure of a modified stacked gate type semiconductor device in a known example and its manufacturing process.

FIG. 6 is a layout of active elements on a substrate according to an embodiment.

7A and 7B are a structure of a modified stacked gate semiconductor device and a manufacturing process thereof in an example.

[Explanation of symbols]

1,10 Translucent Substrate 2,11 p-type Semiconductor Layer 3,14 n-type Semiconductor Layer 4,16 Polycrystalline Intrinsic Semiconductor Layer 5,15,36 Gate Insulating Film 6,17,38 Main Gate Electrode 7,22,44 Interlayer insulating film 8, 21, 43 Sub-gate electrode 12 Intrinsic semiconductor film 13, 34 Resist 18 Oxide layer 19, 40 Source electrode 20, 41 Drain electrode 30 Glass substrate 31 Blocking layer 32 p ⁺ Si layer 33 Intrinsic Si layer 35 n ⁺ Si Layer 37 Polycrystalline intrinsic Si layer 39, 42 Aluminum oxide layer 45 Pixel electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI technical display location 9056-4M H01L 29/78 311 Y (72) Inventor Yasuhiko Takemura 398 Hase, Atsugi, Kanagawa Co., Ltd. Semiconductor Energy Laboratory

Claims (4)

[Claims] 1. A transparent substrate, a p-type semiconductor layer and an n-type semiconductor layer are laminated on a translucent substrate, and an intrinsic semiconductor layer provided in contact with the two laminated parts is formed. A method for manufacturing a semiconductor device, comprising forming an insulating film so as to cover the entire surface of a semiconductor layer formed over an optical substrate and then performing heat treatment. 2. When manufacturing an insulated gate semiconductor device having two gate electrodes, the first gate electrode is formed of aluminum, and then the surface of the first gate electrode is anodized to form the first gate electrode. A method for manufacturing a semiconductor device, comprising insulating the surface of one gate electrode and then forming a second gate electrode adjacent to the first gate electrode. 3. When manufacturing an insulated gate semiconductor device having two gate electrodes, a gate insulating film is formed, a first gate electrode is formed of aluminum on the gate insulating film, and then the first gate electrode is formed. The surface of the gate electrode is anodized to insulate the surface of the first gate electrode, and then a second gate electrode is formed adjacent to the first gate electrode on the gate insulating film. And a method for manufacturing a semiconductor device. 4. An intrinsic semiconductor layer is formed after forming a patterned p-type semiconductor layer on a light-transmissive substrate, a negative resist is applied, and then ultraviolet light is applied from the back surface of the substrate to form a base on the p-type semiconductor layer. Exposing and developing a portion of the resist not included in the above, implanting ions for making the intrinsic semiconductor layer into an n-type semiconductor using the resist as a mask, the p-type semiconductor layer, the intrinsic semiconductor layer, and the A step of performing a heat treatment for activating the n-type semiconductor layer and performing solid phase growth of the intrinsic semiconductor portion after covering the insulating film so as to cover the entire surface of the n-type portion of the intrinsic semiconductor layer; A method for manufacturing a semiconductor device, which comprises at least a step of forming a first gate electrode from aluminum and then anodizing its surface, and a step of forming a second gate electrode from aluminum.