JPH0697807A - Wired or logic circuit - Google Patents

Abstract

PURPOSE:To provide a wired OR logic circuit which can output the output signal of the logic circuits constructing a wired OR logic circuit to the outside at the same level without receiving the influences of the resistances distributed on a signal line reaching up to an output terminal. CONSTITUTION:The logic circuits L1-Ln are provided with the output bipolar transistors T1-Tn and the constant current sources 41-4n which construct an emitter follower circuit. The sources 41-4n are turned on and off synchronously with the output control signals E1-En. Then only the constant current source of a selected logic circuit supplies the current to the transistors T1-Tn. This current flows to a low level power line 5 from a ground line through the transistors T1-Tn and the sources 41-4n and does not flow to a wiring 2 led to an output terminal 3. Therefore the outputs of the circuits L1-Ln are never affected by the voltage drop caused by the distributed resistances r1-rn-1 and outputted to the outside through the terminal 3 at the same potential.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wired OR logic circuit, and more particularly to a wired OR logic circuit including a plurality of logic circuits for outputting an output logic signal through a signal output bipolar transistor of an emitter follower.

[0002]

2. Description of the Related Art FIG. 5 shows an example of the configuration of a conventional wired OR logic circuit of this type. Referring to FIG. 5, the wired OR logic circuit includes output selection signals E _{1 to} E _1.
n logic circuits L ₁ selected by _n (n is an integer)
There is ~L _n. The emitter of their internal signal output transistor T ₁ through T _n is the output terminal of each logic circuit, the output Q ₁ to Q _n is the wiring resistance or the distribution resistance r ₁ ~r _n-1 outputted therefrom Is output to the common output terminal 3 via the same wiring 2 having The wiring 2 is further connected to a low potential power supply line 5 having the lowest potential through a constant current source 4 common to the logic circuits L _{1 to} L _n .

The operation of this wired OR logic circuit will be described below. First, the output Q _m of the selected logic circuit L _{m with} m number (m is an integer of 1 ≦ m ≦ n) is in a high level (V _H ) or low level ( _VL ) state. The outputs of the other non-selection circuits are fixed to V _L. Since the output of each logic circuit is connected using the wired OR logic, a high level signal or a low level signal is output to the output terminal 3 according to the output Q _m of the logic circuit L _m .

Now, when the nth logic circuit L _n is selected and the other logic circuits are not selected, the voltage value V _OUT of the output terminal 3 is the distributed resistances r _{1 to} r _{n-1 of the} wiring 2. Therefore, the potential of the output Q _n of the logic circuit L _n is almost equal to that of V _OUT = V _H or V _OUT = V _L.

Next, the first terminal farthest from the output terminal 3
Logic circuit L₁Is selected and the other logic circuit L₂~ L_n
If is not selected, the voltage value V of the output terminal 3_OUTThis
The current path at₁From the collector
Distributed resistance r of wiring 2 through the emitter₁, R₂, ..., r
_n-1And then flows from the constant current source 4 to the low-level power supply line 5
Since it is a pass, a voltage drop occurs and the logic circuit L_nof
Depending on the output state, V _OUT= V_H-(R₁+ R₂+ ... +
r_n-1) ・ I or V_OUT= V_L-(R₁+ R₂+ ...
+ R_n-1) ・ I (however, I is the current of the constant current source 4)
value).

In general, when the m-th logic circuit L _m is selected by the output selection signal E _m , the logic signal input to the base of the output transistor T _m inside this logic circuit L _m is output by the logic circuit L _m . When a signal is output from the emitter of the transistor T _m via the output terminal 3, the voltage value V _{OUT at the} output terminal 3 is such that the current is the transistor T _m.
From the collector to the emitter of the wiring 2 and distributed resistances r _m , r _{m + 1} , ..., R _n-1 , r _n (however, for simplicity, r
_n = 0), the current flows from the constant current source 4 to the lowest voltage low-potential power line 5, so that V _OUT = V _H − (r _m + r _{m + 1)} depending on the output state of the logic circuit L _m. + ... + r _n-1 + r
_n ) · I or V _OUT = V _L − (r _m + r _{m + 1} + ... +
r _n-1 + r _n ) · I.

[0007]

In this conventional wired OR logic circuit, a large number of logic circuits share the same signal wiring 2 having a distributed resistance on the line and a single constant current source 4, and each logic circuit L Outputs from _{1 to} L _n Q _{1 to} Q
_n is switched by the output selection signals E _{1 to} E _n . Therefore, the output Q _{1 of the} logic circuits L _{1 to} L _n itself
Even _if signals from Qn to Qn are at the same level, as shown in FIG.
The output signal level V _OUT from ₁ to the outside is a voltage drop due to the distributed resistance of the wiring 2, and is higher than the output signal level from the output Q _n of the logic circuit L _n closest to the constant current source 4 to the outside. , And the voltage effect (r ₁ + r ₂ + ... + r _n-1 ) · I drops. For this reason, in some cases, the minimum signal level required in the next stage may not be obtained by the conventional wired OR logic circuit.

The present invention has been made in view of the above points, and the output signal level from each logic circuit constituting the wired-OR logic circuit to the outside may be related to the difference in the wiring length to the output terminal. First, it is an object of the present invention to provide a wired OR logic circuit which can be obtained at the same level and has a wide operation margin.

[0009]

The wired OR logic circuit of the present invention is a wired OR circuit in which a plurality of logic circuits for outputting an output logic circuit via a bipolar transistor for signal output are connected by a wired OR circuit. Each of the logic circuits has a constant current source that turns on and off in synchronization with the state of the output selection signal for each output bipolar transistor and forms an emitter follower circuit together with the output bipolar transistor. Further, each of the logic circuits includes a circuit for setting the output signal level when not selected to be lower than the low level of the output signal when selected.

[0010]

Next, preferred embodiments of the present invention will be described. FIG. 1 is a block diagram showing the configuration of the first exemplary embodiment of the present invention. Referring to FIG. 1, the present embodiment is different from the conventional wired OR logic circuit shown in FIG. 5 in that instead of the constant current source 4 which is common to all the logic circuits L _{1 to} L _n in the related art, a logic circuit is used. The constant current sources 4 ₁ to 4 _n are provided between the emitters of the output bipolar transistors T _{1 to} T _n and the low-potential power line 5 for each of the L _{1 to} L _n . Each of these constant current sources 4 ₁ to 4 _n is turned on in response to the state of the output select signal E ₁ to E _n, are turned off. Constant current sources 4 ₁ to 4 _n and output bipolar transistor T ₁
Through T _n respectively, to form an emitter follower circuit of each logic circuit L ₁ ~L _n.

The operation of this embodiment will be described below.
In Figure 1, for example, the output selection signal E ₁ is selected, when the output select signal E ₂ to E _n the other was a non-selected logic circuit L ₁ of is selected simultaneously with the constant current source 4 ₁
Turns on and a constant current I ₁ flows. On the other hand, the constant current source 4 ₂ to 4 _n logic circuits L in ₂ ~L _n in a non-selected state
Turns off and no current flows. In general, when the output select signal E _m (m is an integer of 1 ≦ m ≦ n) is selected, the constant current source 4 _m in the logic circuit L _m is turned on,
The other constant current sources are turned off and no current flows. At this time, the current I _m flows from the collector of the output bipolar transistor T _m , through the emitter, and through the constant current source 4 _m to the low-potential power line 5, so that no voltage drop occurs due to the distributed resistance of the wiring 2.

FIG. 2 is a circuit diagram in which the block diagram of FIG. 1 is drawn at a transistor level by taking an ECL type logic circuit as an example. In the present embodiment, when the output selection terminal 6 is at a high level with respect to the input reference voltage V _R , that is, in the non-selected state, the base voltage of the transistor N ₃ is higher than the reference voltage V _R , so the base voltage of the transistor N ₅ is The voltage becomes higher than the base voltage of the transistor N ₆ , the transistor N ₅ is turned on, and the transistor N ₆ is turned off. Therefore, no current flows between the emitter of the transistor T and the collector of the transistor N ₆ , which is equivalent to a state in which the constant current source is off. Further, in this non-selected state, the base voltage of the transistor N ₁ is higher than the base voltage of the transistor N ₂ to which the reference voltage V _R is input, so that the transistor N ₁ turns on and the current I _E1 causes the resistance R _E to flow.
_Flow to ₁ . At this time, the potential of the output ∇Q (where ∇ represents the inversion. Therefore, ∇Q represents the inversion of the output Q. The same applies hereinafter), and the potential between the base and the emitter of the transistor T is V.
If you _f, V ▽ _Q = - a _{(R 1 · I E1 + V} f) next to a low level.

Next, when the output selection terminal 6 is at the low level, that is, in the selected state, the emitter potential of the transistor N ₄ is higher than the emitter potential of the transistor N ₃ ,
Transistor N ₆ base potential becomes higher than the base potential of the transistor N _5, transistor N ₆ is turned on the transistor N ₅ is turned off. Therefore, the transistor T
The current I _E2 is applied to the emitter of and the collector of the transistor N _6.
Flows. Further, in this selected state, the base potential of the transistor N ₁ is lower than the base potential of the transistor N ₂ (reference voltage V _R ), so the path of the current I _E1 is the input D of the base voltage of the transistor N ₉ . Switch according to the value. That is, when a high level is input to the input D, the transistor N ₉ turns on, and at this time, the current I _E1
Flows from the ground line through the resistor R ₁ and from the collector to the emitter of the transistor N ₉ . Therefore, the base potential of the transistor T becomes − (R ₁ · IE ₁ ), the potential V ▽ _Q of the output ▽ _Q is low level, and − (R ₁ · IE ₁ + V
_f ). On the other hand, when the input D is low level, the current I _E1 flows from the ground line through the resistor R ₂ to the emitter of the transistor N ₂ . Therefore, since no current flows through the resistor R ₁ , the base potential of the transistor T becomes equal to the ground potential, the potential of the output ∇Q is at high level, and the potential of −V _f appears.

Next, a second embodiment of the present invention will be described. FIG. 3 is a circuit diagram depicting a logic circuit according to the second embodiment of the present invention at a transistor level. Referring to FIG. 3, this embodiment is different from the logic circuit in the first embodiment shown in FIG. 2 in that a resistor R ₇ is provided between the ground line and the collector of the transistor N _{1 in} series in addition to the resistor R _1. And the collector of the transistor N ₉ is connected to the connection point of both resistors. In this embodiment, as in the first embodiment, when the output selection terminal 6 is in the high level (non-selected) state, the transistor N ₅ is turned on and the transistor N ₆ is turned off. No current flows to the collector of N ₆ . At this time, when the transistor N ₁ is turned on, the current I _E1
Flows through the resistors R ₁ and R ₇ , the potential V ▽ _{Q of the} output ▽ _Q
Let V _f be the base-emitter potential of the transistor T, then V∇ _Q =-{(R ₁ + R ₇ ) · IE ₁ + V _f }. That is, as compared with the first embodiment where the resistance R ₇ is not inserted, - the potential of the amount corresponding to the output ▽ Q of (R ₇ · I _E1) decreases.

In the first embodiment, the output ▽ Q of the logic circuit in the non-selected state is fixed to the low level, and this is the same potential as the low level of the output ▽ Q of the logic circuit in the selected state.
As shown in FIG. 4A, a current path is generated in each logic circuit. This means that I _{E of the} transistor shown in FIG.
As can be seen from the −V _BE characteristic, the emitter current of the transistor is reduced and the potential difference between the base and the emitter is reduced. That is, the base-emitter voltage V _f of the transistor in FIGS. 2 and 3 decreases, and the low-level potential of the output ∇Q rises. On the other hand, in this embodiment, the potential V _LL of the output ▽ Q of the logic circuit in the non-selected state is made lower than the low-level potential _VL of the output ▽ Q of the logic circuit in the selected state by (-R ₇ · IE ₁ ). Therefore, no current flows in the emitter of the output transistor in the non-selected state, the low level of the output ∇Q of the logic circuit in the selected state becomes the output level of the entire circuit, and the operation margin can be further increased.

[0016]

As described above, according to the present invention, a constant current source forming an emitter follower circuit together with an output bipolar transistor is provided for each of a plurality of logic circuits forming a wired OR logic circuit. .
The constant current source is configured to flow a current only when the logic circuit to which it belongs is selected.

Thus, according to the present invention, when the output signals from the plurality of logic circuits are switched by the output selection signal and output on the same signal line, the required constant current source is selected according to the output selection signal. , Since the current can be passed only to the output emitter follower circuit of the selected logic circuit, it is not affected by the voltage drop due to the distributed resistance of the signal line from the logic circuit to the output terminal. The same output level can be output to the output terminal.

Furthermore, by providing a circuit for lowering the output signal level in the non-selected state than the low level of the output signal in the selected state for each logic circuit forming the wired OR logic circuit, the output signal of the selected logic circuit is The rise of the low level can be prevented and the operation margin can be widened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a circuit diagram showing the logic circuit in FIG. 1 at a transistor level.

FIG. 3 is a circuit diagram showing a transistor level of the logic circuit in the embodiment of FIG. 2 of the present invention.

FIG. 4 is a diagram for explaining the effect of the second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional wired OR logic circuit.

[Explanation of symbols]

L ₁ ~L _n logic circuit 2 wire 3 output terminals 4, 4 ₁ to 4 _n constant current sources 5 low potential power supply line 6 output selection terminal T, T ₁ ~T _n output bipolar transistor r ₁ ~r _n distributed resistance

Claims (5)

[Claims] 1. A wired-OR circuit in which a plurality of logic circuits that output an output logic signal via a signal output bipolar transistor are connected by wired OR, wherein each of the plurality of logic circuits is an output bipolar transistor. A wired-OR logic circuit having an emitter follower circuit and a constant current source that turns on and off in synchronization with the state of an output selection signal. 2. The wired OR logic circuit according to claim 1, wherein each of the plurality of logic circuits includes a circuit for setting an output signal level when not selected to be lower than a low level of the output signal when selected. Characterized wired-OR logic circuit. 3. The wired OR logic circuit according to claim 1 or 2, wherein the logic circuit is an ECL type logic circuit. 4. The wired OR logic circuit according to claim 1, wherein each of the logic circuits switches a current path according to a state of an input signal to the logic circuit and a state of the output selection signal, A wired OR logic circuit having a base potential setting circuit for applying different base potentials to the base of the output bipolar transistor. 5. The wired OR logic circuit according to claim 4, wherein the base potential setting circuit includes a circuit that lowers an output signal level when not selected than a low level of an output signal when selected. Wired-or logic circuit.