JPH069784U - Compound solder - Google Patents

Compound solder

Info

Publication number
JPH069784U
JPH069784U JP5121892U JP5121892U JPH069784U JP H069784 U JPH069784 U JP H069784U JP 5121892 U JP5121892 U JP 5121892U JP 5121892 U JP5121892 U JP 5121892U JP H069784 U JPH069784 U JP H069784U
Authority
JP
Japan
Prior art keywords
solder
spacer member
thickness
solder layer
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5121892U
Other languages
Japanese (ja)
Inventor
健一 栗原
勝也 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tanaka Denshi Kogyo KK
Original Assignee
Tanaka Denshi Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tanaka Denshi Kogyo KK filed Critical Tanaka Denshi Kogyo KK
Priority to JP5121892U priority Critical patent/JPH069784U/en
Publication of JPH069784U publication Critical patent/JPH069784U/en
Pending legal-status Critical Current

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  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】 【目的】半田を用いた電子部品用接続材料において、加
熱,溶融時においてその厚さ(高さ)を一定に保持でき
るようにして、温度変化による半導体チップの剥離や導
通不良が生じる虞れのない半導体装置の製造に極めて有
用な接続材料を提供する。 【構成】PbSn,PbAgSn等の半田材料を用いて、所定厚の
半田層1を形成する。半田層1中に、半田よりも高融点
の材質(Cu,Ni,Mo,W,セラミック,アルミナ,ガラ
ス,BN等)からなるスペーサ部材2を埋設する。スペー
サ部材2は上下面夫々に互いに平行な接線2a,2aを有す
る。半田溶融時に、上,下の接線2a,2aが、接続しよう
とする二部材に各々接することで、溶融時における半田
層1の厚さ(高さ)を一定に保持し、接続後における熱
サイクル強度の低下を防止する。
(57) [Abstract] [Purpose] In a connecting material for electronic parts using solder, the thickness (height) of the connecting material can be kept constant during heating and melting so that peeling and conduction of semiconductor chips due to temperature changes (EN) Provided is a connection material extremely useful for manufacturing a semiconductor device, which is free from the risk of defects. [Structure] A solder layer 1 having a predetermined thickness is formed using a solder material such as PbSn or PbAgSn. A spacer member 2 made of a material (Cu, Ni, Mo, W, ceramics, alumina, glass, BN, etc.) having a melting point higher than that of the solder is embedded in the solder layer 1. The spacer member 2 has tangent lines 2a, 2a parallel to each other on the upper and lower surfaces thereof. When the solder is melted, the upper and lower tangents 2a, 2a are in contact with the two members to be connected, respectively, so that the thickness (height) of the solder layer 1 during melting is kept constant, and the thermal cycle after the connection is completed. Prevents the strength from decreasing.

Description

【考案の詳細な説明】[Detailed description of the device]

【0001】[0001]

【産業上の利用分野】[Industrial applications]

本考案はパワートランジスタ等における電子部品の接続に使用される接続材料 、詳しくは、半導体チップの基板への固定等に用いる半田の改良に関する。 The present invention relates to a connecting material used for connecting electronic components in a power transistor and the like, and more particularly to improvement of solder used for fixing a semiconductor chip to a substrate.

【0002】[0002]

【従来の技術】[Prior art]

従来から、半導体チップを基板上に接続する際等に用いるものとして、半田を 0.1mm 厚程度のテープ状(若しくはリボン状),ペレット状等に成形した接続材 料が知られている。この接続材料Fは、チップ状に切断したものを基板C上に載 せ、その上に半導体チップBをセットした後に加熱,溶融させることで、半導体 チップBを基板C上に固着せしめるものである(図3参照)。 BACKGROUND ART Conventionally, as a material used for connecting a semiconductor chip to a substrate, a connecting material is known in which solder is molded into a tape (or ribbon) having a thickness of about 0.1 mm or a pellet. The connection material F is a material cut into chips and placed on the substrate C, and the semiconductor chip B is set on the connection material F and then heated and melted to fix the semiconductor chip B onto the substrate C. (See Figure 3).

【0003】[0003]

【考案が解決しようとする課題】[Problems to be solved by the device]

しかし乍ら、上記従来の接続材料Fは半田のみからなる単層構造であるため、 図3に示すように、溶融時にその形状が崩れて固化後の厚さ(高さ)が不均一に なることがあり、厚みの薄い部分では所定の熱サイクル強度が得られず、温度変 化による半導体チップBの剥離や導通不良を生じさせる虞れがあった。 However, since the conventional connecting material F has a single-layer structure composed of only solder, its shape collapses during melting and the thickness (height) after solidification becomes uneven as shown in FIG. In some cases, the predetermined thermal cycle strength cannot be obtained in the thin portion, and there is a possibility that peeling of the semiconductor chip B or conduction failure may occur due to temperature change.

【0004】 本考案はこのような従来事情に鑑みてなされたものであり、その目的とすると ころは、半田を用いて電子部品の接続を行うに際し、加熱,溶融時においてその 接続材料の厚さ(高さ)を一定に保持できるようにして、接続後において所定の 熱サイクル強度を得られるようにすることである。The present invention has been made in view of such conventional circumstances, and an object thereof is to, when connecting electronic components by using solder, when connecting the thickness of the connecting material during heating and melting. (Height) can be kept constant so that a predetermined heat cycle strength can be obtained after connection.

【0005】[0005]

【課題を解決するための手段】[Means for Solving the Problems]

前述の目的を達成するために、本考案に係る複合半田は、上下夫々に平行な接 線を有し、且つ半田よりも高融点の材質で成形したスペーサ部材を、所定の厚み を有する半田層中に入れてなることを特徴とする。 In order to achieve the above-mentioned object, the composite solder according to the present invention is a solder layer having a predetermined thickness, which has a spacer member formed by a material having a melting point higher than that of the solder and having parallel parallel upper and lower tangent lines. It is characterized by being put inside.

【0006】[0006]

【作用】[Action]

本考案の複合半田によれば、接続しようとする二部材間に半田層とスペーサ部 材が介在し、半田溶融時においてスペーサ部材の上,下の接線が各部材に各々接 することで夫々の部材が互いに平行に支持されるをもって、溶融時における半田 層の厚さ(高さ)を一定に保持し得、固化後の厚さを均一にできる。 According to the composite solder of the present invention, the solder layer and the spacer member are interposed between the two members to be connected, and when the solder melts, the tangent lines above and below the spacer member contact each member respectively. Since the members are supported in parallel with each other, the thickness (height) of the solder layer at the time of melting can be kept constant, and the thickness after solidification can be made uniform.

【0007】[0007]

【実施例】【Example】

以下、本考案複合半田の実施例を、半導体チップBを基板C上に固定するため の接合材料として使用するものを例にとり、図面を参照して説明する。 図1及び2で示す複合半田Aは、薄肉帯状に形成した半田層1中に、さらに薄 肉な帯状のスペーサ部材2を埋設してほぼテープ状(若しくはリボン状)に作製 した実施例を示す。 Hereinafter, an embodiment of the composite solder of the present invention will be described with reference to the drawings, taking as an example a material used as a bonding material for fixing a semiconductor chip B onto a substrate C. The composite solder A shown in FIGS. 1 and 2 shows an example in which a thinner band-shaped spacer member 2 is embedded in a solder layer 1 formed in a thin band shape to produce a substantially tape shape (or ribbon shape). .

【0008】 半田層1は、PbSn,PbAgSn等の周知な半田材を用いて、半導体チップBよりや や小幅で、且つ0.1mm 程度の厚みを備えた薄肉帯状に作製される。半田層1中に は、半田層1の長さ方向へ沿って延びる帯状のスペーサ部材2を埋設する。The solder layer 1 is made of a well-known solder material such as PbSn, PbAgSn or the like, and is formed in a thin band shape having a width slightly smaller than that of the semiconductor chip B and a thickness of about 0.1 mm. A strip-shaped spacer member 2 extending along the length direction of the solder layer 1 is embedded in the solder layer 1.

【0009】 スペーサ部材2は、半田層1を構成する半田よりも高融点(少なくとも50℃ 以上)な材料、例えば、Cu,Ni,Mo,W,セラミック,アルミナ,ガラス ,BN等を用いて、半田層1内に埋設可能な薄肉帯状に作製する。The spacer member 2 is made of a material having a melting point (at least 50 ° C. or higher) higher than that of the solder forming the solder layer 1, for example, Cu, Ni, Mo, W, ceramics, alumina, glass, BN, etc. It is formed into a thin strip that can be embedded in the solder layer 1.

【0010】 スペーサ部材2はその上下面に、互いに平行となる接線2a,2aを有する。これ ら接線2a,2aは半田溶融時において、半導体チップB,基板Cに接することで、 該チップB,基板Cを互いに平行に支持する。 尚、上記スペーサ部材2は、Ag,Au,Cu,Ni等の金属膜を表面に形成 したり、フラックスで表面処理するなどして、半田との馴染みを良くすることが 好ましい。The spacer member 2 has tangent lines 2a, 2a which are parallel to each other on the upper and lower surfaces thereof. These tangents 2a and 2a contact the semiconductor chip B and the substrate C when the solder is melted, thereby supporting the chip B and the substrate C in parallel with each other. It is preferable that the spacer member 2 has a metal film made of Ag, Au, Cu, Ni or the like formed on the surface thereof or is surface-treated with a flux to improve the familiarity with the solder.

【0011】 本実施例の複合半田Aの使用方法を説明すれば、まず、前述の如くテープ状に 作製した複合半田Aの先端部分を、半導体チップBより一回り小さな方形片状( チップ状)に切断し、これを基板C上に載承し、その上に半導体チップBをセッ トする(図2(a) 参照)。The method of using the composite solder A of this embodiment will be described. First, the tip of the composite solder A produced in a tape shape as described above is a square piece (chip shape) that is one size smaller than the semiconductor chip B. It is cut into chips, mounted on a substrate C, and a semiconductor chip B is set on it (see FIG. 2 (a)).

【0012】 この状態でチップ状の複合半田Aを加熱すれば、半田層1が溶融すると共に、 スペーサ部材2の上,下の接線2a,2aが半導体チップB,基板Cに接することで 、半導体チップBを基板Cに対して平行に支持し、これにより溶融する半田の厚 さが均一に保たれ、固化後の半田層1’の厚さを一定に保持する(図2(b) 参照 )。When the chip-shaped composite solder A is heated in this state, the solder layer 1 is melted, and the upper and lower tangents 2a and 2a of the spacer member 2 are in contact with the semiconductor chip B and the substrate C, respectively. The chip B is supported in parallel with the substrate C, so that the thickness of the melted solder is kept uniform, and the thickness of the solidified solder layer 1'is kept constant (see FIG. 2 (b)). .

【0013】 従って、半導体チップBと基板Cとを接続した状態において、その接続部分、 即ち、固化後の複合半田A’に部分的に薄肉な箇所が形成されず、該接続部分全 域で所定の熱サイクル強度を得られる。よって、温度変化による半導体チップB の剥離や導通不良が生じる虞れのない、信頼性の高い半導体装置Dが提供される 。Therefore, in the state where the semiconductor chip B and the substrate C are connected to each other, a thin portion is not partially formed in the connecting portion, that is, the composite solder A ′ after solidification, and the predetermined portion is formed in the entire connecting portion. The thermal cycle strength of can be obtained. Therefore, it is possible to provide a highly reliable semiconductor device D in which there is no risk of peeling of the semiconductor chip B 1 or conduction failure due to temperature change.

【0014】 図3及び4で示す複合半田Eは、前述せる実施例における断面矩形状のスペー サ部材2に代えて、断面X字形のスペーサ部材3を埋設した実施例を示す。The composite solder E shown in FIGS. 3 and 4 shows an embodiment in which a spacer member 3 having an X-shaped cross section is buried in place of the spacer member 2 having a rectangular cross section in the above-described embodiment.

【0015】 この実施例のスペーサ部材3は、前述のスペーサ部材2同様にCu,Ni,M o,W,セラミック,アルミナ,ガラス,BN等を用いて、半田層1内に埋設可 能な大きさで、且つ断面X字形の長尺状に作製し、その上下面における左右の端 部3a,3a間に、互いに平行となる接線3b,3bを形成する。これら接線3b,3bは半 田溶融時において、半導体チップB,基板Cに接することで、該チップB,基板 Cを互いに平行に支持する。The spacer member 3 of this embodiment is made of Cu, Ni, Mo, W, ceramics, alumina, glass, BN, etc., similarly to the spacer member 2 described above, and has a size that can be embedded in the solder layer 1. Then, it is manufactured in a long shape with an X-shaped cross section, and tangential lines 3b, 3b parallel to each other are formed between the left and right ends 3a, 3a on the upper and lower surfaces thereof. These tangent lines 3b and 3b contact the semiconductor chip B and the substrate C at the time of melting the semiconductor, thereby supporting the chip B and the substrate C in parallel with each other.

【0016】 尚、このスペーサ部材3においても、Ag,Au,Cu,Ni等の金属膜を表 面に形成したり、フラックスで表面処理するなどして、半田との馴染みを良くす ることが好ましい。Also in this spacer member 3, a metal film of Ag, Au, Cu, Ni or the like may be formed on the surface or may be surface-treated with flux to improve the familiarity with solder. preferable.

【0017】 而して、この実施例の複合半田Eの使用方法を説明すれば、まず、複合半田E の先端部分を、半導体チップBより一回り小さな方形片状(チップ状)に切断し 、これを基板C上に載承し、その上に半導体チップBをセットする(図4(a) 参 照)。The method of using the composite solder E of this embodiment will now be described. First, the tip portion of the composite solder E is cut into a rectangular piece (chip shape) that is slightly smaller than the semiconductor chip B, This is mounted on the substrate C and the semiconductor chip B is set on it (see FIG. 4 (a)).

【0018】 この状態でチップ状の複合半田Eを加熱すれば、半田層1が溶融すると共に、 スペーサ部材3の上,下の接線3b,3bが半導体チップB,基板Cに接することで 、半導体チップBを基板Cに対して平行に支持し、これにより溶融する半田の厚 さが均一に保たれ、固化後の半田層1’の厚さを一定に保持する(図4(b) 参照 )。When the chip-shaped composite solder E is heated in this state, the solder layer 1 is melted and the tangential lines 3b and 3b above and below the spacer member 3 are in contact with the semiconductor chip B and the substrate C, respectively. The chip B is supported in parallel with the substrate C, so that the thickness of the melted solder is kept uniform and the thickness of the solder layer 1'after solidification is kept constant (see FIG. 4 (b)). .

【0019】 従って前述の実施例同様、固化後の複合半田E’に部分的に薄肉な箇所が形成 されず、該接続部分全域で所定の熱サイクル強度を得られる。よって、温度変化 による半導体チップBの剥離や導通不良が生じる虞れのない、信頼性の高い半導 体装置Dが提供される。Therefore, similarly to the above-described embodiment, a thin portion is not partially formed in the solidified composite solder E ′, and a predetermined heat cycle strength can be obtained in the entire connection portion. Therefore, there is provided a highly reliable semiconductor device D in which there is no risk of peeling of the semiconductor chip B or defective conduction due to temperature change.

【0020】 尚、スペーサ部材の断面形状については、上記以外にも略W字状,略M字状, 逆凹形状等が考えられ、要するに、上下夫々に平行な接線を構成可能な断面形状 であれば、何等限定されない。Regarding the cross-sectional shape of the spacer member, other than the above, a substantially W-shape, a substantially M-shape, an inverted concave shape, and the like are conceivable. In short, a cross-sectional shape capable of forming tangent lines parallel to each other in the upper and lower sides is possible. If there is no limitation.

【0021】 また、本考案の複合半田は図示する長尺状のものに限定されず、例えば、半田 層中にスペーサ部材(2,3)を並列状に備えたシート形に作製して、使用時に 所定寸法のチップ状に切断したり、若しくは予めチップ状に成形するなど、その 外観形状については任意である。Further, the composite solder of the present invention is not limited to the illustrated long one, and for example, it is used by making it into a sheet shape in which spacer members (2, 3) are arranged in parallel in the solder layer. At times, the external shape is arbitrary, such as cutting it into a chip of a predetermined size or preliminarily molding it into a chip.

【0022】 さらに、上記各実施例では半導体チップBを基板C上に固定するための接合材 料について説明したが、本考案はこれに限定されず、各種電子部品の接続に使用 可能であり、接続しようとする二部材の大きさに合わせて半田層やスペーサ部材 の大きさ,形状等を適宜に変更することはいうまでもない。Further, in each of the above embodiments, the bonding material for fixing the semiconductor chip B onto the substrate C has been described, but the present invention is not limited to this, and can be used for connecting various electronic parts. It goes without saying that the size and shape of the solder layer and the spacer member are appropriately changed according to the size of the two members to be connected.

【0023】[0023]

【考案の効果】[Effect of device]

本考案に係る複合半田は以上説明したように構成したことから、半田層中のス ペーサ部材によって半田溶融後の厚さ(高さ)を均一に保持して、接続後におけ る熱サイクル強度の低下を防止し得る。よって、温度変化による半導体チップの 剥離や導通不良が生じる虞れのない、信頼性の高い半導体装置の製造に極めて有 用である。 Since the composite solder according to the present invention is configured as described above, the spacer member in the solder layer keeps the thickness (height) after melting the solder uniform, and the thermal cycle strength It can prevent the deterioration. Therefore, it is extremely useful for manufacturing a highly reliable semiconductor device in which there is no possibility of peeling of a semiconductor chip or defective conduction due to temperature change.

【図面の簡単な説明】[Brief description of drawings]

【図1】本考案に係る複合半田の一実施例を示す斜視図
で、一部切欠して表す。
FIG. 1 is a perspective view showing an embodiment of a composite solder according to the present invention, with a part cut away.

【図2】本考案複合半田を用いて半導体チップを基板に
接続する状態の断面図で、(a)は半田の溶融前を、(b)
は半田の溶融後を、夫々表す。
FIG. 2 is a cross-sectional view of a state in which a semiconductor chip is connected to a substrate by using the composite solder of the present invention, (a) before melting of solder, (b)
Indicates after the solder is melted.

【図3】本考案に係る複合半田の他の実施例を示す斜視
図で、一部切欠して表す。
FIG. 3 is a perspective view showing another embodiment of the composite solder according to the present invention, with a part cut away.

【図4】図3に係る複合半田を用いて半導体チップを基
板に接続する状態の断面図で、(a)は半田の溶融前を、
(b)は半田の溶融後を、夫々表す。
FIG. 4 is a cross-sectional view of a state in which a semiconductor chip is connected to a substrate using the composite solder according to FIG. 3, (a) shows before melting of the solder,
(b) shows after the solder is melted.

【図5】従来の接続材料を用いて半導体チップを基板に
接続する状態の断面図で、半田溶融前を仮想線で、溶融
後を実線で、夫々表す。
FIG. 5 is a cross-sectional view of a state in which a semiconductor chip is connected to a substrate using a conventional connecting material, in which a phantom line indicates before solder melting and a solid line indicates after melting.

【符号の説明】[Explanation of symbols]

A,E:複合半田 1:半田層 2,
3:スペーサ部材 2a,3b:接線 B:半導体チップ C:
基板
A, E: Composite solder 1: Solder layer 2,
3: Spacer members 2a, 3b: Tangent line B: Semiconductor chip C:
substrate

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】 上下夫々に平行な接線を有し、且つ半田
よりも高融点の材質で成形したスペーサ部材を、所定の
厚みを有する半田層中に入れてなることを特徴とする複
合半田。
1. A composite solder, characterized in that spacer members having upper and lower parallel tangent lines and formed of a material having a melting point higher than that of solder are put in a solder layer having a predetermined thickness.
JP5121892U 1992-07-21 1992-07-21 Compound solder Pending JPH069784U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5121892U JPH069784U (en) 1992-07-21 1992-07-21 Compound solder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5121892U JPH069784U (en) 1992-07-21 1992-07-21 Compound solder

Publications (1)

Publication Number Publication Date
JPH069784U true JPH069784U (en) 1994-02-08

Family

ID=12880792

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5121892U Pending JPH069784U (en) 1992-07-21 1992-07-21 Compound solder

Country Status (1)

Country Link
JP (1) JPH069784U (en)

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