JPH07105019A - Instruction simulator processing system - Google Patents

Abstract

PURPOSE:To provide an instruction simulator processing system which can be executed even when a stack overflows. CONSTITUTION:A simulator 101 is provided with the input part 106 of indication information on a console 102, the file input part 104 of program information on an input file 103, an instruction input part 116 reading program information from a program memory part 108, a data memory part 109 including a stack memory part 110, a register memory part 112, an instruction execution part 118 executing an instruction by the instruction analysis result of an instruction analysis part 117, a comparison part 123 comparing and collating the value of a stack pointer part 115 with/to the value of a stack regulation part 122, a switching part 124 switching a stack operation destination by the compared result of the comparison part 123, a control part 107 controlling the file input part 104, the instruction input part 116, the instruction analysis part 117, the instruction execution part 118 and the stack regulation part 122, and the output part 105 of control result by the control part 107.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction simulator processing method, and more particularly to an instruction simulator processing method used as a simulation method of a microcomputer program.

[0002]

2. Description of the Related Art Generally, in any program, a stack operation instruction is executed during instruction simulation of the program. Then, if the stack operation is repeated many times, the stack is sequentially stacked in the stack area correspondingly. The programmer considers how much this stack operation can stack up to,
It is necessary to secure a stack area for that purpose.
In the case of a program that is used as a data area even in the area immediately near this stack area, if the stack area is not secured properly and is insufficient, it extends beyond the stack area to the data area. Also becomes a state where the stack is piled up, which may eventually cause the program to run out of control.

In the conventional instruction simulator processing method, in order to check whether or not a stack overflow has occurred during instruction simulation, the lower limit value of the stack address is input in advance as a prescribed value of the stack. Each time a stack manipulation instruction is executed, it is checked whether the stack pointer is below the specified value, and if it is below the specified value, a warning message is usually output. . However, although the warning message can be issued, once the program goes into a runaway state, it becomes impossible to correctly continue and execute the simulation thereafter.

In the "virtual memory management system and computer system (Japanese Patent Laid-Open No. 3-113550)", an expandable virtual space is proposed as a method for avoiding an error occurrence due to stack overflow.
The proposal relates to stack processing of a self-system computer such as an OS, and therefore, data memory and register memory including program memory and stack memory are all mapped to the same real address on the same address space. When debugging a microcomputer program by simulation, it is necessary to debug all the memory in the address space corresponding to the address as programmed, and in the simulation, allocate each memory to the virtual space for debugging. Therefore, the proposal by the above "virtual memory management system and computer system (JP-A-3-113550)" cannot be applied to this instruction simulator processing method.

[0005]

In the above-described conventional instruction simulator processing method, it is checked whether or not a stack overflow has occurred, and if the stack pointer is below a prescribed value, a warning is issued. Although a message can be issued, once the program runs out of control, it is impossible to continue and correctly execute the simulation thereafter. For this,
The program will be redesigned, including changes in the stack size or data area allocation, etc., the program will be modified, and the object file will be recreated by the assembler compiler, etc. The disadvantage is that it requires a lot of time.

[0006]

The instruction simulator processing method of the present invention is a predetermined instruction simulator processing method for a microcomputer having an instruction analyzing means, an instruction executing means, a program memory means, a data memory means and a register memory means. Input means for inputting instruction information from the console, file input means for inputting program information from a predetermined input file and storing it in the program memory means, and instruction information input from the console via the input means A stack defining means for setting a predetermined stack defining value, an instruction inputting means for reading program information from the program memory means and outputting the program information to the instruction analyzing means, and an instruction analyzing result by the instruction analyzing means. , The register via the instruction executing means The value set in the memory unit is compared with the value set in the stack defining unit, and the value set in the register memory unit is identified by referring to the comparison result by the comparing unit. And a stack memory means and a spare stack memory means for separately storing the values identified and output by the switching means, and the stack is defined by the stack definition means. When it is detected that the value is exceeded, the spare stack memory means functions as an extension of the stack memory means in the data memory, and the simulation processing is normally performed without hindering the execution of the simulator. Is characterized by.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a system configuration diagram of an embodiment of the present invention. As shown in FIG. 1, the present embodiment has a simulator 101, a console 102, and an input file 10.
3, the simulator 101, which is a main component described above, has an input unit 106 for inputting start instruction information from a console 102, a file input unit 104 for inputting program information from an input file 103,
A program memory unit 108 that holds the input program information, an instruction input unit 116 that reads the program information from the program memory unit 108, an instruction analysis unit 117 that receives the read program information and analyzes the instruction.
Data memory unit 109 including stack memory unit 110
And a register memory unit 1 including a BC register unit 113, an HL register unit 114, and a stack pointer unit 115.
12, a data operation instruction execution unit 119 that operates the data memory unit 109, a stack operation instruction execution unit 120 that operates the stack memory unit 110, and a register memory unit 1
12 including a register operation instruction unit 121 for operating 12, an instruction execution unit 118 that executes an instruction according to the instruction analysis result of the instruction analysis unit 117, a stack definition unit 122, a value of the stack pointer unit 115, and a stack definition unit 122. A comparing unit 123 that compares and collates values, a switching unit 124 that switches the stack operation destination according to the comparison result of the comparing unit 123, a spare stack memory unit 111, and a file input unit 104 and an instruction input unit according to an instruction from the input unit 106 116, instruction analysis unit 117, instruction execution unit 118, and stack definition unit 1
22 and an output unit 105 that outputs the control result of the control unit 107 to the console 102.
And is configured.

FIG. 2 shows a part of the program information of the sample assembler source image of the input file 103 created by the user, and the information content is as follows.

201: The value of the stack pointer (SP) is set to F000H.

202: The value of the BC register is set to 1234H.

203: The value of the HL register is set to 5678H.

204: Pushes the contents of the BC register onto the stack.

205: Pushes the contents of the HL register onto the stack.

206: Latch from stack and input to BC register.

207: Latch from the stack and input to the HL register.

In FIG. 2, if this program is correctly simulated from the instruction 201 to the instruction 207 shown in FIG. 2, two stacks are stacked by one PUSH instruction.
The value of 15 temporarily decreases to the value of the maximum EFFCH and becomes the value of F000H again, and the BC register unit 113
The value of 5678H is input to the HL register unit 1
The value of 1234H is input to 14.

FIG. 3 shows operation procedure information on the console 102 by the user, and the information content is as follows.

301: Shows an instruction to read the program of FIG. 2 into the simulator.

302: Indicates an instruction to set the stack specified value as the lower limit value of the stack address to EFFEH.

303: Shows a program execution instruction.

First, the user inputs a program load instruction to the console 102 (301).
By the control action of the input unit 106 and the control unit 107, the program information is input to the program memory unit 108 from the input file 103 in which the program information (see FIG. 2) is stored, via the file input unit 104. Next, an instruction to set the stack specified value EFFEH as the lower limit value of the stack address is issued to the console 102 (302), and the input unit 106 controls the control unit 1.
The execution is instructed to 07. Then, next, a program execution instruction is issued to the console 102 (3
03).

In response to this, the input unit 106 instructs the control unit 107 to execute the program, and the control unit 1
Due to the control action by 07, the first instruction 201 (see FIG. 2) at the beginning of program execution causes the program memory unit 1 to
It is read out from 08 and inputted to the instruction analysis section 117 via the instruction input section 116. The instruction analysis unit 117 analyzes the content of the instruction, and the analysis result is stored in the register memory unit 11 via the register operation instruction execution unit 121.
2 is input to the stack pointer unit 115 included in
F000H is set in the stack pointer section 115. Subsequently, the instruction 202 (see FIG. 2) is read from the program memory unit 108 by the control action of the control unit 107, and the instruction analysis unit 11 is executed via the instruction input unit 116.
Input to 7. In the instruction analysis unit 117, the content of the instruction is analyzed, and the analysis result is input to the BC register unit 113 included in the register memory unit 112 via the register operation instruction execution unit 121, and then to the BC register unit 113. 1234H is set.

Similarly, the instruction 203 (see FIG. 2) is read from the program memory unit 108 by the control operation of the control unit 107 and input to the instruction analysis unit 117 via the instruction input unit 116. The instruction analysis unit 117 analyzes the content of the instruction, and the analysis result is stored in the register memory unit 1 via the register operation instruction execution unit 121.
It is input to the HL register unit 114 included in 12, and 5678H is set in the HL register unit 114. Next, the control unit 107 controls the command 204.
(See FIG. 2) is read from the program memory unit 108 and input to the instruction analysis unit 117 via the instruction input unit 116. The instruction analysis unit 117 analyzes the content of the instruction, and the analysis result is stored in the register memory unit 112 via the register operation instruction execution unit 121.
The value 1234H set in the C register unit 113 is read and input to the stack operation instruction execution unit 120.
In the stack operation instruction execution unit 120, first, the upper value 12H of the value is separated and sent to the switching unit 124. At this time, F00 in the stack pointer unit 115
Since the value of 0H is larger than the value EFFEH of the stack defining unit 122, the value of 12H is stacked as a stack in the stack memory unit 110 via the switching unit 124. Further, the value set in the stack pointer section 115 is decremented to EFFFH. Next, in the stack operation instruction execution unit 120, the lower value 3 of the value is further calculated.
4H is separated and sent to the switching unit 124, but since the value of EFFFH in the stack pointer unit 115 is larger than the value EFFEH of the stack defining unit 122, the value of 34H is passed through the switching unit 124. Stacked at 110. Further, the value set in the stack pointer unit 115 is decremented by E.
It becomes FFEH.

Next, the instruction 205 (see FIG. 2) causes the program memory unit 10 to execute the instruction 205 under the control action of the control unit 107.
8 and is input to the instruction analysis unit 117 via the instruction input unit 116. The instruction analysis unit 117 analyzes the content of the instruction, and the analysis result is stored in the register memory unit 11 via the register operation instruction execution unit 121.
2 is input to the HL register unit 114 included in
The value 5678H of the L register unit 114 is read and sent to the stack operation instruction execution unit 120. In the stack operation instruction execution unit 120, first, the upper value 5 of the value is
6H is separated and sent to the switching unit 124. At this time, the value of EFFFH in the stack pointer unit 115 is not larger than the value EFFEH of the stack defining unit 122, so the value of 56H is stacked as a stack in the spare stack memory unit 111 via the switching unit 124. Further, the value of the stack pointer section 115 is decremented by E.
It becomes FFDH. Next, in the stack operation instruction execution unit 120, the lower value 78H of the value is changed to the switching unit 12.
4, the value of the EFFDH in the stack pointer unit 115 is the value EFF of the stack defining unit 122.
Since it is not larger than EH, the value of 78H is stacked as a stack in the preliminary stack memory unit 111 via the switching unit 124. Further, the value of the stack pointer section 115 is decremented to EFFCH.

Subsequently, the control function of the control unit 107 causes the instruction 206 (see FIG. 2) to be executed by the program memory unit 10.
8 and is input to the instruction analysis unit 117 via the instruction input unit 116. The instruction analysis unit 117 analyzes the content of the instruction, and the stack operation instruction execution unit 120 causes the switching unit 124 to latch two values. At this time, the value of the stack pointer unit 115 is incremented to EFFDH, but since this value is not larger than the value EFFEH of the stack defining unit 122, the stack is read from the standby stack memory unit 111 via the switching unit 124. Issued, the first value 78H
Is sent to the instruction execution unit 118 as a lower value. And
Further, the value of the stack pointer section 115 is incremented to EFFEH, and this value is equal to the stack definition section 1
Since it is not larger than the value EFFEH of 22, the switching unit 12
The stack is read from the backup stack memory unit 111 via 4 and the second value 56H is sent to the instruction execution unit 118 as an upper value. In the instruction execution unit 118,
The obtained value 5678H is the register operation instruction execution unit 121.
Is transmitted to the register operation instruction execution unit 121,
It is set in the BC register unit 113.

Then, the control action of the control unit 107 causes the instruction 207 (see FIG. 2) to be executed by the program memory unit 10.
8 and is input to the instruction analysis unit 117 via the instruction input unit 116. The instruction analysis unit 117 analyzes the content of the instruction, and the stack operation instruction execution unit 120 causes the switching unit 124 to latch two values. At this time, the value of the stack pointer unit 115 is incremented to EFFFH. Since this value is larger than the value EFFEH of the stack defining unit 122, the stack is read from the stack memory unit 110 via the switching unit 124. Then, the first value 34H is sent to the instruction execution unit 118 as a lower value. Then, the value of the stack pointer section 115 is further incremented by E.
000H, which is larger than the value EFFEH of the stack defining unit 122, the stack is read from the stack memory unit 110 via the switching unit 124, and the second value 12H is used as the upper value of the instruction executing unit. Sent to 118. In the instruction execution unit 118, the obtained value 123
4H is transmitted to the register operation instruction execution unit 121, and the HL register unit 1 is transmitted via the register operation instruction execution unit 121.
It is set to 14.

Next, the processing steps in the switching unit 124 when the value X is sent from the stack operation instruction execution unit 121 to the switching unit 124, that is, the contents of the PUSH processing will be described with reference to the flowchart of FIG. To do.

First, in step 401, the value of the stack pointer (SP) is compared with the specified stack value. If the value of the stack pointer is larger, the process proceeds to step 402 and conversely the value of the stack pointer is changed. If it is not larger, the process proceeds to step 403. In step 402, the stack memory unit 110 is loaded with the value X, and the process proceeds to step 404. On the other hand, step 403
In, the value X is stored in the spare stack memory unit 111, and the process proceeds to step 404. These steps 402
Then, in step 404 following step 403, the stack pointer is decremented (SP-
1), this processing step ends.

Next, the processing steps in the switching unit 124 when the stack operation instruction executing unit 120 latches the value X to the switching unit 124, that is, the contents of the POP processing will be described with reference to the flowchart of FIG. To do.

First, in step 501, the stack pointer is incremented, and in step 502, the value of the stack pointer (SP) is compared with the stack prescribed value. If the value of the stack pointer is larger, step 503. If the stack pointer value is not larger, the process proceeds to step 504. In step 503, the stack memory unit 11
The value X is read from 0, and this processing step ends. On the other hand, in step 504, the spare stack memory unit 11
The value X is read from 1, and this processing step ends.

Next, as a second embodiment of the present invention, FIG.
2 is input based on the instruction procedure information shown in FIG. 2, a case where a spare stack memory use message is output to the console 102 will be described with reference to the flowchart of PUSH processing in FIG. .

First, in step 601, the value of the stack pointer (SP) is compared with the specified stack value. If the value of the stack pointer is larger, the process proceeds to step 602 and conversely the stack pointer value If it is not larger, the process proceeds to step 603. In step 602, the stack memory unit 110 is loaded with the value X, and the process proceeds to step 605. On the other hand, in step 603, the value X is stored in the spare stack memory unit 111, and the process proceeds to step 604. In step 604,
The control unit 107 is instructed to output a message to use the spare stack memory unit 111, the output unit 105 outputs the message to the console 102, and the process proceeds to step 605. Following these steps 602 and 604, step 60
In 5, the stack pointer is decremented (SP-1), and this processing step ends.

[0034]

As described above, according to the present invention, when it is detected that the stack exceeds the specified value, the spare stack memory is used as an extension of the stack memory in the data memory. It is possible to correctly perform the simulation processing without stopping the execution, and it is possible to eliminate the redo of the simulation work due to the bug caused by the stack overflow.

[Brief description of drawings]

FIG. 1 is a system configuration diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing program information of an input file.

FIG. 3 is a diagram showing instruction procedure information input to a console.

FIG. 4 is a diagram showing a flowchart of PUSH processing in the first embodiment.

FIG. 5 is a diagram showing a flowchart of POP processing in the first embodiment.

FIG. 6 is a diagram showing a flowchart of PUSH processing in the second embodiment.

[Explanation of symbols]

 101 simulator 102 console 103 input console 104 file input unit 105 output unit 106 input unit 107 control unit 108 program memory unit 109 data memory unit 110 stack memory unit 111 spare stack memory unit 112 register memory unit 113 BC register unit 114 HL register unit 115 Stack pointer unit 116 Instruction execution unit 117 Instruction analysis unit 118 Instruction execution unit 119 Data manipulation instruction execution unit 120 Stack manipulation instruction execution unit 121 Register manipulation instruction execution unit 122 Stack definition unit 123 Comparison unit 124 Switching unit

Claims (1)

[Claims] 1. An instruction simulator processing method for a microcomputer having an instruction analyzing means, an instruction executing means, a program memory means, a data memory means and a register memory means, and input means for inputting instruction information from a predetermined console, and a predetermined means. A predetermined stack prescribed value is set through file input means for inputting program information from the input file of the above and storing it in the program memory means, and instruction information input from the console through the input means. A stack defining means, an instruction input means for reading out program information from the program memory means and outputting the program information to the instruction analyzing means, and an instruction analysis result by the instruction analyzing means to cause the register memory means via the instruction executing means. The set value and the stack defining means Comparing means for comparing the set value with each other; switching means for identifying and outputting the value set in the register memory means by referring to the comparison result by the comparing means; A stack memory means and a spare stack memory means for separately storing the values output by the above, as a simulator, and when it is detected that the stack exceeds the stack specified value, An instruction simulator processing method, wherein the auxiliary stack memory means functions as an extension of the stack memory means in the data memory, and normally performs the simulation processing without hindering the execution of the simulator.