JPH07105695A - Read only memory - Google Patents

Abstract

PURPOSE:To eliminate charge-up after a bit line is selected, to operate a read only memory at high speed and to simplify a design by ususally maintaining a part of the bit lines not selected by column address inform mation at a prescribed potential. CONSTITUTION:The address information same as the column address information Am inputted to a Y selector 6 is inputted to a decoder circuit 9. Then, NMOS transistors adjacent each other along the same group are connected to no common output line. Then, for instance, the column address information Am excepting a most significant bit may be imparted to the decoder circuit 9. Further, the number of input bits of the decoder circuit 9 are selected optionally within the range of the address information Am. In such a case, the time required from when the address change occurs to the read of a sense amplifier is satisfied with only the time required for the potential change 20-30mV in the bit line. Further, the complex timing design for generating a precharging timing signal is eliminated also.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read-only memory, and more particularly to a read-only memory capable of high-speed reading.

[0002]

2. Description of the Related Art A read-only memory, like many other semiconductor memory devices, is required to have a higher storage capacity and a higher operating speed.

FIG. 4 shows, for example, Japanese Patent Application Laid-Open No. 62-189649.
FIG. 6 is a schematic block diagram illustrating the configuration of a conventional read-only memory disclosed in Japanese Patent Publication No. 63-291289. In the figure, the read-only memory is provided for each of the memory cell array 100 arranged in the row and column directions and storing a predetermined potential information, and a memory cell array 100 arranged in the row direction. Word line 1
01, a bit line 102 provided for each memory cell group arranged in the column direction and reading out potential information from the memory cells in the memory cell group, and an X decoder 2 for selecting the word line 101 based on the row address information. , A Y selector 6 for selecting the bit line 102 based on the column address information;
A precharge circuit 11 for charging up the bit line 102 selected by the selector 6, a timing generation circuit 3 for giving a timing signal for precharge to the precharge circuit 11, and a bit line selected by the Y selector 6. It has a sense amplifier 7 for detecting potential information read from the memory cell 1 by detecting the potential of the memory cell 102.

FIG. 5A is a timing chart showing the precharge signal φ _P in the read-only memory together with the address change timing. As shown in the figure, the precharge timing signal φ _P is periodically generated with a delay of a predetermined time t ₀ from the timing when the address changes. FIG. 5B shows the potential change of the bit line 102 and the change of the sense amplifier output at the time of each address change in FIG. When a particular bit line by the address change is selected, the bit lines, have reduced its potential by previous reading, firstly, a predetermined potential V _P by the precharge signal phi _P, for example, 1 to 1.
Charged up to 5V.

Next, the potential of the bit line 102 changes according to the potential information stored in the selected memory cell. For example, if the information of the memory cell is "0", the potential drops by about 20 to 30 mV. After a lapse of a predetermined time from the completion of precharge, this potential change is detected by the sense amplifier, and the output of the sense amplifier is lowered to the L level as shown. As a result, the potential information of the memory cell is read.

[0006]

In the above conventional read-only memory, the word line is generally formed of polysilicon forming the wiring layer, and the parasitic resistance and the parasitic capacitance with the substrate cannot be ignored. . Due to such parasitic resistance and parasitic capacitance, a time delay occurs in the rise of the voltage level when the word line is selected. Although the bit line is generally formed as a metal wiring layer, a parasitic capacitance exists between the bit line and the substrate, and it takes time to charge up due to the parasitic capacitance and the parasitic resistance. In the read-only memory, the access mode in which the column address information changes in sequence is generally adopted, and thus the rise delay time of the bit line has a great influence on the access speed. This time delay becomes particularly significant as the memory capacity increases, making it difficult to speed up access.

Particularly in a large-capacity read-only memory, there is an example in which a word line or a bit line is divided to reduce its parasitic capacitance and parasitic resistance in order to shorten the access time. However, when the word line or the bit line is divided, a large number of row (X) decoders or column (Y) selectors are arranged correspondingly, which has a disadvantage of increasing the chip area of the read-only memory.

Further, the timing of the precharge signal φ _P is set in accordance with the timing of the change of the address information, and also when the signal is read from the sense amplifier,
It is necessary to set the timing corresponding to the timing of generating the precharge signal. Therefore, there is a problem in that the timing of the precharge signal needs to be devised to complicate the timing design in the read-only memory.

In view of the above, the present invention provides a high-speed read-only memory capable of shortening the access time, and provides a read-only memory which suppresses an increase in the chip area thereof and has an easy timing design. To aim.

[0010]

In order to achieve the above object, a read-only memory according to the present invention comprises a plurality of memory cells arranged in the row and column directions and each storing predetermined potential information, and arranged in the row direction. A word line for selecting the selected memory cell group, a bit line arranged corresponding to the memory cell group arranged in the column direction, for reading the potential information from the memory cells of the memory cell group, and row address information. A row decoder that selects the word line based on the column address, a column selector that selects the bit line based on column address information, a sense amplifier that reads the potential of the bit line selected by the column selector, and a column selector. Bias means for always maintaining at least one group of unselected bit lines at a predetermined potential.

The bias means is connected to, for example, a column decoder for decoding column address information, a bit line and a bias power supply of a predetermined potential in a normal state, is controlled by the output of the decoder, and is selected by the column selector. The bit line can be composed of a switch means for opening the bias power supply.

Further, as a group of bit lines that are always connected to the bias power supply, only a group of bit lines adjacent to the bit line selected by the column selector can be selected. If such a configuration is adopted, the current consumption of the bias power supply can be reduced.

[0013]

In the read-only memory of the present invention, since the bit line not selected by the column selector is kept at a predetermined potential, charge-up is not required when the bit line is selected next time. Will reduce the time required to charge up, and
Timing design is simple.

[0014]

The present invention will be described in more detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a read-only memory according to the first embodiment of the present invention. The read-only memory of the present embodiment has a large number of memory cells 1 arranged in the row and column directions and having predetermined potential information, a word line 101 provided for each memory cell group arranged in the row direction, and a column direction. Bit lines 102 and 103 provided for each of the arranged memory cell groups and electrically connected to the selected memory cell 1 in the group, and an X decoder for selecting one of the word lines 101 based on the row address information A _n. Y selector 6 for selecting and 2, one of the bit lines 102 and 103 based on the column address information a _m
If, decoder circuit 9 decodes the column address information A _m
And the bit line 10 controlled by the output of the decoder circuit 9.
2 and 103 and the NMOS transistor 5 for electrically connecting the bias circuit 4 and the memory cell 1 to the bit lines 102, 1
And a sense amplifier 7 for detecting the signal potential read out via signal line 03.

The same address information as the column address information A _m input to the Y selector 6 is input to the decoder circuit 9. Each output line XP ₀ of the decoder circuit 9 (showing P _{0 with} a top bar, the same applies hereinafter), XP ₁ , ..., XP _q
Is connected to the gate of each NMOS transistor 5.
Here, as shown in the figure, one output line of the decoder 9 is input to the gates of the NMOS transistors 5 at two locations, for example. The NMOS transistors 5 connected to one output line of the decoder circuit are chosen so that they are not arranged close to each other. That is, the mutually adjacent NMOS transistors belonging to the same group are not connected to the common output line.

Therefore, for example, the most significant bit of the column address information A _m may be removed and given to the decoder circuit 9.
The number of input bits of the decoder circuit 9 is the address information A
_It can be arbitrarily selected within the range of _m . Each NMOS transistor 5 receives the bit line 1 according to the signal of the corresponding output line.
02 and 103 are electrically connected to the bias circuit 4, or the bit lines 102 and 103 are disconnected from the bias circuit 4.
The circuit voltage of the bias circuit 4 is, for example, 1 to 1.5V.

In the read-only memory of the above embodiment,
When the address information A _m and A _n are input, first, the bit line 1 corresponding to the column address information A _m is selected by the Y selector 6.
01 is selected and connected to the input of the sense amplifier 7.
At the same time, the output lines XP ₀ , X of the decoder circuit 9
Of P ₁ and XP ₂ , the output line for controlling the NMOS transistor 5 corresponding to the selected one bit line is selected by the decoder circuit 9 and becomes the L level. For this reason,
Bit line selected by the Y selector 6 is disconnected from the bias circuit 4, according to the potential information stored in the memory cell 1 selected by the address information A _m and A _n,
The voltage changes. This voltage change is caused by the sense amplifier 7
Is read by. On the other hand, not selected by the column address information A _m bit lines except for the bit line corresponding to a common output line of the decoder circuit 9 is connected to a constant bias circuit 4, the voltage level V _P of the bias circuit 4 Maintained. The timing of this signal change is shown in FIG.

In FIG. 3, the column address information A _m of the read-only memory sequentially changes to address 0, address 1, and address 2. Accordingly, the various lines P ₀ , P ₁ , P ₂ of the decoder are sequentially lowered to the L level, and the bit lines 102, 103 and 104 are sequentially selected by the Y selector. When address 0 is input as the column address information, first, this address 0
The bit line 102 corresponding to is disconnected from the bias circuit. At the same time, the memory cell corresponding to the row selected by the address information A _n is connected to this bit line and its potential information is given to the bit line 102. The information given to the bit line 102 is "1" in this example, so that the bit line 102 is maintained at the potential V _P and no voltage change occurs. This information is selected by the Y selector and then read by the sense amplifier. Therefore, the output of the sense amplifier is at H level.

Next, when the address 1 is input as the column address information A _m , the decoder output P ₁ and the bit line 103 are similarly selected, and the information "0" of the selected memory cell is given to the bit line. To be As a result, the potential of the bit line 103 drops from V _P by about 20 to 30 mV. The information "0" of the memory cell is read by the sense amplifier due to the potential decrease of the bit line 103, and the output of the sense amplifier is reduced to the L level. Next, when the address 2 is input as the column address information A _m , the decoder output P ₂ and the bit line 104 are similarly selected, and the address 0
As in the case of, the potential change does not occur in the bit line because the information of the memory cell is "1", and the potential information of the memory cell is detected by the output H level of the sense amplifier.

As described above, the potential of the unselected bit line is always maintained at the voltage level V _P of the bias circuit. Therefore, when the bit line is selected, the potential of the bit line is the previous potential level V _P. Either it remains at _P , or the voltage level slightly drops according to the memory cell information. Therefore, the time required from the address change to the reading of the sense amplifier is sufficient only for the slight potential change of 20 to 30 mV on the bit line. Further, unlike the prior art, the procedure of temporarily charging up after the address change can be omitted, and no time is required for this. Particularly, in a large-capacity read-only memory, since the parasitic resistance and parasitic capacitance of the bit line increase, much time is required for charge-up, and the effect of shortening time by omitting charge-up is great.
In addition, a complicated timing design for generating the precharge timing signal is also unnecessary.

FIG. 2 is a block diagram showing the configuration of a read-only memory according to the second embodiment of the present invention. In this embodiment, the bit lines 102 and 103 are composed of a first group of NMOS transistors 5 corresponding to each bit line and a second group of NMOS transistors 8 corresponding to a bit line group 30 composed of four bit lines. By the series switch circuit,
The bias circuit 4 is electrically connected. The NMOS transistors 5 of the first group are controlled by the output of the first decoder circuit 9, and the NMOS transistors 8 of the second group are controlled by the output of the second decoder circuit 10. The addresses A ₀ and A _{1 of the} lower bits of the column address information are input to the first decoder circuit 9, and
The decoder circuit 10 among the column address information, the address A2～A _n upper bits is inputted. Other configurations are shown in FIG.
The configuration is the same as that of the first embodiment, and the description thereof is omitted.

In the embodiment of FIG. 2, one NMOS transistor 8 in the second group is connected to the second decoder circuit 10.
Of the output lines L _{0 to} L _i of which are turned on by being controlled by the output line which becomes H level. Also, one NMOS transistor 5 in the first group is
The decoder circuit 9 is turned off by being controlled by the output line selected from the output lines XP _{0 to} XP ₄ and having the L level. Therefore, the specific bit line selected by the column address information is disconnected from the bias circuit 4, while the other three bit lines belonging to the same group as the specific bit line are electrically connected to the bias circuit 4, and All bit lines belonging to the other group are disconnected from the bias circuit 4.

In a read-only memory, memory cells are generally accessed in the order of consecutive addresses.
By maintaining the bit lines at the H level for each group as described above, the bit lines maintained at the H level are sequentially selected. Therefore, as in the first embodiment, the selected bit line is maintained at a predetermined potential before that, and the selected bit line does not need to be charged up, so that the access time can be shortened. On the other hand, the number of bit lines connected to the bias circuit 4 can be limited by the configuration in which the bit lines belonging to another group are not connected to the bias circuit 4. Therefore, the current consumption of the bias circuit 4 can be reduced as compared with the first embodiment.

As shown in each of the above embodiments, in the read-only memory of the present invention, the bit lines not selected by the column address information are always maintained at the H level so that the bit lines selected by the column address information are Since it is not necessary to charge up the memory cell, it is possible to speed up the access to the memory cell regardless of the size of the parasitic resistance and the parasitic capacitance of the bit line.

The configurations of the above embodiments are merely examples, and various modifications and changes can be made from the configurations of the above embodiments within the scope of the present invention.

[0026]

As described above, according to the read-only memory of the present invention, at least a part of the bit lines not selected by the column address information is always maintained at the predetermined potential, so that the charge-up after the bit line selection is performed. By eliminating the need for a complicated timing design and enabling high-speed access to the memory cells, the present invention has the remarkable effect of enabling high-speed operation of the read-only memory and simplification of its design. .

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a read-only memory according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a read-only memory according to a second embodiment of the present invention.

3 is a timing diagram of signal changes in the read-only memory of the embodiment of FIG.

FIG. 4 is a block diagram showing a configuration of a conventional read-only memory.

5 is a signal timing diagram in the read-only memory of FIG.

[Description of Reference Signs] 1 memory cell 2 X decoder 3 timing generation circuit 4 bias circuit 5, 8 NMOS transistor 6 Y selector 7 sense amplifier 9, 10 decoder circuit 11 precharge circuit 20 parasitic resistance 22 parasitic capacitance 30 bit line group 100 memory Cell array 101 Word line 102 to 104 Bit line

Claims (3)

[Claims] 1. A plurality of memory cells arranged in row and column directions for respectively storing predetermined potential information, a word line selecting a memory cell group arranged in the row direction, and arranged in the column direction. A bit line which is arranged corresponding to the memory cell group, reads the potential information from the memory cells of the memory cell group, a row decoder which selects the word line based on the row address information, and a column decoder based on the column address information. A column selector that selects the bit line, a sense amplifier that reads out the potential of the bit line selected by the column selector, and a bias unit that constantly maintains at least one group of bit lines not selected by the column selector at a predetermined potential. A read-only memory characterized by comprising. 2. The bias means comprises a decoder for decoding the column address information, and a switch means which is controlled by an output of the decoder and opens a bit line selected by the row selector and a bias power supply line. The read-only memory according to claim 1, wherein the read-only memory is configured. 3. The read-only memory according to claim 1, wherein the bias means maintains only one group adjacent to the bit line selected by the row selector at the predetermined potential.