JPH07106922A - Oscillator circuit - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to provide an oscillation circuit that changes only the duty number while keeping the optimum oscillation frequency when transferring display data to a display element. In the display transfer clock switching circuit 8, duty number data of input display data is latched at a latch timing of a latch set signal input to a clock terminal CK input to a latch circuit 11 and output to a decoder 12. Then, the signal is decoded and a switching signal is output to the switches S1 to Sn for switching, and the resistance element R
1 to Rn are selectively connected to the capacitor C, and a circuit constant KCR that determines the duty number of the basic clock signal CK0 is set. With this basic clock signal CK0, the display transfer clock oscillator generates a display transfer clock signal in which only the duty number m is changed while the frame frequency F remains constant, and the display data of the segment number n is transferred to the display unit. It

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillator circuit suitable for a liquid crystal display device or the like, and more particularly to an oscillator circuit for setting a transfer frequency when transferring display data.

[0002]

2. Description of the Related Art Conventionally, in a liquid crystal display unit provided in a small electronic computer, data stored in a ROM and key information to be input are converted into display data by a control unit and once written in a display RAM, The display transfer clock signal is again transferred to the liquid crystal display unit via the control unit to display the liquid crystal display element with the light on and off.

Since such a liquid crystal display element requires lighting information for the number of segments × the number of commons because of its structure, for example, as shown in FIG. 5, a display data storage area for storing display data in a RAM is provided. If the number of segments is n (for example, 8 bits) × duty number m (corresponding to the number of commons, for example, 4) and the display data storage area is 3
Display data for 2 bits can be stored.

Therefore, the number of display data can be changed by increasing or decreasing the number of duty m when storing in the display data storage area, and it can be applied to a liquid crystal panel having a large number of display dots to a liquid crystal panel having a small number of display dots. It had the advantage of being able to.

Further, the display transfer clock signal generated when the number of display data is changed has the frequency of the display transfer clock signal as "f" and the transfer time for transferring n pieces of display data as "f". If T ", duty number m
= 4, the frame frequency F is "1 / 4T", and the signal waveform is as shown in FIG.

[0006]

However, in such a conventional display transfer clock signal generated when changing the number of display data, when the duty number m is changed, the following problem occurs. There was a problem.

That is, the frame frequency F when the duty number m = 4 is "1 / 4T", but the frame frequency F when the duty number m = 5 is "1 / 5T".
T "and the signal waveform is as shown in Fig. 7. If" 1 / 4T "is the optimum frame frequency F of the liquid crystal display panel.
If the duty factor m is simply changed while keeping the transfer time T constant, the frame frequency F corresponding to the changed duty factor m will be the optimum frame frequency F0.
There was a problem that it came off.

It is an object of the present invention to provide an oscillation circuit which changes the duty factor only while keeping the optimum oscillation frequency when transferring display data to a display element.

[0009]

The invention according to claim 1 is
In an oscillation circuit that sets the oscillation frequency of a transfer signal that transfers a series of display data in frame units to a plurality of display elements arranged in segment units, the oscillation frequency in the transfer signal is fixed and the The duty number setting means provided with a plurality of duty number setting elements for changing the setting, and the duty number setting element provided in the duty number setting means are selected according to the display content displayed on the display element to select the duty of the transfer signal. Control means for changing only the number and changing the display data transfer pattern,
It is characterized by having.

Further, in this case, as described in claim 2, the duty number setting means is provided with a capacitor and a resistor as the duty number setting element, and the control means selects the combination of the capacitor and the resistor. It is more effective to change the duty factor according to.

[0011]

According to the invention described in claim 1, in the oscillation circuit for setting the oscillation frequency of the transfer signal for transferring a series of display data in frame units to a plurality of display elements arranged in segment units, A plurality of duty number setting elements for changing the setting of the duty number while keeping the oscillation frequency of the transfer signal constant is provided by the duty number setting means, and the duty number setting means is provided to the duty number setting means according to the display content displayed on the display element by the control means. The provided duty factor setting element is selected, only the duty factor of the transfer signal is changed, and the transfer pattern of the display data is changed.

Further, in this case, as described in claim 2, the duty number setting means is provided with a capacitor and a resistor as the duty number setting element, and the control means selects a combination of the capacitor and the resistor. As a result, the duty number is changed.

Therefore, it is possible to generate a transfer signal for transferring the display data for which only the duty number is changed while maintaining the optimum frame frequency of the segment type display element in accordance with the setting change of the duty number data, and an external circuit is generated. It is possible to cope with variations of the segment-type display element without adding and to improve the display quality.

[0014]

EXAMPLES Examples will be described below with reference to FIGS.

1 to 4 are views showing an embodiment of a small electronic computer to which the oscillator circuit of the present invention is applied.

First, the structure will be described.

FIG. 1 is a block diagram of a small electronic computer 1. In this figure, the small computer 1 includes a display unit 2, a key input unit 3, a ROM 4, a RAM 5, and a control unit 6.
It is composed of

The display section 2 is composed of a liquid crystal display panel in which a plurality of liquid crystal display elements each composed of a segment electrode and a common electrode are arranged, and each liquid crystal display element is displayed by display data transferred from the control section 6 by a transfer clock signal. Is turned on or off to display numbers or calculated characters.

The key input unit 3 is composed of numeric keys, addition / subtraction / multiplication / division keys, etc., and outputs each key input instruction to the control unit 6.

A ROM (Read Only Memory) 4 stores a calculation processing program executed by the controller 6.
A RAM (Random Access Memory) 5 is a numerical data storage area for temporarily storing numerical data when the control unit 6 is performing a calculation process, and, as shown in FIG. A display data storage area for storing display data is formed according to the number of segment electrodes and the number of common electrodes of the liquid crystal display element structure.

The control unit 6 includes a CPU (Central Processing).
Unit) and the like, and internally includes a display transfer clock oscillator 7 and a display transfer clock switching circuit 8. The control unit 6 executes calculation processing according to the calculation processing program stored in the ROM 4 according to the numerical data and calculation instructions input from the key input unit 3, and displays the input numerical data, calculation formula, and calculation result. After the data is generated and temporarily stored in the display data storage area in the RAM 5, the stored display data is read out, and the display transfer clock signal generated by the display transfer clock oscillator 7 and the display transfer clock switching circuit 8 is used. It is transferred to the display unit 2 and displayed.

The display transfer clock oscillator 7 generates a display transfer clock signal having a frame frequency F on the basis of the basic clock signal CK0 input from the display transfer clock switching circuit 8 and uses the display transfer clock signal to generate a frame. By outputting the display data to the display unit 2 in units, a drive voltage is supplied to the common electrode and the segment electrode of each liquid crystal display element in the display unit 2 to turn on and off the display data to display the display data.

As shown in FIG. 2, the display transfer clock switching circuit 8 latches the latch set signal input to the clock terminal CK by the duty number m data input by the display data generated in the control section 6. A latch circuit 11 that latches at a timing and outputs it to a decoder, and switches S1 to Sn that select the resistance elements R1 to Rn by decoding duty number m data input from the latch circuit 11
Of the switch 12 for outputting a switching signal for switching between the switches S1 to Sn and the switches S1 to Sn for selectively connecting the resistance elements R1 to Rn to the capacitor C by the switching signal output from the decoder 12. A plurality of resistance elements R which are selectively connected to the capacitor C by switching and change the setting of the duty number of the display transfer clock signal in combination with the capacitor C.
1 to Rn, a capacitor C, and a basic clock signal CK0 having an input clock output signal of a duty number m set by a combination of the resistance elements R1 to Rn and the capacitor C.
Is generated and output to the display transfer clock oscillator 7.

In FIG. 1, white arrows connecting the blocks represent data buses, and line arrows represent address buses.

Next, the operation of this embodiment will be described.

First, when the user inputs numerical data and calculation instructions in the key input section 3, the control section 6 generates display data for the input data and stores it in the display data storage area in the RAM 5. To be done. At this time, the display data stored in the display data storage area in the RAM 5, as shown in FIG.
The data structure is stored in accordance with the number of segment electrodes and the number of common electrodes of the liquid crystal display element configuration arranged in.

Next, the display data stored in the display data storage area in the RAM 5 is read out by the control unit 6 and transferred to the display transfer clock oscillator 7 and the display transfer clock switching circuit 8.

In the display transfer clock switching circuit 8, the duty number data of the display data input from the control unit 6 is latched at the latch timing of the latch set signal input to the clock terminal CK input to the latch circuit 11. It is output to the decoder 12. In the decoder 12,
Duty number m data input from the latch circuit 11 is decoded and a switching signal is output to the switches S1 to Sn.

When the switches S1 to Sn are switched by this switching signal, the resistance elements R1 to Rn are selectively connected to the capacitor C, and the circuit constant KCR that determines the duty number of the basic clock signal CK0 is set. .

Next, the duty factor of the clock output signal input to the gate circuit 13 is determined by the determination of the circuit constant KCR, which is output to the display transfer clock oscillator 7 as the basic clock signal CK0. In the display transfer clock oscillator 7, when the basic clock signal CK0 is input from the display transfer clock switching circuit 8, the display transfer clock signal of the frame frequency F is generated based on the basic clock signal CK0. The segment number n data input from the control unit 6 is transferred to the display unit 2 by the display transfer clock signal.

In the display section 2, each liquid crystal display element is turned on or off according to the segment number n data input by the display transfer clock signal from the display transfer clock oscillator 7, and the input numerical data or calculation formula is displayed. To be done.

Thereafter, the control section 6 executes the calculation processing according to the calculation processing program stored in the ROM 4,
When the display data of the calculation result is generated, RA is similarly generated.
After being stored in the display data storage area in M5 and read and transferred to the display transfer clock oscillator 7 and the display transfer clock switching circuit 8, the display transfer clock oscillator 7 and the display transfer clock switch are performed. The display data is transferred to the display unit 2 by the processing in the circuit 8 and the calculation result is displayed.

In the display transfer clock oscillator 7,
For example, when the data of the duty factor m = 4 is input, as shown in FIG. 2, assuming that the switch S1 is turned on and the resistance element R1 is connected to the capacitor C, the transfer time T is It is calculated by the equation (1).

T = n × (1 / f) (1) where n: number of data f: clock frequency for display transfer In this embodiment, a CR oscillation circuit is used, so 1 / f is given by the following equation (2). Required by. 1 / f = KCR (2) However, K: constant C: capacitance value of the capacitor C R: resistance value of the resistance elements R1 to Rn That is, in the present embodiment, the resistance is changed according to the input duty number m data. By switching and connecting the elements R1 to Rn to the capacitor C, the frame frequency f of the display transfer clock signal is kept constant and only the duty number m is changed.

Specifically, when the duty number m = 4,
If the resistance element R1 is selected and a display transfer clock signal having a frame frequency F of 1 / 4T and a transfer time T of n segment data is output as shown in FIG. When m = 5,
By selecting the resistance element R2 of FIG. 2, for example, as shown in FIG. 4, the transfer time T ′ of n segments is transferred.
(However, when T '= 4 / 5T), the display transfer clock signal having the frame frequency F of 1 / 5T' is output.

That is, when the duty number m = 5,
By setting the resistance value of the resistance element R2 so that T ′ = 4 / 5T, the transfer time is changed from T to T ′, and the transfer time of n segment data is shortened.
The frame frequency F is maintained at 1 / 4T.

Therefore, in this embodiment, when the duty number m data is changed, only the duty number m is changed while the frame frequency F of the display transfer clock signal is constant, which is optimum for the liquid crystal display element. Assuming that the frame frequency F0 is 1 / 4T when the duty number m = 4, the transfer pattern of the display data is changed while the optimum frame frequency F0 is maintained.

As a result, in the present embodiment, the display transfer clock switching circuit 8 changes only the duty number m while maintaining the optimum frame frequency F0 in the control unit 6 in response to the setting change of the duty number m data. The transfer clock signal can be generated, it is possible to cope with variations of the liquid crystal display element in the display unit 2 without adding an external circuit, and display quality can be improved.

In the above embodiment, the combination of the capacitor C and the resistance elements R1 to Rn is used to set the duty number m. However, even if other combinations of the oscillation elements are used, the oscillation of the present invention is performed. Of course, it is possible to realize the function of changing the oscillation frequency in the circuit.

Further, the scope of application of the oscillator circuit of the present invention is not limited to the small-sized electronic computer 1 of the above-described embodiment, but can be applied to other electronic devices having a display section using a liquid crystal display element.

[0041]

According to the present invention, it is possible to generate a transfer signal for transferring display data in which only the duty number is changed while maintaining the optimum frame frequency of the segment type display element in accordance with a change in the duty number data setting. Therefore, it is possible to cope with variations of the segment type display element without adding an external circuit, and it is possible to improve the display quality.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a compact electronic computer to which an oscillator circuit of the present invention is applied.

FIG. 2 is a circuit configuration diagram of a display transfer clock switching circuit of FIG.

FIG. 3 is a diagram showing an example of a waveform of a display transfer clock signal generated based on a basic clock signal output from the display transfer clock switching circuit of FIG.

FIG. 4 is a diagram showing another example of the waveform of the display transfer clock signal generated based on the basic clock signal output from the display transfer clock switching circuit of FIG.

FIG. 5 is a diagram showing a configuration of a display data storage area formed in a RAM in a conventional small-sized computer.

FIG. 6 is a diagram showing an example of a waveform of a display transfer clock signal output by a conventional oscillator circuit.

FIG. 7 is a diagram showing another example of the waveform of the display transfer clock signal output from the conventional oscillation circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Small computer 2 Display section 3 Key input section 4 ROM 5 RAM 6 Control section 7 Display transfer clock oscillator 8 Display transfer clock switching circuit 11 Latch circuit 12 Decoder 13 Gate circuit S1 to Sn switch R1 to Rn Resistance element C Capacitor

Claims (2)

[Claims] 1. An oscillating circuit for setting an oscillation frequency of a transfer signal for transferring a series of display data to a plurality of display elements in a frame unit composed of a plurality of duty, wherein the oscillation frequency of the transfer signal is constant. For transferring the duty number setting means provided with a plurality of duty number setting elements for changing the duty number setting, and the duty number setting element provided in the duty number setting means according to the display content displayed on the display element. An oscillation circuit comprising: a control unit that changes only the duty number of a signal and changes a transfer pattern of display data. 2. The duty number setting means includes a capacitor and a resistor as a duty number setting element, and the control means changes the duty number by selecting a combination of the capacitor and the resistor. The oscillator circuit according to claim 1, which is characterized in that.