JPH07106970A - A / D converter - Google Patents

Abstract

(57) [Abstract] [Purpose] To improve the conversion accuracy and arithmetic processing of the A / D converter by reducing or expanding the bits during digital output. [Structure] A triangular wave output circuit 2 that outputs a reference signal, a sample-and-hold circuit 9 that inputs an analog signal, a comparator 4 that compares an analog value with a triangular wave, and a counter 5 that operates with a signal different from the reference signal. To be done. The time length of the comparison result is set to the reset period of the counter 5, and the output of the counter 5 after the count up of the counter 5 is made a digital output. As a result, the digital value can be reduced or expanded by setting the clock for operating the counter 5 to a frequency different from that of the reference signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter,
In particular, the present invention relates to an A / D converter having a function of converting a minute analog signal.

[0002]

2. Description of the Related Art A conventional successive approximation A / D converter will be described in detail with reference to the drawings.

Referring to FIG. 3, which shows a block diagram of an example of a conventional successive approximation A / D converter, an 8-bit A / D converter 300 of this conventional successive approximation A / D converter is shown.
Is a sample-and-hold circuit 39 that receives the analog input VIN, and compares the output 31 of the supplement-and-hold circuit 39 with the analog voltage 32 to convert the analog input V.
A comparator 35 that outputs a "0" level when IN is smaller than the analog voltage 32, a timing counter 38 that sequentially turns on by a counter signal TS given from the outside to output outputs (T1 to Tn), and a timing counter 38.
Of the digital output (R1
.About.Rn) the successive approximation register 37 in which the comparison signal 33 is set to the output Rn which is the MSB and the output (Rn-1) is reset, and the analog output 32 is D / A based on the digital outputs (R1 to Rn). And a D / A converter 36 for conversion.

Next, referring to FIG. 4, which shows a time chart showing the operation of the A / D converter 300 of the conventional 8-bit successive approximation type A / D converter device shown in FIG. The operation will be described.

The analog input VIN is held by the sample-and-hold circuit 39, and the successive approximation register 37
Indicates that only the output Rn, which is the MSB of the output (Rn to R1), is "0", and all the other bits (Rn-1 to R1) are "1".
Initialized to. This initial value is converted into the analog voltage 32 by the D / A converter 36.

The analog input VIN and the analog voltage 32 held in the sample and hold circuit 39 are the comparator 3
5, the analog input VIN is the analog voltage 32
When it is smaller, the output 33 of the comparator 35 becomes "0",
When the analog input VIN is higher than the analog voltage 32, the output 33 of the comparator 35 becomes "1".

The timing counter 38 outputs a count signal T
When S is given from the outside, its output (Tn to T
Although it is sequentially turned on until 1), when the output Tn is turned on first, the output Rn which is the MSB of the successive approximation register 37
At the same time that the comparator output signal 33 is set to
n-1) is reset.

Based on the outputs (Rn to R1) of the successive approximation register 37 in which the output Rn is set, the analog voltage 32
Is generated by the D / A converter 36, and the successive approximation register 3 is generated by the output (Tn-1) of the timing counter 38.
The comparison result signal 33 is set to the output (Rn-1) of 7 and the output (Rn-2) is similarly reset.

Similarly, the outputs (Rn-2 ...
R1) is set and the conversion is completed when the output R1 is set, and the digital output OUT of the A / D converter 300 is output from the successive approximation register 37.

Further, the above-mentioned conventional successive approximation type A for performing high precision A / D conversion when the signal S1 whose amplitude is sufficiently smaller than the analog input range and whose resolution is to be converted more finely is input (see FIG. 5). This will be described with reference to FIG. 6 showing the configuration of the / D conversion device. The offset value removing circuit 61 removes the offset of the analog input VIN having a small amplitude by the external input offset voltage value 63. The signal 65 with the offset removed is A / D by the amplifier 62.
The signal 66 is amplified to the extent that it does not exceed the analog input voltage range of the converter 300, and the amplified signal 66 is output to the A / D converter 300.

The A / D converter 300 outputs digital outputs (Ri to R1) having a wide dynamic range and digital values (Fn to Fn) corresponding to the offset voltage value 63.
m) is externally input, and the offset addition circuit 64 adds digital values (Fn to Fm) to the digital inputs (Ri to R1) to obtain highly accurate digital outputs (Sn to S1).

With the above configuration, the A / D conversion resolution is 8 bits, the accuracy is ± 2 LSB, and the minute amplitude Vs is
When x is in the range of 2 LSB, if the above-mentioned number of bits is i = 2, n = 8, and m = 3, the range (2 LSB) in which accuracy cannot be obtained can be A / D converted, and the effective 8-bit resolution , Accuracy ± 0.5 LSB can be realized.

[0013]

However, since the above conversion flow includes the work of being less than the offset value after A / D conversion, the digital value (Fn to Fm) corresponding to the offset voltage value must be designated. However, although the method by external input is shown above as the designation method, it is necessary to perform the A / D conversion operation of the offset value, resulting in a very complicated A / D conversion operation. Regarding the A / D conversion of the amplitude value, if i = 2, there is a waste of using an A / D converter having an 8-bit configuration for the resolution of 2 bits. In order to save waste, there is a drawback in that an A / D converter having a suitable number of bits must be selected according to the amplitude value.

Further, in signal processing of the digital output value after A / D conversion, considering the processing speed and the circuit configuration, it is preferable that the number of bits is small, but it is effective to reduce the bits to be deleted. Only when the input amplitude is so small that the upper bits do not change. In the conventional technology, unless it is determined whether the small amplitude exists only in the lower bits or the upper bits are propagated, it is possible to reduce the bits without simply deleting the upper bits, but depending on the output range. There was also a problem that linearity disappeared.

[0015]

An A / D converter according to the present invention comprises a triangular wave signal generating circuit for inputting a first clock signal and outputting a triangular wave signal, and an analog input signal for inputting a constant analog value after sampling. A sample-and-hold circuit that outputs an analog signal, a comparator that compares the analog signal with the triangular wave signal, and an output signal of the comparator that is input and that is controlled by a second clock signal to output a digital value. This is a configuration including an A / D converter including one counter circuit.

Further, the A / D conversion device of the present invention may be configured to input a reset signal to the first counter circuit.

Furthermore, the triangular wave signal generation circuit of the A / D conversion device of the present invention comprises a second counter circuit and a D / A.
It can also be configured with a converter.

Furthermore, the A / D conversion device of the present invention is
An offset value removing circuit that removes the offset of the external analog input signal by a predetermined offset voltage value with an external analog input signal of a small amplitude as an input, and an output of the offset value removing circuit is input and amplitude is applied to the analog output. It is also possible to adopt a configuration having an amplitude device for making a signal.

Further, the A / D conversion device of the present invention receives an external analog input signal having a small amplitude as an input, removes the offset of the external analog signal with a predetermined offset voltage value, and outputs the offset value as the analog signal. It is also possible to adopt a configuration having a removal circuit.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An A / D converter according to a first embodiment of the present invention will be described with reference to the drawings.

Referring to FIG. 1 which shows the circuit configuration of the A / D converter of the A / D converter of the first embodiment of the present invention, the A / D converter of this embodiment uses a triangular wave in response to a clock signal CLK1. The triangular wave signal generation circuit 2 that outputs the signal 22, the sample and hold circuit 9 that samples and holds the analog input VIN, and the non-inverting input of the triangular wave 22 that receives the output voltage Vsh of the sample and hold circuit 9.
A which is composed of a comparator 4 which receives at the inverting input and a counter 5 which inputs the comparison result 23 of the comparator 4 as a reset signal and counts by the clock signal CLK2 to output digital outputs (R1 to Rn).
/ D converter 100.

Further, the triangular wave signal generating circuit 2 has a configuration including a counter 1 which operates by a clock signal CLK1 and a D / A converter 3 which converts an output 25 of the counter 1 into an analog signal and outputs an analog voltage triangular wave signal 22. is there.

Next, the operation of the A / D converter according to the first embodiment of the present invention will be described with reference to FIG.

First, the triangular wave signal generation circuit 2 outputs a triangular wave 22 in response to the input of the clock CLK1. An example of the circuit configuration of the triangular wave signal generation circuit 2 is composed of a counter 1 and a D / A converter 3, and the operation of the counter 1 causes the signal 22 to have a waveform that rises from the negative power supply side to the positive power supply side or the positive power supply side. It may be a waveform that drops from the side to the minus power supply skin.

Next, the A / D conversion analog input VIN is held by the sample and hold circuit 9.

Further, the comparator 4 compares the output voltage Vsh of the sample and hold circuit 9 with the triangular wave 22 and outputs the comparison result 23. The comparison result 23 is not a single shot, the comparator 4 is always operating until the analog voltage Vsh is changed by the sample-and-hold circuit 9, and the comparison result 23 outputs "H" only during the time when the analog value is high (FIG. 2). reference).

Next, the operation of the counter 5 will be described. The comparison result 23 is reset signal (“L”) of the counter 5.
Reset signal 2 and another reset signal 2
The counter 5 is counted up and the output of each bit of the counter 5 is regarded as a digital output until the comparison result 23 is reset after the reset of 4 is released from the reset release and the comparison result 23 is reset.

That is, the timing of the reset signal (comparison result 23) of the counter 5 changes depending on the magnitude of the analog input voltage VIN, and as a result, the timing of ending the count-up of the counter 5 changes, and the analog input voltage VI
The counter output corresponding to N is a digital output value (Rn-
It is output as R1).

Next, an A / D converter according to the second embodiment of the present invention will be described.

In the operation of the A / D converter 100 of the A / D converter of the first embodiment of the present invention, the normal clock CL
K2 does not need to be synchronized with the clock CLK1, and if the clock CLK2 has the same frequency as the clock CLK1 and the respective operations of the counters 1 and 5 are the same, the digital output values (Rn to R1) have the same dynamic range as the triangular wave 22. Is output as data.

The frequency of the clock CLK2 is changed to the clock CLK.
When it is faster than 1, the amplitude of the digital output value (Rn to R1) is expanded from the normal level, and when it is slowed, the amplitude of the digital output is reduced. If the reset signal 24 input to the counter 5 is input as a reset signal from the outside in addition to the comparison result signal 23, the offset value of the digital output value can be adjusted.

FIG. 7 is a diagram showing the configuration of the A / D converter of the second embodiment of the present invention, showing an example in which the amplitude of the digital output value is reduced, and FIG. 8 is the A / D shown in FIG. It is the figure which showed the timing when the amplitude of the digital output value of a converter is reduced.

Explaining with reference to FIG. 7, the A / D converter of this embodiment has an offset value removing circuit 11 with an analog input VIN as an input and an offset voltage value 73.
And an amplifier 12 that amplifies the output 75 of the offset removal circuit 11 and supplies it to the input of the sample-and-hold circuit 9 of the A / D converter 100, and the A / D converter 100. The offset removal circuit 11 removes the offset of the analog input VIN having a small amplitude by the offset voltage value 73 of the external input. Offset removed signal 75
Is amplified by the amplifier 12 to an extent not exceeding the analog input voltage range of the A / D converter 100, and the amplified signal Va is input to the A / D converter 100.

Finally, if 8-bit conversion is used to configure the amplitude value of 2 bits and the offset value of 6 bits, the counter 1 of the triangular wave output generation circuit 2 can be configured to have 2 bits, and four values (00 , 01, 10, 11
Then, the comparator 4 compares the analog input Vsh with the four values and inputs the comparison result 23 to the counter 5 as the reset signal Re2. In the counter 5, the reset signal Re1 is externally input at a timing corresponding to the offset voltage in advance and the counter 5 is counted up, and the digital value corresponding to the offset value is obtained by the time immediately before the data of the reset signal Re2 is input. It is designed to be used.

If it takes too long to obtain the offset value and the conversion time cannot be met in time, the frequency of the clock CLK2 of the counter 5 is increased only by the offset value conversion time to shorten the conversion time. Further, in the above method, the outputs of the counter 1 and the counter 5 are both output in 2 bits, but in order to output only the counter 5 in 2 bits, the output 22 of the triangular wave output generation circuit 3 is set to 4 bits.
There is also a method of reducing the digital output value by making not the value output but an output that changes all the given number of bits as shown in FIG. 11 to make the frequency of the clock CLK2 slower than that of the clock CLK1.

Next, an A / D converter according to the third embodiment of the present invention will be described.

In the A / D converter of this embodiment, it is preferable that the number of bits is small in consideration of the processing speed in signal processing of the digital output value after A / D conversion. As an example of expanding the digital value, its configuration is shown in FIG. 9 and its operation timing is shown in FIG.

In the configuration of the A / D converter of this embodiment, the offset is removed, but the minute analog amplitude is directly input to the A / D converter 100 without being amplified, and the A / D converter of the second embodiment is used. Since the structure is the same as that of the / D conversion device, the same reference numerals are given to the constituent elements, and only the drawings are shown, and the detailed description is omitted.

Next, the operation of the A / D converter of this embodiment will be described with reference to FIG. As shown in FIG. 10, the input amplitude is in the range of up to 8 values of the counter 1 which operates with the clock CLK1. After outputting the reset signal Re2 by comparing the triangular wave 22 (analog constant voltage of 8 values) and the analog input voltage Vsh, the clock CLK2 changes at a speed twice that of the clock CLK1, and the counter 5 compares the input amplitude. , And the count-up operation is performed as a double size. As a result, digital output values (Rn to R1)
Has a large amplitude value.

For example, in the case of a small amplitude within the range of 3 bits (8 LSB), the frequency of the clock CLK2 is set to the clock C.
If the frequency of LK1 is doubled, the digital output value becomes 4-bit data, and the digital output value expands. And 4
2 to 1 when you want to enable only the upper 3 bits
The lower bits of the bit are trimmed, and the signal processing is performed thereafter. Therefore, according to the present invention, even if the lower bits are deleted, the linearity is not impaired.

[0041]

As described above, the A / D converter according to the present invention can adjust the A / D conversion of the amplitude value with an appropriate number of bits when the minute amplitude is desired to be converted with high accuracy. It has the effect of not having to do any work. In addition, there is also an effect that it is possible to perform signal processing capable of bit reduction without impairing linearity.

[Brief description of drawings]

FIG. 1 is an A / D converter of the first embodiment of the present invention;
It is a figure which shows the structure of a D converter.

FIG. 2 is a diagram showing a timing of an operation of the A / D converter shown in FIG.

FIG. 3 is a diagram showing a configuration of a conventional successive approximation type A / D conversion device.

FIG. 4 is a diagram showing the operation timing of the conventional successive approximation type A / D conversion shown in FIG.

FIG. 5 is an example of an input signal to be converted.

FIG. 6 is a diagram showing an example of conversion in a conventional A / D conversion device.

FIG. 7 is a diagram showing a configuration of an A / D conversion device according to a second embodiment of the present invention.

8 is a diagram showing an example of operation timing when highly accurate conversion is desired in the A / D conversion device of the present invention shown in FIG.

FIG. 9 is a diagram showing a configuration of an A / D conversion device according to a third embodiment of the present invention.

10 is a diagram showing an example of operation timing in the case of performing bit reduction of an output value in the A / D conversion device of the present invention shown in FIG.

FIG. 11 is a diagram showing another example of the operation timing when highly accurate conversion is desired in the A / D conversion device of the present invention shown in FIG. 7.

[Explanation of symbols]

1,5 Counter 2 Triangle wave signal generation circuit 3,36 D / A converter 4,35 Comparator 9,39 Sample and hold circuit 11,61 Offset removal circuit 12,62 Amplifier 21,31, Vsh sample and hold circuit output 22 Triangle wave 23 comparison result 24, Re1, Re2 reset signal 25 output of counter 1 32 D / A converter output 33 comparator output 37 successive approximation register 38 timing counter 63, 73 offset value 64 offset addition circuit 65, 75 offset removal circuit output 66 amplifier 62 output 100,300 A / D converter CLK1, CLK2 clock Fn-Fm offset value Rn-R1, Sn-S1 digital output Tn-T1 timing counter VIN, Va analog input

Claims (5)

[Claims] 1. A triangular wave signal generation circuit for inputting a first clock signal and outputting a triangular wave signal; a sample and hold circuit for inputting an analog input signal and outputting an analog signal of a constant analog value after sampling; An A / D converter including a comparator for comparing a signal with the triangular wave signal and a first counter circuit for receiving an output signal of the comparator and controlling the digital signal with a second clock signal to output a digital value. An A / D conversion device comprising: 2. The A / D conversion device according to claim 1, wherein a reset signal is input to the first counter circuit. 3. The A / D conversion device according to claim 1, wherein the triangular wave signal generation circuit includes a second counter circuit and a D / A converter. 4. An offset value removing circuit for removing an offset of the external analog input signal according to a predetermined offset voltage value when an external analog input signal having a small amplitude is input, and an output by the offset value removing circuit is inputted and an amplitude is inputted. 4. An A / D conversion device according to claim 1, further comprising an amplitude device whose output is the analog signal. 5. An offset value removing circuit for inputting a small amplitude external analog input signal, removing an offset of the external analog signal by a predetermined offset voltage value, and making an output the analog signal. Item 1. The A / D converter according to item 1, 2 or 3.