JPH07109940B2 - Method for manufacturing multilayer circuit board - Google Patents
Method for manufacturing multilayer circuit boardInfo
- Publication number
- JPH07109940B2 JPH07109940B2 JP2402108A JP40210890A JPH07109940B2 JP H07109940 B2 JPH07109940 B2 JP H07109940B2 JP 2402108 A JP2402108 A JP 2402108A JP 40210890 A JP40210890 A JP 40210890A JP H07109940 B2 JPH07109940 B2 JP H07109940B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- resin
- prepreg
- inner layer
- prepregs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000000034 method Methods 0.000 title claims description 8
- 229920005989 resin Polymers 0.000 claims description 54
- 239000011347 resin Substances 0.000 claims description 54
- 239000000155 melt Substances 0.000 claims description 12
- 239000002648 laminated material Substances 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000011888 foil Substances 0.000 claims description 6
- 239000011521 glass Substances 0.000 description 10
- 239000003822 epoxy resin Substances 0.000 description 9
- 239000004744 fabric Substances 0.000 description 9
- 229920000647 polyepoxide Polymers 0.000 description 9
- 238000000465 moulding Methods 0.000 description 7
- 230000000052 comparative effect Effects 0.000 description 4
- 238000001035 drying Methods 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000009719 polyimide resin Substances 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000010030 laminating Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、インナービアホールを
形成した多層回路板の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer circuit board having inner via holes.
【０００２】[0002]
【従来の技術】近年、プリント回路板について配線の高
密度化、高性能化等の要求が強くなっており、回路の多
層化が進んでいる。このように回路の多層化が進むと、
各層間の回路の接続は回路板の表裏に貫通するスルーホ
ールだけでは確保することができず、インナービアホー
ルによっても接続をおこなう必要がある。2. Description of the Related Art In recent years, there has been an increasing demand for higher density wiring and higher performance of printed circuit boards, and the multilayering of circuits is progressing. In this way, as the number of circuits increases,
The connection of the circuits between the layers cannot be ensured only by the through holes penetrating the front and back of the circuit board, and it is necessary to make the connection also by the inner via holes.
【０００３】図３は多層回路板Ａの一例を示すものであ
り、多層回路板Ａの表裏に貫通するスルーホールＢを設
けると共に内層ＣにインナービアホールＤを設け、スル
ーホールＢの内周に設けたメッキ層Ｇで外層Ｅ及び一部
の内層Ｃに形成した回路Ｆを電気的に導通接続し、また
インナービアホールＤの内周のメッキ層Ｈでこのインナ
ービアホールＤを設けた内層Ｃに形成した回路Ｆ同士を
導通接続するようにしてある。FIG. 3 shows an example of the multilayer circuit board A. Through holes B penetrating the front and back of the multilayer circuit board A are provided, an inner via hole D is provided in an inner layer C, and the inner periphery of the through hole B is provided. The circuit F formed on the outer layer E and part of the inner layer C is electrically connected by the plated layer G, and the inner layer C provided with the inner via hole D is formed by the plated layer H on the inner periphery of the inner via hole D. The circuits F are electrically connected to each other.
【０００４】そして上記のようなインナービアホールを
有する多層回路板の製造は、ビアホール（スルーホール
と称されることもある）を表裏に貫通させて設けた内層
回路板にプリプレグを介して他の内層回路板や外層回路
板、金属箔等の積層材を重ね、これを加熱加圧して多層
成形することによっておこなうことができる。[0006] In order to manufacture the multilayer circuit board having the inner via holes as described above, the inner layer circuit board provided with the via holes (also referred to as through holes) penetrating the front and back sides is provided with another inner layer through the prepreg. It can be performed by stacking laminated materials such as a circuit board, an outer layer circuit board, and a metal foil, and heating and pressing the laminated materials to form a multilayer.
【０００５】[0005]
【発明が解決しようとする課題】しかしこのようにして
多層回路板を製造するにあたって、内層回路板のビアホ
ール内には加熱加圧成形をおこなう際にプリプレグの樹
脂が溶融流動して充填されることになるが、プリプレグ
からビアホールに流れる樹脂量が不足するとビアホール
内に空隙が発生するおそれがある。そしてこのように空
隙が発生すると完成された多層回路板の耐熱性等に問題
が生じるものである。すなわち、多層回路板を製造する
工程で半田付け等の際に高温（約２６０〜３００℃）が
作用することになるが、多層回路板の内部に空隙が存在
するとこの部分でフクレ等の欠陥が生じることになるの
である。However, in manufacturing a multilayer circuit board in this way, the resin of the prepreg is melted and fluidized and filled in the via hole of the inner layer circuit board during heat and pressure molding. However, if the amount of resin flowing from the prepreg into the via hole is insufficient, voids may occur in the via hole. When such voids are generated, a problem occurs in heat resistance and the like of the completed multilayer circuit board. That is, a high temperature (about 260 to 300 ° C.) acts during soldering or the like in the process of manufacturing a multilayer circuit board, but if voids are present inside the multilayer circuit board, defects such as blisters occur at this portion. It will happen.
【０００６】本発明は上記の点に鑑みてなされたもので
あり、耐熱性に優れた多層回路板の製造方法を提供する
ことを目的とするものである。The present invention has been made in view of the above points, and an object thereof is to provide a method for manufacturing a multilayer circuit board having excellent heat resistance.
【０００７】[0007]
【課題を解決するための手段】本発明に係る多層回路板
の製造方法は、ビアホール１を設けた内層回路板２に複
数枚のプリプレグ３を介して他の内層回路板や外層回路
板、金属箔等の積層材４を重ね、これを加熱加圧して多
層成形することによって多層回路板を製造するにあたっ
て、上記複数枚のプリプレグ３のうち内層回路板２に接
するよう配置されるプリプレグ３ａとして、そのレジン
コンテントが他のプリプレグ３ｂよりも高く且つその含
浸樹脂の溶融粘度が他のプリプレグ３ｂよりも小さいも
のを用いることを特徴とするものである。A method for manufacturing a multilayer circuit board according to the present invention comprises an inner circuit board 2 provided with a via hole 1 and another inner circuit board, an outer circuit board, and a metal via a plurality of prepregs 3. When manufacturing a multilayer circuit board by stacking laminated materials 4 such as foils and heating and pressurizing the laminated materials 4, as the prepreg 3a arranged to be in contact with the inner layer circuit board 2 among the plurality of prepregs 3 described above, It is characterized in that a resin whose resin content is higher than that of the other prepreg 3b and whose melt viscosity of the impregnated resin is smaller than that of the other prepreg 3b is used.
【０００８】以下、本発明を詳細に説明する。内層回路
板２としては常法で作成されたものが用いられる。すな
わち、ガラス基材等にエポキシ樹脂やポリイミド樹脂、
トリアジン樹脂等の熱硬化性樹脂を含浸乾燥して調製し
たプリプレグを複数枚重ねると共にその両側に銅箔等の
金属箔を重ねて加熱加圧成形することによって、金属箔
張り積層板を作成し、この金属箔をエッチング加工等し
て表裏面に回路１０の形成をおこなうことによって内層
回路板２を作成することができる。そして本発明ではビ
アホール１を設けた内層回路板２を用いる。ビアホール
１は内層回路板２の表裏に貫通するように形成されてい
るものであり、その内周にはスルーホールメッキ処理に
よってメッキ層１１を設けて表裏の回路１０を導通接続
するようにしてある。The present invention will be described in detail below. As the inner layer circuit board 2, one prepared by a conventional method is used. That is, epoxy resin or polyimide resin on the glass substrate,
By laminating a plurality of prepregs prepared by impregnating and drying a thermosetting resin such as a triazine resin and laminating a metal foil such as a copper foil on both sides of the prepreg and heat-pressing, a metal foil-clad laminate is created. The inner layer circuit board 2 can be formed by forming the circuit 10 on the front and back surfaces of the metal foil by etching or the like. In the present invention, the inner layer circuit board 2 provided with the via hole 1 is used. The via hole 1 is formed so as to penetrate through the front and back surfaces of the inner layer circuit board 2, and a plating layer 11 is provided on the inner periphery by through hole plating to electrically connect the front and back circuits 10. .
【０００９】上記のようにビアホール１を設けた内層回
路板２を用いて多層回路板を製造するにあたっては、図
１に示すように各内層回路板２の表裏両面に複数枚のプ
リプレグ３を重ねると共にこのプリプレグ３を介して積
層材４を重ねる。プリプレグ３としては、ガラス布基材
にエポキシ樹脂やポリイミド樹脂、トリアジン樹脂等の
熱硬化性樹脂を含浸乾燥して作成したものを用いること
ができるが、本発明ではこの複数枚のプリプレグ３のう
ち、内層回路板２に接するよう配置されるプリプレグ３
ａとして、そのレジンコンテントが他のプリプレグ３ｂ
よりも高く且つその含浸樹脂の溶融粘度が他のプリプレ
グ３ｂよりも小さいものを用いるものである。この内層
回路板２に接するよう配置されるプリプレグ３ａをガラ
ス布基材にエポキシ樹脂を含浸乾燥して作成する場合に
は、レジンコンテントを５０〜９０重量％（％と略す）
に設定すると共に、含浸樹脂の溶融粘度が５０〜１００
０ＰＳ（ポイズ：測定温度１３０℃−以下同じ−）にな
るように調整するのがよい。また内層回路板２に接する
よう配置されるプリプレグ３ａをガラス布基材にポリイ
ミド樹脂を含浸乾燥して作成する場合には、レジンコン
テントを５０〜９０％に設定すると共に、含浸樹脂の溶
融粘度が１００〜２０００ＰＳになるように調整するの
がよい。また積層材４としては、他の内層回路板や外層
回路板、銅箔等の金属箔などを用いることができる。When manufacturing a multilayer circuit board using the inner layer circuit board 2 provided with the via holes 1 as described above, a plurality of prepregs 3 are stacked on both front and back surfaces of each inner layer circuit board 2 as shown in FIG. Along with this prepreg 3, the laminated material 4 is stacked. As the prepreg 3, those made by impregnating and drying a glass cloth base material with a thermosetting resin such as an epoxy resin, a polyimide resin, or a triazine resin can be used. In the present invention, among the plurality of prepregs 3, , Prepreg 3 arranged so as to contact the inner circuit board 2
As a, the resin content is another prepreg 3b.
And the melt viscosity of the impregnated resin is smaller than that of the other prepreg 3b. When the prepreg 3a arranged so as to contact the inner layer circuit board 2 is formed by impregnating and drying an epoxy resin on a glass cloth base material, the resin content is 50 to 90% by weight (abbreviated as%).
And the melt viscosity of the impregnated resin is 50-100.
It is preferable to adjust the temperature to 0 PS (poise: measurement temperature 130 ° C.-the same applies hereinafter). When the prepreg 3a arranged so as to be in contact with the inner circuit board 2 is prepared by impregnating and drying a glass cloth base material with a polyimide resin, the resin content is set to 50 to 90%, and the melt viscosity of the impregnating resin is It is better to adjust it to 100 to 2000 PS. As the laminated material 4, other inner layer circuit boards, outer layer circuit boards, metal foils such as copper foils, and the like can be used.
【００１０】そしてこのように内層回路板２に複数枚の
プリプレグ３を介して積層材４を重ねた後に、これを加
熱加圧して多層積層成形することによって、プリプレグ
３によるボンディング層１２で内層回路板２に積層材４
を積層して多層に回路形成をした多層回路板Ａを得るこ
とができるものであり、多層回路板Ａの層内には内層回
路板２に設けたビアホール１でインナービアホールが形
成されるものである。そして図２に示すようにインナー
ビアホールとなるビアホール１内にはプリプレグ３から
流れ出る溶融樹脂が流入し、樹脂５で充填されて埋めら
れるものである。ここで、本発明では、複数枚のプリプ
レグ３のうち内層回路板２に接するよう配置されるプリ
プレグ３ａとして、そのレジンコンテントが他のプリプ
レグ３ｂよりも高く且つその含浸樹脂の溶融粘度が他の
プリプレグ３ｂよりも小さいものを用いているために、
内層回路板２に接するプリプレグ３ａからは多量の樹脂
がビアホール１に供給されることになると共にしかも溶
融粘度の低いこの樹脂は容易に流れてビアホール１内に
流入してビアホール１内に良好に充填されることにな
る。従って、インナービアホールとなるビアホール１の
部分において多層回路板Ａ内に空隙部が生じることを防
ぐことができ、空隙の存在による半田の際のフクレの発
生を防止すると共に耐熱性を高めることができるもので
ある。In this way, after laminating the laminated material 4 on the inner layer circuit board 2 through the plurality of prepregs 3 and heating and pressing the laminated material 4, the inner layer circuit is formed by the bonding layer 12 by the prepreg 3. Laminated material 4 on board 2
It is possible to obtain a multilayer circuit board A in which a plurality of layers are laminated to form a circuit, and the inner via hole is formed in the layer of the multilayer circuit board A by the via hole 1 provided in the inner layer circuit board 2. is there. Then, as shown in FIG. 2, the molten resin flowing out from the prepreg 3 flows into the via hole 1 serving as an inner via hole, and is filled and filled with the resin 5. Here, in the present invention, among the plurality of prepregs 3, the prepreg 3a arranged so as to be in contact with the inner layer circuit board 2 has a resin content higher than that of the other prepreg 3b and a melt viscosity of the impregnated resin of the other prepreg 3a. Since it is smaller than 3b,
A large amount of resin is supplied to the via hole 1 from the prepreg 3a in contact with the inner layer circuit board 2, and this resin having a low melt viscosity easily flows and flows into the via hole 1 to be well filled in the via hole 1. Will be done. Therefore, it is possible to prevent a void portion from being formed in the multilayer circuit board A in the portion of the via hole 1 which is an inner via hole, to prevent generation of blisters during soldering due to the presence of the void and to improve heat resistance. It is a thing.
【００１１】尚、複数枚のプリプレグ３のうち、内層回
路板２に接しないプリプレグ３ｂも内層回路板２に接す
るプリプレグ３ａと同じようにレジンコンテントを高く
すると共に樹脂の溶融粘度を低くすると、各プリプレグ
３の全体において樹脂が流れ易くなってしまい、プリプ
レグ３の四方から樹脂が流出して多層回路板Ａに板厚の
ばらつきが発生することになり、また場合によっては樹
脂の流れが良すぎて成形時に積層の位置ずれ不良が発生
することになるために、本発明では採用することができ
ない。Of the plurality of prepregs 3, the prepreg 3b not in contact with the inner layer circuit board 2 has the same resin content as that of the prepreg 3a in contact with the inner layer circuit board 2 and has a lower resin melt viscosity. The resin easily flows in the entire prepreg 3, the resin flows out from the four sides of the prepreg 3, and the thickness of the multilayer circuit board A varies, and in some cases, the resin flows too well. This method cannot be used in the present invention because the positional deviation of the laminate will occur during molding.
【００１２】[0012]
【実施例】次に、本発明を実施例によって例証する。実施例１ 直径０．９mmのビアホール１を設けたエポキ
シ樹脂系の厚み０．２mmの内層回路板２を用い、図１の
ように、この内層回路板２の表面と裏面にそれぞれ２枚
づつガラス布基材エポキシ樹脂プリプレグ３ａ，３ｂを
重ねると共にさらにその外側に銅箔４を重ねた。ここで
内層回路板２に接するプリプレグ３ａはレジンコンテン
トが７０％、樹脂の溶融粘度が３００ＰＳになるよう設
定し、他方のプリプレグ３ｂはレジンコンテントが５０
％、樹脂の溶融粘度が５００ＰＳになるよう設定した。
そしてこれを１７０℃、３０kg/cm2、９０分の条件で加
熱加圧して多層成形することによって、多層回路板を得
た。The invention will now be illustrated by the examples. Example 1 Using an epoxy resin-based inner layer circuit board 2 having a thickness of 0.2 mm provided with a via hole 1 having a diameter of 0.9 mm, two glass sheets are provided on each of the front surface and the back surface of the inner layer circuit board 2 as shown in FIG. The cloth base epoxy resin prepregs 3a and 3b were stacked, and the copper foil 4 was further stacked on the outer side thereof. Here, the prepreg 3a in contact with the inner layer circuit board 2 is set so that the resin content is 70% and the melt viscosity of the resin is 300 PS, and the other prepreg 3b has the resin content of 50%.
%, And the melt viscosity of the resin was set to 500 PS.
Then, this was heated and pressed under the conditions of 170 ° C., 30 kg / cm 2 and 90 minutes to perform multi-layer molding to obtain a multi-layer circuit board.
【００１３】実施例２ ガラス布基材ポリイミド樹脂プ
リプレグ３ａ，３ｂを用いると共に、内層回路板２に接
するプリプレグ３ａはレジンコンテントが７０％、樹脂
の溶融粘度が１０００ＰＳになるよう設定し、他方のプ
リプレグ３ｂはレジンコンテントが５０％、樹脂の溶融
粘度が１５００ＰＳになるよう設定し、さらに多層成形
条件を２００℃、４０kg/cm2、９０分に設定するように
した他は、実施例１と同様にして多層回路板を得た。 EXAMPLE 2 Glass cloth base polyimide resin prepregs 3a and 3b were used, and the prepreg 3a in contact with the inner layer circuit board 2 was set so that the resin content was 70% and the resin melt viscosity was 1000 PS, and the other prepreg was used. 3b was the same as Example 1 except that the resin content was set to 50%, the melt viscosity of the resin was set to 1500 PS, and the multilayer molding conditions were set to 200 ° C., 40 kg / cm 2 , and 90 minutes. A multilayer circuit board was obtained.
【００１４】実施例３ ガラス布基材エポキシ樹脂プリ
プレグ３ａ，３ｂを用いると共に、内層回路板２に接す
るプリプレグ３ａはレジンコンテントが７０％、樹脂の
溶融粘度が３００ＰＳになるよう設定し、他方のプリプ
レグ３ｂはレジンコンテントが４５％、樹脂の溶融粘度
が１１００ＰＳになるよう設定した他は、実施例１と同
様にして多層回路板を得た。 Example 3 Glass cloth base epoxy resin prepregs 3a and 3b were used, and the prepreg 3a in contact with the inner layer circuit board 2 was set so that the resin content was 70% and the resin melt viscosity was 300 PS, and the other prepreg was used. A multilayer circuit board was obtained in the same manner as in Example 1 except that 3b had a resin content of 45% and a resin melt viscosity of 1100 PS.
【００１５】比較例１ ガラス布基材エポキシ樹脂プリ
プレグ３ａ，３ｂを用いると共に、両方のプリプレグ３
ａ，３ｂをともにレジンコンテントが７０％、樹脂の溶
融粘度が３００ＰＳになるよう設定した他は、実施例１
と同様にした。このものでは成形の際に積層ずれが生じ
て多層回路板を得ることができなかった。比較例２ ガラス布基材エポキシ樹脂プリプレグ３ａ，
３ｂを用いると共に、両方のプリプレグ３ａ，３ｂをと
もにレジンコンテントが４５％、樹脂の溶融粘度が８０
０ＰＳになるよう設定した他は、実施例１と同様にして
多層回路板を得た。 Comparative Example 1 Glass cloth base epoxy resin prepregs 3a and 3b were used, and both prepregs 3 were used.
Example 1 except that both a and 3b were set so that the resin content was 70% and the melt viscosity of the resin was 300 PS
Same as. With this product, a multi-layer circuit board could not be obtained due to a stacking deviation during molding. Comparative Example 2 Glass cloth-based epoxy resin prepreg 3a,
3b is used, and both prepregs 3a and 3b have a resin content of 45% and a resin melt viscosity of 80%.
A multilayer circuit board was obtained in the same manner as in Example 1 except that the setting was 0 PS.
【００１６】比較例３ ガラス布基材エポキシ樹脂プリ
プレグ３ａ，３ｂを用いると共に、内層回路板２に接す
るプリプレグ３ａはレジンコンテントが５０％、樹脂の
溶融粘度が５００ＰＳになるよう設定し、他方のプリプ
レグ３ｂはレジンコンテントが７０％、樹脂の溶融粘度
が３００ＰＳになるよう設定した他は、実施例１と同様
にして多層回路板を得た。 Comparative Example 3 Glass cloth base epoxy resin prepregs 3a and 3b were used, and the prepreg 3a in contact with the inner layer circuit board 2 was set so that the resin content was 50% and the resin melt viscosity was 500 PS, and the other prepreg was used. 3b was obtained in the same manner as in Example 1 except that the resin content was 70% and the melt viscosity of the resin was 300 PS.
【００１７】上記のように実施例１〜３及び比較例１〜
３で得た多層回路板について、オーブン耐熱温度、板厚
のばらつきを測定すると共に半田工程でのフクレ不良の
発生率を調べた。結果を次表に示す。As described above, Examples 1 to 3 and Comparative Examples 1 to 1
Regarding the multilayer circuit board obtained in No. 3, the oven heat resistance temperature and the variation in board thickness were measured, and the occurrence rate of blistering defects in the soldering process was examined. The results are shown in the table below.
【００１８】[0018]
【表１】 [Table 1]
【００１９】表の結果にみられるように、内層回路板２
に接するよう配置されるプリプレグ３ａとして、そのレ
ジンコンテントが他のプリプレグ３ｂよりも高く且つそ
の含浸樹脂の溶融粘度が他のプリプレグ３ｂよりも小さ
いものを用いるようにした各実施例のものでは、耐熱性
が向上していると共にフクレ不良の発生率が低いことが
確認される。As shown in the results of the table, the inner layer circuit board 2
As the prepreg 3a arranged so as to come into contact with the prepreg 3a, the resin content of which is higher than that of the other prepreg 3b and the melt viscosity of the impregnated resin is smaller than that of the other prepreg 3b is used. It is confirmed that the property is improved and the occurrence rate of blister defects is low.
【００２０】[0020]
【発明の効果】上記のように本発明は、内層回路板に接
するよう配置されるプリプレグとして、そのレジンコン
テントが他のプリプレグよりも高く且つその含浸樹脂の
溶融粘度が他のプリプレグよりも小さいものを用いるよ
うにしたので、内層回路板に接するプリプレグからは多
量の樹脂がビアホールに供給されることになると共にし
かも溶融粘度の低いこの樹脂は容易に流れてビアホール
内に流入してビアホール内に良好に充填されることにな
り、インナービアホールとなるビアホールの部分におい
て多層回路板内に空隙部が生じることを防ぐことがで
き、空隙の存在による半田の際のフクレの発生を防止す
ると共に耐熱性を高めることができるものである。As described above, the present invention has a resin content higher than that of the other prepregs and a melt viscosity of the impregnated resin smaller than that of the other prepregs, as the prepreg arranged so as to be in contact with the inner layer circuit board. Since a large amount of resin is supplied to the via hole from the prepreg in contact with the inner layer circuit board, this resin with a low melt viscosity easily flows and flows into the via hole and is good in the via hole. In this way, it is possible to prevent the formation of voids in the multilayer circuit board at the via holes that will be the inner via holes, prevent the occurrence of blisters during soldering due to the presence of voids, and improve heat resistance. It can be raised.
【図１】本発明の一実施例の多層成形の前の概略断面図
である。FIG. 1 is a schematic cross-sectional view before multilayer molding according to an embodiment of the present invention.
【図２】本発明の一実施例の多層成形後の概略断面図で
ある。FIG. 2 is a schematic cross-sectional view after multilayer molding according to an embodiment of the present invention.
【図３】多層回路板の断面図である。FIG. 3 is a cross-sectional view of a multilayer circuit board.
【符号の説明】 １ ビアホール ２ 内層回路板 ３ プリプレグ ４ 積層材[Explanation of symbols] 1 via hole 2 inner layer circuit board 3 prepreg 4 laminated material
Claims (1)
のプリプレグを介して他の内層回路板や外層回路板、金
属箔等の積層材を重ね、これを加熱加圧して多層成形す
ることによって多層回路板を製造するにあたって、上記
複数枚のプリプレグのうち内層回路板に接するよう配置
されるプリプレグとして、そのレジンコンテントが他の
プリプレグよりも高く且つその含浸樹脂の溶融粘度が他
のプリプレグよりも小さいものを用いることを特徴とす
る多層回路板の製造方法。1. A laminated material such as another inner layer circuit board, an outer layer circuit board, and a metal foil is laminated on an inner layer circuit board provided with a via hole via a plurality of prepregs, and this is heated and pressed to form a multilayer. In manufacturing a multilayer circuit board, as the prepreg arranged so as to contact the inner layer circuit board among the plurality of prepregs, the resin content is higher than other prepregs and the melt viscosity of the impregnated resin is higher than other prepregs. A method for manufacturing a multilayer circuit board, characterized in that a small one is used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2402108A JPH07109940B2 (en) | 1990-12-14 | 1990-12-14 | Method for manufacturing multilayer circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2402108A JPH07109940B2 (en) | 1990-12-14 | 1990-12-14 | Method for manufacturing multilayer circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04215496A JPH04215496A (en) | 1992-08-06 |
| JPH07109940B2 true JPH07109940B2 (en) | 1995-11-22 |
Family
ID=18511922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2402108A Expired - Fee Related JPH07109940B2 (en) | 1990-12-14 | 1990-12-14 | Method for manufacturing multilayer circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07109940B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007095795A (en) * | 2005-09-27 | 2007-04-12 | Matsushita Electric Works Ltd | Manufacturing method of multilayer printed wiring board |
| JP5982760B2 (en) * | 2011-09-07 | 2016-08-31 | 富士通株式会社 | Electronic device and manufacturing method thereof |
| CN116156741B (en) * | 2023-04-23 | 2023-07-04 | 南昌龙旗信息技术有限公司 | Printed circuit board and mobile device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54163360A (en) * | 1978-06-16 | 1979-12-25 | Hitachi Ltd | Method of producing multiilayer printed circuit board |
| JPS54163359A (en) * | 1978-06-16 | 1979-12-25 | Hitachi Ltd | Method of producing multiilayer printed circuit board |
| JPS56144957A (en) * | 1980-04-15 | 1981-11-11 | Matsushita Electric Works Ltd | Manufacture of laminated board for multilayer printed wiring |
-
1990
- 1990-12-14 JP JP2402108A patent/JPH07109940B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04215496A (en) | 1992-08-06 |
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