JPH07112008B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a second semiconductor device that is self-aligned with the first conductor pattern in the vicinity of the first conductor pattern. To an improved method for forming a contact window of a conductor pattern.

Dynamic random access memory (D-RAM)
In MOS memories such as those mentioned above, large scale and high integration is a major proposition, and in order to achieve this, a manufacturing method capable of further reducing the cell area is strongly demanded.

[Conventional technology]

Figure 5 shows the original 1-transistor / 1-capacitor structure D-
It is a schematic side sectional view showing a RAM cell (for two cells).

In the figure, 1 is a p-type silicon substrate, 2 is a field oxide film, 3 is a gate oxide film, and 4a, 4b, 4c and 4d are gate electrodes (word lines) made of the first-layer polycrystalline silicon layer PA, 5
Is an n ⁺ type drain region, 6a and 6b are n ⁺ type source regions, 7 is a lower insulating film, 8 is a contact window, 9a and 9b are the first capacitor electrodes made of the second polycrystalline silicon layer PB, 10 Is a drain electrode made of the second-layer polycrystalline silicon layer PB, 11 is a dielectric layer (capacitor film), and 12 is a third-layer polycrystalline silicon layer.
Second capacitor electrode made of PC, 13 is upper insulating film, 14
Indicates drain wiring (bit wiring), and C ₁ and C ₂ indicate first and second cells.

In this initial structure, as is clear from the figure, the contact windows 8 of the drain region 5 and the drain electrode 10, and the source regions 6a and 6b and the first capacitor electrodes 9a and 9b are mask-matched to the lower insulating film 7. Was formed by.

Therefore, it is necessary to form the source / drain regions 5, 6a, 6b wide in view of the dimensional margin for absorbing the mask alignment error, which makes it difficult to improve the degree of integration.

Therefore, a structure has been conventionally provided in which the contact windows for the source and drain are formed by self-aligning with the gate electrode (word line), thereby reducing the cell area and achieving high integration.

FIG. 6 is a schematic side sectional view showing a one-transistor / one-capacitor memory cell having such a contact window self-alignment structure, and each reference numeral in the drawing indicates the same object as that in FIG.

Conventionally, the contact window self-aligned with the gate electrode in the above structure has been formed by the method shown in the process cross-sectional views of FIGS. 7A to 7E.

That is, first, as shown in FIG. 7A, for example, a field oxide film 2 is selectively formed on a p-type silicon substrate 1 by a normal selective oxidation method or the like, and is defined by the field oxide film 2. After the gate oxide film 3 is formed on the substrate surface by thermal oxidation as usual, chemical vapor deposition (CV) is performed on the substrate.
The first-layer polycrystalline silicon layer PA is formed by the D) method, and then the first silicon dioxide (Si) having a thickness of, for example, about 2000 to 3000 Å is formed on the polycrystalline silicon layer PA by the CVD method.
O ₂ ) The lower insulating film 7a is formed.

Then, patterning is performed by a normal photolithography technique to form gate electrodes (word lines) 4a, 4b, 4c made of PA and having a first SiO ₂ lower insulating film 7a on the upper portion as shown in FIG. 7B. , 4d are formed, and then ion implantation of impurities is performed using the gate electrode as a mask as usual to form n ⁺ type drain regions 5 and n ⁺ type source regions 6a, 6b.

Next, as shown in FIG. 7C, a second SiO ₂ lower insulating film 7b having a thickness of, for example, about 2000 to 3000 Å is formed on the substrate by the CVD method.

Then, the second SiO ₂ lower insulating film 7b is drained from the upper surface by a dry ion etching method that is predominant in the direction perpendicular to the substrate surface, for example, reactive ion etching method using carbon tetrafluoride (CF ₄ ) gas. Source regions 5 and 6a, 6
By uniformly etching the surface b until it is exposed, the second SiO ₂ lower insulating film 7b on the side surfaces of the gate electrodes 4a, 4b, 4c, 4d, etc. is formed on the gate electrodes 4a, 4b, 4c, 4d as shown in FIG. 7 (d). This is a method of forming the contact windows 8 of the drain and source regions 5, 6a, 6b which are self-aligned via the contact windows 8. (In FIG. 6, the first SiO ₂ lower insulating film 7a and the second SiO ₂ lower insulating film 7b are
Are integrated into a SiO ₂ lower insulating film 7. [Problems to be solved by the invention] However, in the above-mentioned conventional method, the upper edge portion UE of the contact window 8, that is, the gate electrodes 4a, 4b, 4c, 4d, etc. is subjected to reactive ion etching for forming the contact window 8. Since the second SiO ₂ lower insulating film 7b on the shoulder of the substrate tends to be etched excessively and the corners are cut away, the distribution of the etching rate in the substrate surface and the substrate surface of the second SiO ₂ lower insulating film 7b If there is a large variation in thickness inside the gate electrodes 4a, 4b,
Shoulders such as 4c and 4d are exposed, and the gate electrode is short-circuited with conductive layers such as capacitor electrodes 9a and 9b and drain electrode 10 formed on the contact window 8 as shown in FIG. 7 (e). There was a problem that occurred.

[Means for solving problems]

The above problem can be solved by providing a second conductor pattern which is adjacent to the first conductor pattern mounted on the semiconductor substrate via the first insulating film and is in contact with the surface of the semiconductor substrate. A step of forming a second insulating film on the semiconductor substrate on which the first conductor pattern is mounted, a step of forming a polycrystalline silicon film on the second insulating film, and a step of forming a polycrystalline silicon film on the polycrystalline silicon film. A step of forming an oxidation-resistant mask film, a step of filling a concave portion around the first conductor pattern having the oxidation-resistant mask film with an etching mask layer, and a step of forming the oxidation-resistant mask film using the etching mask layer as a mask A step of selectively removing exposed portions, a step of removing the etching mask layer, and a polycrystalline silicon film on the first conductor pattern halfway through the remaining oxidation resistant mask film as a mask. The step of forming a film, A step of selectively removing the oxidation-resistant mask film and the polycrystalline silicon film on the concave portion using the silicon oxide film as a mask, and using the residual polycrystalline silicon film on the first conductor pattern as a mask, with respect to the substrate surface The second insulating film and the first insulating film in the recess are formed by a vertically dominant etching means.
The method for manufacturing a semiconductor device according to the present invention, which comprises the steps of selectively removing the insulating film of FIG. 6 to expose the semiconductor substrate surface in the recess, and forming a second conductor pattern in contact with the exposed semiconductor substrate surface. Achieved by

[Operation] That is, in the method of the present invention, a heterogeneous film having etching selectivity with respect to the insulating film is selectively formed on the gate electrode and the insulating film on the side surface thereof, and self-aligned with the gate electrode having the insulating film on the side surface. The reactive ion etching for forming the contact window is not performed for the entire surface etching but for the selective etching by using the different film as a mask, and the etching rate and the film thickness of the insulating film are slightly varied. Also, since the upper edge of the insulating film on the side surface of the gate electrode is completely protected by the different film and the upper edge of the insulating film is not scraped off on the side surface of the gate electrode, it is formed on the contact window. A short circuit between the capacitor electrode or drain electrode and the gate electrode is completely prevented.

〔Example〕

Hereinafter, the present invention will be specifically described by way of examples with reference to the drawings.

FIGS. 1A to 1I are process cross-sectional views showing an embodiment for forming a one-transistor / one-capacitor type memory cell,
FIG. 2 shows a 1-transistor 1 formed by the above embodiment.
FIG. 3 is a schematic plan view of a capacitor-type memory cell, FIG. 3 is a schematic plan view of a ROM cell, and FIGS. 4A to 4I are process cross-sectional views showing one embodiment in forming the ROM cell.

The same object is denoted by the same symbol throughout all the drawings, and the same object in FIG. 7 is also denoted by the same symbol.

Referring to FIG. 1 (a), when forming a one-transistor / one-capacitor type memory cell by the method of the present invention, a field oxide film 2 is selectively formed on a p-type silicon substrate 1 by an ordinary method, A gate oxide film 3 is formed on the cell formation region defined and exposed by the field oxide film 2, and is made of the first-layer polycrystalline silicon layer PA and extends from above the gate oxide film 3 onto the field oxide film 2. After forming the gate electrodes (word lines) 4a, 4b, 4c, 4d to be used, the n ⁺ type drain region 5 and the n ⁺ type source regions 6a, 6b are formed using the gate electrodes as a mask.

See FIG. 1 (b). Then, a SiO ₂ lower insulating film 7 having a thickness of, for example, about 2000 to 3000 Å is formed on the substrate by a CVD method, and then a CVD method having a thickness of about 1000 to 2000 Å is also formed thereon. A polycrystalline silicon layer 21 is formed, and then an oxidation resistant mask film, for example, a silicon nitride (Si ₃ N ₄ ) film 22 having a thickness of about 500 to 1000Å is formed on the substrate by the same CVD method, and then a gate is formed on the substrate. An etching mask layer, for example, a resist film 23 having a thickness that fills the recesses between is spin-coated.

See FIG. 1 (c). Then, the resist film is processed by oxygen (O ₂ ) plasma treatment or the like.
23 is etched away from the upper surface until the Si ₃ N ₄ film 22 is exposed, and recesses 24a, 24b, 24c, 24d, between the gate electrodes (word lines) are formed.
24e is selectively filled with the resist film 23.

See FIG. 1 (d). Then, using the resist film 23 in the recess as a mask, for example, CF
Gate electrode 4 by dry etching using ₄ + O ₂ gas
a, 4b, 4c, 4d and the Si ₃ N ₄ film 22 exposed on the upper part of the SiO ₂ lower insulating film 7 on the side surfaces thereof are selectively removed to selectively remove the polycrystalline silicon layer 21 in the regions. To expose.

See FIG. 1 (e). Then, the exposed surface of the polycrystalline silicon layer 21 exposed by thermal oxidation using the Si ₃ N ₄ film 22 as a mask has a thickness of 500 to 1 selectively.
The SiO ₂ film 25 of about 000Å is formed. At this time, the thickness of the residual polycrystalline silicon layer in this region is about 1700 to 500Å.

See FIG. 1 (f). Then, using the SiO ₂ film 25 as a mask, the Si ₃ N ₄ film 22 in the recesses 24a, 24b, 24c, 24d and 24e is removed by a phosphoric acid boiling method or the like, and then the substrate surface is removed. In the recess, the polycrystalline silicon layer 21 exposed in the recess is selectively removed by reactive ion etching using a gas having vertical anisotropy, such as carbon tetrachloride (CCl ₄ ). The SiO ₂ lower insulating film 7 is selectively exposed.

At this time, the gate electrodes 4a, 4b, 4c, 4d and the side surfaces of the SiO
_{2 The} polycrystalline silicon layer 21 remains on the lower insulating film 7.

See FIG. 1 (g). Then, for example, CF ₄ having anisotropy perpendicular to the substrate surface is used.
The SiO ₂ film exposed on the substrate surface is etched by reactive ion etching with + O ₂ gas. By the etching, the gate electrodes 4a, 4b, 4c, 4d and the SiO ₂ film 25 on the side surface of the SiO ₂ insulating film 7 are removed, and the polycrystalline silicon layer 21 existing in the region is used as a mask to remove the gap between the gate electrodes. The SiO ₂ lower insulating film 7 and the gate oxide film 3 on the bottoms of the recesses 24a, 24b, 24c, 24d, 24e are selectively removed, and the contact windows 8 exposing the drain regions 5 and the source regions 6a, 6b on the bottoms of the recesses are formed. Is formed.

Since the polycrystalline silicon layer 21 remains on the gate electrodes 4a, 4b, 4c, 4d and the upper part of the SiO ₂ lower insulating film 7 on the side surfaces thereof as described above, the upper edge portion of the contact window 8 during the etching. That is, the SiO ₂ lower insulating film 7 on the shoulder of the gate electrode
Is not scraped off.

Then, as shown in FIG. 1 (h), a second polycrystalline silicon layer PB having a thickness of about 4000 to 5000 Å is formed on the substrate as usual, and the polycrystalline silicon layer PB and the lower portion thereof are formed on the polycrystalline silicon layer PB by a normal photolithography technique. The remaining polycrystalline silicon layer 21 is patterned to form a first polycrystalline silicon layer PB of the second layer, which is in contact with the source regions 6a and 6b in the contact window 8 portion.
A drain electrode 10 is formed in contact with the capacitor electrodes 9a and 9b and the drain region 5.

As shown in FIG. 1 (i), a dielectric film (capacitor film) 11 is formed on a capacitor electrode by a conventional thermal oxidation method, and a third polycrystalline silicon layer of about 4000 to 5000 Å is formed on the substrate by a CVD method. A second capacitor electrode 12 made of PC is formed, an opening 26 for exposing the drain electrode 10 is formed in the second capacitor electrode 12 by a normal photolithography technique, and then phosphosilicate glass is formed on the substrate. An interlayer insulating film 13 made of (PSG) or the like is formed, a contact window 27 exposing the drain electrode 10 is formed in the interlayer insulating film 13, and the drain electrode 10 is formed on the interlayer insulating film 13 at the contact window 27. A bit wiring 14 made of aluminum or the like is formed in contact with the.

Then, although not shown, a cover insulating film and the like are formed to complete a memory cell having a one-transistor / one-capacitor structure.

FIG. 2 is a schematic plan view showing a memory cell (a region for two cells) having the one-transistor / one-capacitor structure of the above-described embodiment. Each object is indicated by the same reference numeral as in FIG.

According to the above embodiment, the D-RA having the one-transistor / one-capacitor structure in which the drain contact window and the capacitor contact window are formed in the gate electrode by self-alignment.
When forming the M cell, the upper edge portion of the lower layer insulating film formed on the surface of the gate electrode, that is, the shoulder portion of the gate electrode is not damaged.

Therefore, it is possible to prevent the breakdown voltage and the short circuit between the gate electrode and the drain electrode or the capacitor electrode formed by overlapping the gate electrode.

The method of the present invention is not limited to the above-described embodiment, and is used when the drain contact (bit line contact window) in the ROM cell as shown in the schematic plan view of FIG. 3 is formed on the gate electrode (word line) by self-alignment. Also applies to In the figure, 2 is a field oxide film, 4a and 4b are gate electrodes (word lines), 5 is a drain region, 6a and 6b are source regions, 108 is a drain / contact window (bit line contact window), and 14 is a bit wiring. Indicates.

An embodiment will be described below with reference to process sectional views shown in FIGS.

Refer to FIG. 4 (a). For example, gate electrodes 4a and 4b having a gate oxide film 3 at the bottom are formed on a p-type silicon substrate 1 by a conventional method, and the n ⁺ -type drain region 5 and The n ⁺ type source regions 6a and 6b are formed, and then the SiO ₂ lower layer insulating film 7 having a thickness of about 2000 to 3000 Å is formed on the substrate as in the above-mentioned embodiment, and a multi-layer having a thickness of about 1000 to 2000 Å is formed thereon. A crystalline silicon layer 21 is formed, and a Si ₃ N ₄ film having a thickness of 500 to 1000Å is formed on the crystalline silicon layer 21.
22 is formed, a positive resist film 123 is formed on the substrate to a thickness that fills the recess 24 between the gate electrodes, and a photomask 28 is formed.
Is used to perform exposure. L indicates light for exposure.

Next, as shown in FIG. 4B, development is performed to selectively remove the resist film 123 in regions other than the upper portion of the recess 24.

4C, the unexposed resist film 123 remaining on the upper portion of the recess 24 is etched with a developing solution or the like to selectively remove the portions other than those filled in the recess 24 between the gate electrodes. .

Then, referring to FIG. 4 (d), Si ₃ N is exposed in a place other than the recess 24 by dry etching means using the resist film 123 as a mask.
_{4 The} film 22 is selectively removed.

After that, the resist film 123 is removed, and then thermal oxidation is performed on the surface of the exposed polycrystalline silicon layer 21 to form a SiO film having a thickness of about 500 to 1000Å.
_{2 The} film 25 is formed. At this time, the surface of the polycrystalline silicon layer in the recess 24 is not oxidized because it is covered with the Si ₃ N ₄ film 22.

See FIG. 4 (f). Then, the Si ₃ N ₄ film 22 in the recess 24 is formed by a method such as using a phosphoric acid foil.
Is removed to expose the polycrystalline silicon layer 21 in the recess 24.

Next, referring to FIG. 4 (g), using the SiO ₂ film 25 as a mask, the polycrystalline silicon layer 21 in the recess 24 is selectively removed by reactive ion etching with CCl ₄ gas, and the SiO ₂ lower layer in the recess 24 is removed. The insulating film 7 is exposed.

See FIG. 4 (h). Then, for example, CF ₄ having anisotropy perpendicular to the substrate surface is used.
The SiO ₂ film exposed on the surface of the substrate is etched by reactive ion etching using + H ₂ gas. As a result of the etching, SiO _{2 on the} gate electrodes 4a, 4b and the side surfaces thereof is
The SiO ₂ film 25 on the lower insulating film 7 is removed, and the SiO ₂ lower insulating film 7 on the bottom surface of the recess 24 between the gate electrodes is selectively removed by using the polycrystalline silicon layer 21 existing in the region as a mask. A contact window 108 exposing the drain region 5 is formed on the bottom surface of the recess.

Since the polycrystalline silicon layer 21 remains on the gate electrodes 4a and 4b and on the SiO ₂ insulating film 7 on the side surfaces thereof, the upper edge portion of the contact window 108, that is, the shoulder portion of the gate electrode on the concave portion side is etched during the etching. The SiO ₂ lower insulating film 7 is not scraped off.

See FIG. 4 (i). Then, a wiring material layer is formed on the substrate by a usual method, and the polycrystalline silicon layer 21 is formed by a usual lithography technique.
Is removed, an interlayer insulating film 13 made of PSG or the like is formed on the substrate, a large contact window 27 exposing the contact window 108 and its peripheral portion is formed in the interlayer insulating film 13, and then a normal contact is formed. By the method, the bit wiring 14 connected to the drain region 5 through the contact windows 27 and 108 is formed on the interlayer insulating film 13.

Also in this embodiment, in the etching for forming the contact window shown in FIG. 4 (g), as described above, Si on the upper edge portion of the contact window 108, that is, on the recess side shoulder portion of the gate electrodes 4a and 4b is used.
Since there is no possibility that O ₂ lower insulating film 7 is scraped, the contact window 108 gate electrode 4a on, 4b overlap with the bit line 14 which is formed with the gate electrode 4a, breakdown voltage and short circuit or the like between 4b It will not cause any problems.

〔The invention's effect〕

As described above, according to the present invention, it is possible to form a contact window having a high dielectric strength with respect to a word line by self-alignment with the word line, and a highly integrated D-RAM is provided.
Reliability and manufacturing yield of semiconductor memory devices such as ROM and ROM can be improved.

[Brief description of drawings]

FIGS. 1 (a) to 1 (i) are process cross-sectional views showing an embodiment for forming a one-transistor / one-capacitor type memory cell, and FIG. 2 is a one-transistor / one-transistor formed by the above embodiment.
FIG. 3 is a schematic plan view of a capacitor-type memory cell, FIG. 3 is a schematic plan view of a ROM cell, and FIGS. 4A to 4I are process cross-sectional views showing an embodiment for forming the ROM cell. The figure shows the original 1-transistor / 1-capacitor structure D
-Schematic side sectional view showing a RAM cell, Fig. 6 is a schematic side sectional view showing a conventional one-transistor / one-capacitor type memory cell having a contact window self-alignment structure, and Figs. FIG. 6 is a process cross-sectional view showing the manufacturing method of FIG. In the figure, 4a, 4b, 4c and 4d are gate electrodes (word lines), 5 is a drain region, 6a and 6b are source regions, 7 is a silicon dioxide insulating film, 8 is a contact window, 9a and 9b are first capacitors. Electrode, 10 drain electrode, 21 polycrystalline silicon layer, 22 silicon nitride film, 23 resist film, 24a, 24b, 24c, 24d, 24e
Is a recess between the gate electrodes, and 25 is a silicon dioxide film.

Claims (1)

[Claims] 1. When providing a second conductor pattern adjacent to a first conductor pattern mounted on a semiconductor substrate via a first insulating film and in contact with the surface of the semiconductor substrate, the first conductor pattern is provided. Second on the semiconductor substrate on which the conductor pattern of
A step of forming an insulating film, a step of forming a polycrystalline silicon film on the second insulating film, a step of forming an oxidation resistant mask film on the polycrystalline silicon film, and a step of forming the oxidation resistant mask film. 1. A step of filling a concave portion around the conductor pattern of No. 1 with an etching mask layer, a step of selectively removing exposed portions of the oxidation resistant mask film by using the etching mask layer as a mask, and a step of removing the etching mask layer And a step of using the remaining oxidation-resistant mask film as a mask to form the polycrystalline silicon film on the first conductor pattern halfway into a silicon oxide film, and using the silicon oxide film as a mask, the acid resistance on the recesses. Selectively removing the patterned mask film and the polycrystalline silicon film, and using the residual polycrystalline silicon film on the first conductor pattern as a mask, the recess is formed by a predominant etching means in a direction perpendicular to the substrate surface. A step of selectively removing the second insulating film and the first insulating film in the inside to expose the semiconductor substrate surface in the recess, and a step of forming a second conductor pattern in contact with the exposed semiconductor substrate surface. A method of manufacturing a semiconductor device, comprising: