JPH07118701B2 - Delay insertion / removal circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to control of writing and reading of a temporary memory circuit, and more particularly to a delay inserting / removing circuit for preventing duplication or loss of data when the writing and reading phases are asynchronous.

[0002]

2. Description of the Related Art A conventional delay insertion / removal circuit prepares two types of a write start signal with no delay and a write start signal with a delay and selects a write start signal outside a write inhibit area. It was

[0003]

In this conventional delay insertion / removal circuit, if the write control signal rises just before the write-prohibited area, delay insertion / removal may occur during operation, resulting in duplication or loss of data. There was a problem. The present invention has been made to solve such a problem, and an object thereof is to obtain a delay insertion / removal circuit that prevents slippage due to delay insertion / removal during operation.

[0004]

SUMMARY OF THE INVENTION A delay insertion / removal circuit according to the present invention selects a delay circuit for delaying a write start signal, and a write start signal delayed by the write start signal and the delay circuit. A first selection circuit, a write inhibit signal creation circuit that inputs a read start signal and a clock signal, and creates a first write inhibit signal and a second write inhibit signal, and a first write inhibit signal creation circuit from the write inhibit signal creation circuit. A second selection circuit that selects and outputs one of the write-inhibit signal and the second write-inhibit signal by a reset signal, and the output signal of the first selection circuit and the output signal of the second selection circuit are matched. A match detection circuit for detecting and a selection control signal generation circuit for outputting a selection control signal for selecting the output of the first selection circuit according to the match result output signal of the match detection circuit. It is obtain things. Also write
The inhibit signal generation circuit is used to write to the memory circuit.
Signal and the read start signal do not approach each other
A first write inhibit signal having a minimum time width of
Add a specified margin to this first write inhibit signal
A second write inhibit signal having a different time width
It is a thing.

[0005]

According to the present invention, two kinds of control signals having different write inhibit widths are prepared, delay control is performed by a wide control signal at the time of reset, and delay control is performed by a narrow control signal during operation. Try to take it off. It should be noted that the prohibited width of the write prohibition control signal having a narrow width is a minimum width or more for preventing frequent occurrence of slip due to phase fluctuation.

[0006]

The present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.
In FIG. 1, 1 is a delay circuit for delaying the write start signal a, 2 is a selection circuit for selecting the write start signal a and the write start signal delayed by the delay circuit 1, and 3 is a read start signal b. And a clock signal c to input a write inhibit signal g and a write inhibit signal h, and a write inhibit signal generation circuit 4 generates the write inhibit signal g and the write inhibit signal h from the write inhibit signal generation circuit 3 by a reset signal d. A selection circuit for selecting and outputting one, 5 is a coincidence detection circuit for detecting coincidence between the selection signal f which is the output signal of the selection circuit 2 and the selection signal i which is the output signal of the selection circuit 4, and 6 is this coincidence detection circuit 5 is a selection control signal generation circuit that outputs a selection control signal k that selects the output of the selection circuit 2 according to the result output j that is the coincidence result output signal of 5. FIG. 2 is a time chart used to explain the operation of FIG. In FIG. 2, the same reference numerals as those in FIG. 1 indicate corresponding parts.

Next, the operation of the embodiment shown in FIG. 1 will be described with reference to FIG. First, the input write start signal a
Is delayed by the delay circuit 1 and is output to the selection circuit 2 as an output signal e. In the selection circuit 2, one of the write start signal a and the output signal e from the delay circuit 2 is selected by the selection control signal k from the selection control signal generation circuit 6 and output to the coincidence detection circuit 5 as a selection signal f. The write inhibit signal creation circuit 3 creates a write inhibit signal g and a write inhibit signal h by the input read start signal b and clock signal c. This write inhibit signal g
Is a prohibition region of at least a minimum for not reading the data twice or reading the data before writing due to the approach of the write start signal a and the read start signal b. This signal is a signal obtained by adding more than the relative variation amount of the write phase to the read phase in operation to the inhibit signal g.

Next, the selection circuit 4 selects the write inhibit signal g from the write inhibit signal generating circuit 3 at the time of reset by the input reset signal d, and writes from the write inhibit signal generating circuit 3 at times other than reset. The prohibition signal h is selected and output as the selection signal i to the coincidence detection circuit 5. In the coincidence detection circuit 5, it is determined whether the selection signal f from the selection circuit 2 coincides with the prohibited area of the selection signal i from the selection circuit 4 and the result is output to the selection control signal generation circuit 6 as a result output signal j. To do. The selection control signal generation circuit 6 inverts the selection control signal k to the selection circuit 2 when the result output signal j from the coincidence detection circuit 5 matches, and holds it when they do not match.

[0009]

As described above, according to the present invention, two kinds of control signals having different write-inhibit widths are prepared, and a wide control signal is used for delay insertion / removal at the time of resetting. Since the delay insertion / removal is performed by the narrow control signal, there is an effect that it is possible to prevent data duplication or loss due to the delay insertion / removal during operation.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a time chart used to explain the operation of FIG.

[Explanation of symbols]

 1 delay circuit 2 selection circuit 3 write inhibit signal creation circuit 4 selection circuit 5 match detection circuit 6 selection control signal creation circuit

Claims (2)

[Claims] 1. A delay circuit for delaying a write start signal, a first select circuit for selecting the write start signal and the write start signal delayed by the delay circuit, a read start signal and a clock signal. To generate a first write inhibit signal and a second write inhibit signal, and a reset signal for the first write inhibit signal and the second write inhibit signal from the write inhibit signal producing circuit. A second selection circuit that selects and outputs one of them, a match detection circuit that detects a match between the output signal of the first selection circuit and the output signal of the second selection circuit, and the match detection circuit. A delay insertion / removal circuit comprising a selection control signal generation circuit for outputting a selection control signal for selecting an output of the first selection circuit according to a result output signal. 2. The write inhibit signal creation according to claim 1.
The circuit is a write start signal to the memory circuit and read
Minimum of the range that does not cause erroneous reading due to proximity to the start signal
A first write inhibit signal having a time width and this first write
Has a time width that is a specified margin added to the burn-in prohibition signal
And a second write inhibit signal for
Delay insertion and removal circuit.