JPH07123094A - Buffer control circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] Control the buffer at high speed without stopping the writing and reading operations of the buffer. A buffer control circuit includes a write pointer 21 that controls a write address of a buffer memory, a read pointer 22 that controls a read address of a buffer memory, and a selector that outputs either the output of the write pointer 21 or a specific fixed address. 23, a flag determination circuit 24 for determining the empty / closed state of the buffer memory, and a selector 25 for selecting and outputting either the output cell from the buffer memory or the empty cell.
When using one address of the buffer memory as the discard address and discarding the cell, write the cell to be discarded to the discard address, discard without stopping the memory write operation, and there is no cell to be read in the buffer memory. Is
An empty cell is output without stopping the read operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM switch buffer control circuit for switching information in cell units.

[0002]

2. Description of the Related Art An ATM switch determines whether to write data in a buffer memory according to information in a header portion added to an ATM cell. Such a conventional example,
There is JP-A-3-3448. In the buffer control circuit of the present invention, the write operation is stopped by stopping the clock supply to the buffer when the write is not performed according to the validity indication bit of the header section added to the ATM cell. The same applies to the read operation.

[0003]

Since the buffer memory used in the present invention operates in synchronization with the write clock (WC) and the read clock (RC), writing and reading are performed at the rising edge of these clocks. Take action. Therefore, by fixing each clock to "0", the write and read operations can be stopped.

In the conventional buffer control circuit, the write enable (WE) is obtained by taking the logical product of the write clock (WC) and the write enable (WE) and the read clock (RC) and the read enable (RE).
When the read enable (RE) is "0", the write clock (WC) and the read clock (RC) are "0".
It was fixed to.

This method can be applied when the cycle of the address and cell data is longer than the cycle of the clock. However, when the address and data cycles are shortened to be the same as the clock cycle due to the increase in the speed of the ATM switch as a whole, the control of the empty and closed states of the buffer becomes complicated, and the clock, write enable, and Since the read enable changes at the same time, a hazard may occur and a malfunction may occur.

An object of the present invention is to enable a buffer control operation in the case where the data and the clock have the same cycle, and thereby realize a high speed operation.

[0007]

In order to achieve the above object, in the present invention, instead of stopping the write and read operations, the clock is always input to the buffer memory and any specific address of the buffer memory is used as a dummy address. When an invalid cell is input or when the buffer is closed, the cell is discarded by writing the cell to the dummy address. In addition, a counter for counting the number of valid cells in the buffer is provided to detect the vacancy and blockage of the buffer.

[0008]

The invalid cell is written to the dummy address without stopping the write clock and the read clock, so that the invalid cell can be discarded while the clock is always input to the buffer memory. Further, by providing a counter that counts valid cells in the buffer, it is possible to detect the vacancy and clogging of the buffer at the same cycle as the clock. As a result, the buffer memory can be controlled at high speed, and it is possible to prevent cell discard in the buffer due to overwriting of cells when the buffer overflows.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of a buffer memory for storing cells and a buffer control circuit.

The buffer control circuit 2 includes a write pointer 21 for designating a write address, a read pointer 22 for designating a read address, a selector 23 for selecting and outputting either the write pointer or a dummy address for cell discard, and buffer control. From a flag determination circuit 24 that receives a write enable and a read enable input to the circuit and determines whether the buffer memory is empty or full, and a selector 25 that selects and outputs either an output cell from the buffer memory or an empty cell. Composed.

At the same time that the cell is input to the terminal DI of the buffer memory 1, the write enable generated according to the information of the header portion added to the cell is input to the terminal WE of the flag determination circuit 24. The write enable of a cell is valid when "1" and invalid when "0".

The flag determination circuit 24 puts "1" at the terminal WE.
When it is determined that the buffer memory 1 is not closed, the write pointer 21 and the terminal S1 of the selector 23 are output with "1" indicating validity.

The write pointer 21 counts up one by one each time "1" is input, and holds the address value while "0" is input. The value of the write pointer is output to the selector 23.

When "1" is input to the terminal S1, the selector 23 selects the write address output from the write pointer 21 and outputs it to the terminal WA of the buffer memory 1. When the signal input to the terminal S1 is "0", the cell input to the terminal DI of the buffer memory 1 is regarded as invalid and a dummy address (for example, the highest address of the buffer memory 1) is selected. Output to the terminal WA. The buffer memory 1 writes the cell input from the terminal DI to the write address input from the terminal WA in synchronization with the write clock input to the terminal WC. As a result, the invalid cell is written to the dummy address and discarded.

The read enable input to the terminal RE of the flag determination circuit 24 is valid when "1" and invalid when "0". The flag determination circuit 24 has "1" at the terminal RE.
Is input and it is determined that there is a valid cell in the buffer, the read pointer 22 from the terminal Q2 and the selector 2
5 outputs "1" to the terminal S2.

The read pointer 22 counts up one by one each time "1" is input and holds the counted value while "0" is input. The counted value is output as a read address. The buffer memory 1 outputs the cell of the read address input from the terminal RA from the terminal DO in synchronization with the read clock input to the terminal RC.

When "1" is input to the terminal S2, the selector 25 selects the cell output from the terminal DO of the buffer memory 1 and outputs it. When the signal input to the terminal S2 is "0", the cell output from the terminal DO of the buffer memory 1 is regarded as invalid, and an empty cell is selected and output.

FIG. 2 shows an embodiment of the flag judgment circuit 24. The flag determination circuit 24 detects a block state of the buffer memory 1 from the values of the cell counter 241 and the cell counter 241 that count the number of cells in the buffer.
42, a vacancy detection 243 for detecting a vacant state, and an operation mode determination 244 for controlling these.

The cell counter 241 has an operation mode determination 2
It operates by the signal input from 44 and constantly counts the number of valid cells stored in the buffer memory 1. When "1" is input to the terminal U, the cell counter 241 counts up one by one, and when "1" is input to the terminal D, it counts down one by one, and when both are "0", the counted value is held. To do.

The blockage detection 242 is performed by the terminal Q of the cell counter.
When the value output from the buffer memory 1 becomes equal to the capacity of the buffer memory 1, “1” is output to the terminal F of the operation mode determination 244.

The vacancy detection 243 is performed by the terminal Q of the cell counter.
When the value output from is 0, the operation mode is determined.
"1" is output to the terminal E of 4.

The operation mode determination 244 is such that when "0" is input to both terminals F and E, and when "0" indicating invalidity is input to both terminals WE and RE, terminal Q is detected.
“0” is output from 1, Q2, Q3 and Q4. Terminal W
When "1" is input to E, "1" is input from terminals Q1 and Q3.
Is output, and “1” is input to the terminal U of the cell counter 241. When "1" is input to the terminal RE, the terminal Q2
Then, “1” is output from Q4 and “1” is input to the terminal D of the cell counter 241. When "1" is input to both the terminals WE and RE, "1" is output from the terminals Q1 and Q2, and the buffer memory 1 simultaneously writes and reads valid cells. The cell counter 241 retains the value.

When "1" is input to the terminal F, "0" is output from the terminals Q1 and Q3 regardless of the write enable. When "1" is input to the terminal RE, the terminals Q2 and Q4 output "1".

When "1" is input to the terminal E, "0" is output from the terminals Q2 and Q4 regardless of the read enable. When "1" is input to the terminal WE, "1" is output from the terminals Q1 and Q3.

FIG. 3 shows an embodiment for realizing the operation mode determination 244 of FIG.
41, 4442, 2443, 2444, and four AND elements 2445, 2446, 2447, 2448 are configured by combination logic.

FIG. 4 is a truth table for the operation mode determination 244.

FIG. 5 shows an embodiment of a switch system to which the buffer control circuit of the present invention is applied.

The switch system comprises a buffer memory 1-
1-1-n, buffer control circuits 2-1 to 2-n, data multiplexing 3, address filter 4, P / S 5-1 to 5-n,
Composed of. The cells input from the m lines are multiplexed by the data multiplexing 3, and the n buffer memories 1-1 to 1-1.
The information of the header portion added to the cell 1-n and added to the cell is input to the address filter 4. In the address filter 4, a write enable that selects the buffer memory in which the valid input cell is to be written is generated,
One of the terminals WE of the buffer control circuits 2-1 to 2-n
Output to. The buffer control circuits 2-1 to 2-n have terminals W
According to the write enable input to E, the address number at which the cell is to be written is output to the terminal WA of the buffer memory, and the buffer memories 1-1 to 1-n write the cell input from the terminal DI to that address. The read enable is provided at the terminals RE of the buffer control circuits 2-1 to 2-n at regular intervals in accordance with the output timing to the output line.
Entered in. When the read enable is input, the buffer control circuits 2-1 to 2-n output the address number of the cell to be read to the terminal RA of the buffer memory. In the buffer memories 1-1 to 1-n, the cell stored at the address input from the terminal RA is output from the terminal DO. The output cell is returned to the original form before input by P / S5-1 to 5-n and output from each line.

6 and 7 show another embodiment of the buffer control circuit 2.

Empty detection 24 in the flag determination circuit 24
3 outputs "1" to the terminal E of the operation mode determination 244 and the terminal L of the read pointer 22 when the value output from the terminal Q of the cell counter 241 becomes "0". When “1” is input to the terminal L of the read pointer 22 in the buffer control circuit 2, the value of the write pointer 21 input from the terminal DT is loaded, so that the write pointer 21, the read pointer 22 and the cell counter 241 are loaded.
Synchronize with.

[0031]

According to the buffer control circuit of the present invention, instead of stopping the write and read operations, any specific address of the buffer memory is used as a dummy address, and the dummy write and dummy read operations are performed to perform the write and read operations. Invalid cells can be discarded while the read clock is always input to the buffer memory. Further, since the operation of the buffer memory is controlled without stopping the clock, it is possible to prevent the occurrence of a hazard and the malfunction of the buffer memory when stopping the clock. Therefore, the clock and data cycle of the memory peripheral circuit can be speeded up, and it is possible to prevent the necessary data in the memory from being overwritten when the buffer memory is in the closed state.

Further, by counting the number of cells in the buffer memory, it is possible to easily make a fragment in a free state and a closed state.

When the buffer memory is empty, the value of the write pointer is loaded into the read pointer to synchronize with the cell counter, since all the addresses of the buffer memory are used evenly, all bits of the memory are used. However, it is possible to detect bit errors evenly.

[Brief description of drawings]

FIG. 1 is a block diagram of a buffer control circuit of an ATM switch showing an embodiment of the present invention.

FIG. 2 is a block diagram of an embodiment of a flag determination circuit in the buffer control circuit of FIG.

3 is a circuit diagram of an embodiment of operation mode determination in the flag determination circuit of FIG.

FIG. 4 is an explanatory diagram of an operation truth value for operation mode determination in the flag determination circuit of FIG.

FIG. 5 is a block diagram of an ATM switch to which the buffer control circuit of the present invention is applied.

FIG. 6 is a block diagram of a buffer control circuit of an ATM switch showing an embodiment of the present invention.

7 is a block diagram of an embodiment of a flag determination circuit in the buffer control circuit of FIG.

[Explanation of symbols]

1 ... Buffer memory, 2 ... Buffer control circuit, 21 ... Write pointer, 22 ... Read pointer, 23, 25
... selector, 24 ... flag determination circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kenichi Asano 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Hitate Cho-LS Engineering Co., Ltd. (72) Inventor Masaru Nakamura Kokubunji, Tokyo 1-280, Higashi-Kengokubo, Ichi, Central Research Laboratory, Hitachi, Ltd. (72) Inventor Toshihiko Fujita, 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Stock company Hitachi Information & Communication Division

Claims (4)

[Claims] 1. A buffer control circuit of an ATM switch for exchanging communication information between a plurality of incoming lines and a plurality of outgoing lines based on the information of the header section by using a fixed-length cell composed of a header section and an information section, A write pointer that controls a write address of a buffer memory that stores cells, a read pointer that controls a read address of the buffer memory, and a first selector that outputs either the output of the write pointer or a specific fixed address. A buffer determining circuit that determines a free / empty state of the buffer memory and controls operations of the write pointer and the read pointer, and controls the write and read operations of the buffer memory. Use the specific fixed address of memory as a dummy address for discarding Buffer control circuit and writes the cell to be discarded to the dummy address. 2. The method according to claim 1, wherein a second selector for outputting either the output of the buffer memory or the vacant cell of a specific pattern is provided to read when there is no cell to output in the buffer memory. A buffer control circuit that outputs the empty cell when enable indicates invalid. 3. A cell counter for counting the number of cells stored in the buffer memory is provided in the flag determination circuit, and a free / closed state of the buffer memory is determined by the cell counter. Buffer control circuit that judges by value. 4. The synchronization of the cell counter with the write pointer and the read pointer by loading the value of the write pointer into the read pointer when there is no cell to be output in the buffer memory. A buffer control circuit provided with a means for taking.