JPH07128462A - Logic regulation circuit and electronic clock - Google Patents

Abstract

(57) [Summary] [Purpose] No need for complicated control circuits or adjustment of load capacitance,
A logic slowdown circuit with small slowdown resolution can be realized without changing the slowdown range. [Structure] A logic slow-and-fast circuit, an oscillation means 101 for outputting a reference clock, a logic slow-and-quick data input means 108 for inputting slow-and-fast data, and a logic slow-and-fast data input means 108.
Of the reference clock to perform logical slowing / fastening in half cycle units of the reference clock, a frequency dividing means 103 for inputting and dividing the clock output from the half-period logical slowing / fastening means 102, and logic. It has a one-cycle logical slowing / fastening means 106 for inputting an output signal of the slowing / fastening data input means 108 and performing logical slowing / fastening in units of one cycle of a clock output by the half-cycle logical slowing / fastening means 102.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic regulation circuit for adjusting the rate of an electronic timepiece, an electronic timepiece having a logic regulation circuit,
And an electronic device with a logic regulation circuit.

[0002]

2. Description of the Related Art Conventionally, a method has been used in which a circuit as shown in FIG. 2 is used to perform logical regulation on a cycle-by-cycle basis of a reference clock. The operation will be briefly described with reference to FIG. 2 and FIG. 3 showing a timing chart.

A reference clock a output from the oscillator circuit 201 is a T-type flip-flop (hereinafter referred to as TFF) 20.
It is inputted to the frequency dividing circuit composed of 2 to 205 and is frequency-divided. When the slow-moving operation is not performed, the frequency is accurately divided into 1/2 as in the sections A to B in FIG. When the slow start / stop command b rises at a certain timing, the slow start / start operation is started. Normally, the slow start command b starts at a cycle of 10 seconds. The gradual start command b is input to the data of the latch circuit 208 which uses the normal rotation (hereinafter referred to as Q) output signal of the TFF 204 in the frequency division stage as a clock signal. Inversion of the latch circuit 208 (hereinafter Q
The output signal c (referred to as X) falls in synchronization with the rising of the Q output signal of the TFF 204. The QX output signal c of the latch circuit 208 is input to the NOR circuit 209. NO
The R circuit 209 is a reference clock a and the Q of the latch circuit 208 is Q.
The X output signal c and the Q output signal d of the D-type flip-flop (hereinafter referred to as DFF) 210 are input.

As can be seen from the timing of FIG. 3C, T
When the Q output signal of the FF204 rises, the level of the reference clock a is "L", and the Q output signal level of the DFF210 is also "L". Therefore, the output e of the NOR circuit 209 is output.
Rises in synchronization with the fall of the QX output signal c of the latch circuit 208.

Output e of NOR circuit 209 and slow / fast data f
Further, the outputs of the AND circuits 206 and 207 having g as an input are connected to the preset inputs of the TFFs 202 and 203. When the level of the slow / fast data f is “H” and the level of g is “L”, the output signal h of the AND circuit 206
Becomes "H", and the level of the output signal i of the AND circuit 207 remains "L". Therefore, TFF2
02 is preset and the Q output signal is forcibly set to "H".

Next, when the reference clock a rises at the timing of FIG. 3D, the NOR circuit 209 output e falls. The data input is fixed to the "H" level, and the Q output signal d of the DFF 210 clocked by the NOR circuit 209 output e is synchronized with the falling edge of the NOR circuit 209 output e until the DFF 210 is reset after that.
H "is maintained. Therefore, NOR circuit 209 output e
Also maintains the "L" level.

When the output e of the NOR circuit 209 becomes "L" level, the preset of the TFF 202 is canceled. Since the reference clock a is continuously input to the TFF 202, FIG.
At the timing of E, the Q output signal of the TFF 202 is subjected to the usual 1/2 frequency division after falling.

By this series of operations, one section of the "L" level of the Q output signal of the TFF 202, that is, one cycle of the reference clock a, is omitted. TFF20
From the fall timing of the Q output signal of 5, originally,
What should have fallen at the timing of FIG. 3G, falls at the timing of FIG. 3F. As a result, it means that the period of the reference clock a is slowed down in the forward direction.

The above-described logical slowdown / fastening method in the direction of delay or advance in one cycle unit of the reference clock is already known and put into practical use.

[0010]

However, in the conventional logic regulation circuit, since only the logic regulation in the delay or advance direction of the reference clock in one cycle unit is possible, the rate adjustment resolution is fine and highly accurate. It was not suitable when adjusting the rate.

For example, the watch rate standard with an annual difference of 20 seconds (accuracy error within 20 seconds throughout the year) is ± 32 msec /
Although it is d, for example, 262 kH for the reference clock
If the crystal oscillation of z is used, the adjustment amount for one cycle of logical slow / quick becomes 32 msec / d. Considering the error of rate measurement and the like, there is a problem that it is very difficult to match the rate by changing the logical regulation data in order to mass-produce a highly accurate timepiece.

Further, when attempting to implement a high-precision clock with the conventional logic regulation circuit, the load capacitance in the oscillation circuit is periodically changed to finely adjust the frequency of the reference clock to obtain a finer regulation resolution. There is a way to get it,
There is a problem in that complicated control circuits and load capacitance adjustment work are required.

[0013]

SUMMARY OF THE INVENTION In order to further fine the slow-movement resolution without requiring a complicated control circuit or load capacitance adjustment work, in the present invention, a slow-movement data input means for half-cycle slowdown of the reference clock is used. And a data holding means,
By providing a half-cycle slowdown unit capable of slowing down / down in half-cycle units of the reference clock between the oscillating unit and the frequency dividing unit, the logic with smaller slowdown / fast resolution can be combined with the conventional single-cycle logical slowdown unit without changing the slowdown range. Made it possible to achieve speed.

[0014]

In order to realize the above function according to the present invention, the oscillation means 101 in FIG. 1 outputs a reference clock. The logical regulation data input means 108 inputs regulation data. The logic slow / fast data holding means 107 inputs and stores the output signal output from the logic slow / fast data input means 108. The half-cycle logical slowing / fastening means 102 inputs the output signal of the logical slowing / fastening data holding means 107 and performs the logical slowing / fastening in half cycle units of the reference clock. The frequency dividing means 103 inputs the clock output from the half-cycle logic slowing / fastening means 102 and divides the frequency. The one-cycle logic regulation means 106 inputs the output signal of the logic regulation data holding means 107 and receives the half-cycle logic regulation means 1.
Logic regulation is performed for each cycle of the clock output by 02. With the above configuration, the logic regulation circuit of the present invention performs logic regulation in half cycle units of the reference clock.

In the electronic timepiece using the logic regulation circuit of the present invention, since the logic regulation can be performed in half cycle units by adding a simple logic element, highly accurate time display becomes possible.

[0016]

Embodiments of the present invention will be described with reference to the drawings.
FIG. 4 is a circuit diagram showing an example of the basic configuration of the embodiment of the logic regulation circuit of the present invention.

The crystal oscillator circuit 401 outputs the reference clock signal a. In this embodiment, the signal has a frequency of 262 kHz. The half-cycle logic regulation circuit 415 receives the reference clock signal a, the control signal k output by the frequency division circuit 416, the VCW control signal d output by the one-cycle logic regulation circuit 417, and the logic regulation data VCWD1 as input, and the logic regulation data VC.
When WD1 is at "H" level, the reference clock signal a is half-periodically logically adjusted in synchronization with the control signal k output from the frequency dividing circuit 416, and the frequency-divided basic clock 1 which is the input clock of the frequency dividing circuit 416 is output. To do. This half-cycle logic regulation 415
Is an exclusive OR (hereinafter referred to as EXOR) circuit 402, a latch circuit 409, an AND circuit 410, and a TFF.
411. Detailed operation will be described later.

The frequency dividing circuit 416 includes TFFs 403 to 406.
It consists of. Since the control signal for operating the display drive circuit must be actually output, the TFF406
Although several stages of TFFs are connected after this, they are omitted here. The one-cycle logic regulation circuit 417 is provided in the latch circuit 41.
2, NOR circuit 413, DFF 414, AND circuit 40
7, 408. The one-cycle logic regulation circuit 417
The frequency division basic clock 1 output from the half-cycle logic slow / fast circuit 415, the slow / fast operation start signal VCWDR, the control signal j output from the frequency divider circuit 416, the logic slow / fast data VCWD2, VCW.
D3 as input, logical regulation data VCWD2, VCWD
When either or both of the three are "H" level, the frequency dividing circuit 416 is synchronized with the control signal j output from the frequency dividing circuit 416.
It outputs the one-cycle logical slowing / fastening operation signals m and n for presetting each TFF. The detailed operation has already been described in the section of the related art, and therefore will be omitted.

In the configuration of this embodiment, the slow-and-quick operation start signal V
When CWDR rises, one cycle logical slowing / quicking operation is performed at the next falling edge of 64 kHz, and half cycle logical slowing / fastening operation is performed at the next falling edge of 64 kHz. FIG. 5 is a timing chart of this embodiment.

The half-cycle logical regulation operation including the one-period logical regulation operation will be described in detail. Moderation start signal VCWDR
Rises (5-A) and as described in the section of the prior art, the NOR circuit 413 outputs a one-cycle logical slowing / quicking operation signal in synchronization with the next falling of 64 kHz (5-
B). It has already been described that the control signal d at the time when the one-cycle logical slow / fast operation signal falls is the Q output signal of the DFF 414. Further, this control signal d is combined with the data of the latch circuit 409 in the half cycle logical regulation circuit 415 and the AND circuit 4
Input to 10.

The AND circuit 410 has three inputs.
One of the inputs is the half cycle logic regulation data VCWD1.
Here, it is assumed that the "H" level is maintained as the data for performing the half cycle logical regulation. The other input of the AND circuit 410 is input with the QX output signal of the latch circuit 409.

The latch circuit 409 receives the Q output signal d of the DFF 414 in the one-period logical regulation circuit 417 as a data input, and outputs the Q output signal k of the TFF 405 in the frequency dividing circuit 416.
(Here, 32 kHz signal) is used as the clock signal. The QX output signal of the latch circuit 409 normally maintains the “H” level, and is synchronized with the next rise of 32 kHz (signal k) when the Q output signal d of the DFF 414 rises.
It falls to L "level (5-D).

The output of the AND circuit 410, to which the Q output signal d of the DFF 414, the half cycle logical regulation data VCWD1 and the QX output signal of the latch circuit 409 are input, is the DFF 414.
Rises in synchronization with the rise of the Q output signal d of (5
-C). Here, the half cycle logic regulation data VCWD1 is "
In the case of the L "level, one input of the AND circuit 410 is"
Since it becomes the L "level, the output of the AND circuit 410 is DFF.
The "L" level is maintained regardless of the change in the Q output signal d of 414, so that the half-cycle logical slowing / fastening operation is not performed.

The half cycle logic regulation data VCWD1 is "H".
In the case of the level, after the output of the AND circuit 410 becomes "H" level, the QX output signal of the latch circuit 409 becomes TFF4.
The Q output signal k of 06 (here, 32 kHz) falls in synchronization with the rising edge. At the same time, the output of the AND circuit 410 that receives the QX output signal of the latch circuit 409 also falls (5-E). The output signal of the AND circuit 410 is input to the clock of the falling TFF 411, so that the Q output signal o of the TFF 411 is inverted (5-
F). The Q output signal o of the TFF 411 is the EXOR circuit 40.
Entered in 2.

The other input of the EXOR circuit 402 is the reference clock signal a which is the output signal of the oscillation circuit 401.
The frequency dividing circuit 41 including the operation of the EXOR circuit 402 in FIG.
6 shows a timing chart of output signals of each TFF of No. 6.
In FIG. 6, the upper stage shows the state where the half-cycle logical slowdown / quick action is not performed, and the lower stage shows the half-cycle slowdown / loose action (6-A).
It shows the state at the timing of.

The Q output signal o of the TFF 411 is (6-A)
When inverted at the timing of, the output signal 1 of the EXOR circuit 402 changes from "L" level to "H" level. In other words, the reference clock signal a is forcibly set to the "H" level by omitting the "L" level period, so that the reference clock signal a falls half a cycle earlier than usual.

Thereafter, the output signal l of the EXOR circuit 402
Continues to output the inverted clock of the output of the oscillation circuit 401, which is the other input signal, until the Q output signal o of the TFF 411 is inverted. The output signal 1 of the EXOR circuit 402 is used as the frequency division basic clock 1 of the frequency division circuit 416 to perform the frequency division circuit 416.
After input to, the frequency is divided. Each TF of the frequency dividing circuit 416
Looking at the Q output signal of F in the timing chart of FIG.
The Q output signal of the TFF 403 rises earlier than the normal rise by the half cycle of the reference clock signal a (6−
B), the Q output signal of the TFF 404 rises earlier by a half cycle of the reference clock signal a than usual (6-C).

Similarly, the output signals of the following TFFs also change rapidly by a half cycle of the reference clock signal a, and the operation of the half cycle logic regulation circuit 402 causes the reference clock signal a to change.
It is possible to realize logical regulation in half cycle units. In the embodiment of the present invention, a display drive circuit that inputs the output signal of the frequency dividing means 416 and outputs a drive signal for driving the display element, and a display drive output signal that the display drive circuit outputs are input and time information is displayed. An electronic timepiece having a logical regulation circuit can be realized by adopting a configuration having a display element for displaying, for example. An electronic timepiece having this logic regulation circuit can be very highly accurate.

As the display element, a motor and a pointer, a liquid crystal panel or the like is preferably used. Further, by applying the logic regulation circuit of the present invention, it is possible to realize an electronic device with a logic regulation circuit that displays or reports timekeeping information such as a highly accurate timer, a stopwatch, or an alarm device.

[0030]

As described above, in the present invention, the oscillation means for outputting the reference clock, the logical slow / fast data input means for inputting the slow / fast data, and the output signal of the logical slow / fast data input means are input and stored. Input the output signal of the logic slowdown / fastness data holding means, the half cycle logic slowdown / fastening means for inputting the output signal of the logic slowdown / fastness data holding means to perform the logic slowdown / forward in half cycle unit of the reference clock, and the signal output from the half cycle logic slowdown / forwarding means. Frequency division means for performing frequency division, and one-cycle logic regulation means for performing logic regulation on a cycle-by-cycle basis of the clock output from the half-cycle logic regulation means by inputting the output signal of the logic regulation data holding means. As a result, there is an effect that it is possible to perform highly accurate logical regulation in half cycle units of the reference clock with a simple element configuration.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing an example of a basic configuration of an electronic timepiece with a logical slowdown / advance circuit of the present invention.

FIG. 2 is a circuit diagram of a conventional logic regulation circuit.

FIG. 3 is a timing chart of a slow / fast operation of a conventional logic slow / fast circuit.

FIG. 4 is a circuit diagram of an embodiment of a logic regulation circuit of the present invention.

FIG. 5 is a timing chart of an embodiment of the logic regulation circuit of the present invention.

FIG. 6 is a timing chart of a half-cycle grading part of the embodiment of the logic grading circuit of the present invention.

[Explanation of symbols]

 Reference Signs List 101 Oscillation means 102 Half-cycle logical slowing / forwarding means 103 Frequency dividing means 104 Waveform shaping means 105 Displaying means 106 Single-cycle logical slowing / forwarding means 107 Logical slowing / fastening data holding means 108 Logical slowing / fastening data inputting means

Claims (4)

[Claims] 1. An oscillating means (10) for outputting a reference clock.
1) and the logical speed / speed data input means (10) for inputting speed / speed data.
8) and an output signal of the logic slowdown / fastness data input means (108) to perform a logic slowdown / fastness in a half cycle unit of the reference clock and a half cycle logic slowdown / fastness means (102) output A frequency dividing means (103) for inputting a clock to divide the frequency, and an output signal of the logic slowdown / speedup data input means (108) for inputting a logic for each cycle of the clock output from the half cycle logic slowdown means (102). One-cycle logical speed-up / down means (10)
6) A logical regulation circuit comprising: 2. An oscillating means (10) for outputting a reference clock.
1) and the logical speed / speed data input means (10) for inputting speed / speed data.
8) and an output signal of the logic slowdown / fastness data input means (108) to perform a logic slowdown / fastness in a half cycle unit of the reference clock and a half cycle logic slowdown / fastness means (102) output A frequency dividing means (103) for inputting a clock to divide the frequency, and an output signal of the logic slowdown / speedup data input means (108) for inputting a logic for each cycle of the clock output from the half cycle logic slowdown means (102). One-cycle logical speed-up / down means (10)
6) and the output signal of the frequency dividing means (103) are input to display means (1
Display drive means (104) for outputting a drive signal for driving the display device (05), and display means (105) for inputting the display drive output signal output by the display drive means (104) to display time information and the like. An electronic watch characterized by having. 3. A logical regulation data input means (108) for inputting regulation data, and a logical regulation data input means (10).
Predetermined cycle logical regulation means (10) for inputting the output signal of 8) and performing logical regulation in a prescribed cycle unit shorter than the reference clock.
2) and the frequency changing means (10) for changing the frequency by inputting the output signal output from the predetermined period logic slowing / fastening means (102).
3) and an output signal of the logic slowdown / speedup data input means (108), and a logic slowdown / fastening means (106) for performing the slowdown / fastening of logic based on the output signal output from the predetermined period logic slowdown / fastness means (102).
And a logical regulation circuit having: 4. A display drive means (104) for outputting a drive signal for driving the display means (105) based on the output signal output by the frequency changing means (103) of the logic slowdown circuit according to claim 3. An electronic device with a logical slowdown / advance circuit, comprising: a display unit (105) for inputting a display drive output signal output from the display drive unit (104) to display time information.