JPH07129457A - Storage device - Google Patents

Abstract

PURPOSE:To continuously perform access to the discontinuous areas of a storage space by controlling the value of an address counter so as to change it into a value stored in a first address holding means. CONSTITUTION:This device is provided with plural counters 1-4 for storing a write or read address in a storage medium 6 for each device, and the write or read address is stored for each device by controlling the value of the counter matched with a second address (slip source address) as a skip source so as to change it into the first address (skip destination address) as the skip destination discontinuous from the second address. Therefore, the counters 1-4 corresponding to a certain device are operated, then the counters 1-4 corresponding to the other device are operated, thereby the other device can be accessed in the area discontinuous from the area accessed by the device without resetting the values of the counters 1-4 after the device is accessed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device, and more particularly to a storage device having a storage medium that a plurality of devices access for writing or reading.

[0002]

2. Description of the Related Art In a conventional storage device, data is stored in order from the start address of the storage space (hereinafter referred to simply as the start address), and the final address of the storage space (hereinafter referred to as the final address). However, the storage capacity of the storage medium limits the amount of data that can be handled by the storage device. In order to improve this drawback, a storage device in which a part or the whole of the storage space is used as a ring buffer has been proposed, for example, there is a technique disclosed in JP-A-60-100872. In the above technique, a memory is connected to the image input unit, and the image data output from the image input unit is sequentially stored page by page from the start address, and the data stored in the remaining capacity of the writing area of the memory is stored. If the amount of data is less than, after storing the data up to the final address of the writing area,
The ring buffer is realized by successively storing from the start address until the write address reaches the inhibit top address indicating the start address of the write-protected area.

[0003]

However, in the above technique, when another device accesses an area discontinuous with the area accessed by the device after the access by the device, or when a certain device has a storage space When accessing a discontinuous area, it is necessary to reset the value in the counter inside the storage device each time, so that control and management of the write or read address become complicated. Therefore, the system using the above technique takes time for resetting the value more than the case where the resetting of the value in the counter is not necessary, and there is a problem that the processing speed of the system becomes slow.

The present invention is intended to solve the above-mentioned problems, and it is possible to continuously access a discontinuous area of a storage space from outside the storage device without resetting a value in a counter inside the storage device. It is possible to improve the processing speed by eliminating the time and procedure for resetting the value to the counter.
It is an object of the present invention to provide a storage device whose control is simplified.

[0005]

A storage device according to the present invention includes a storage medium accessed by a plurality of devices for writing or reading data, and writing or reading corresponding to the plurality of devices, respectively. A plurality of address counters for instructing a read address, a first address holding means for holding an arbitrary address in the storage space of the storage medium, and an arbitrary address different from the address stored in the first address holding means. A second address holding unit that holds an address is compared with the value of the address counter and the address stored in the second address holding unit, and when the two match, the value of the address counter is set to the first value. And a control means for controlling to change to a value stored in the address holding means.

[0006]

According to the present invention, each device is provided with a plurality of counters for storing a write or read address in the storage medium, and the count value matches the second address (hereinafter referred to as the jump source address) which is the jump source. The value of the counter is the second
The address of is controlled so that it becomes the first address (hereinafter referred to as a jump destination address) which is a discontinuous jump destination, and the write or read address is stored for each device, so that it corresponds to a certain device. If the counter corresponding to another device is activated after the counter is activated, it is divided into an area discontinuous from the area accessed by the device after the access by a device without resetting the value of the counter. Devices can be accessed. When the counter value matches the jump source address, the next address is set as the jump destination address, so that a device can continuously access the discontinuous area of the storage space.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a storage device according to the present invention is shown in FIGS.
Will be described below with reference to. In the following,
It is assumed that the address is in ascending order from the address of the storage space to the final address. In addition, the active level is the signal level (either high or low) at which the part to which the signal is input performs a predetermined operation when the signal becomes the active level, and the inactive level is the opposite of the active level. Shall mean signal level.

FIG. 1 shows an example of the configuration of a system including the storage device of the present invention when there are four devices that access the storage medium, and FIG. 2 shows an example of the configuration of the storage device of FIG. An example is shown. 1 and 2, a thick arrow indicates a bus, a thin arrow indicates a signal line, and an arrow direction indicates a signal flow direction. In FIG. 1, devices 11 to 14 access a storage medium in the storage device 15, for example, an image processing device such as an image compression device, an image input device such as a scanner, an image recording device such as a printer, and a communication interface with the outside. Device or the like, and the device 11
14 to 14 need to access the storage medium in the storage device 15, the corresponding access request signals RQ1 to RQ1
RQ4 is set to the active level, the device permitted to access exchanges data with the storage device 15, and when the access is completed, the signals RQ1 to RQ4 are set to the inactive level. The storage device 15 is a storage device according to the present invention, and an internal configuration example and operation will be described later.
The control device 16 is a CPU (central processing unit) and peripheral circuits that control the operations of the devices 11 to 14, the storage device 15, and the access control device 17. The access control device 17 receives the access request signal RQ from the devices 11 to 14.
The presence or absence of an access request from each device is determined according to the signal levels of 1 to RQ4, and if any device is not accessing, only one device to which access is permitted is determined according to a predetermined priority order. The storage medium 6 in the storage device 6 stores the signals ET1 to ET4, which are count enable signals to the corresponding counters, and the signal group CNTL, which is a control signal group to the storage device 15.
The active level is set at a predetermined timing determined by the configuration of FIG. 2 and the device to be accessed.
If any device is accessing the storage device 15, the access control device 17 does not allow any other device to access the storage device 15. The signal group CNTL is a control signal group that controls the storage device 15 at the time of writing data to the storage device 15 of the devices 11 to 14 or reading data from the storage device 15.

Next, FIG. 2, which is an example of the configuration of the storage device of FIG. 1, will be described. Each of the counters 1 to 4 is an up-counter having the same number of bits as the address in the storage space of the storage medium 6 for storing the read or write address of the device 1 to 4 that accesses the storage medium 6, and the interface corresponding to each. When the signals LE1 to LE4 from the (I / F) 8 become active level, the bus LD
Load the above data and the corresponding signal ET1
When ET4 to ET4 reach the active level, the count-up is performed, and when the corresponding signals RS1 to RS4 reach the active level, the jump destination address stored in the register 9 is loaded. Further, the value stored in each counter, that is, the write or read address is output to the MUX (multiplexer) 5. MUX5
Is data of any one of the counters 1 to 4 according to the signal MX from the access control device 17,
That is, a write or read address is selected, and all or some of the bits of the selected address (for example, lower 10 bits) are selected by the signal RC from the access control device 17.
(Bit) to the storage medium 6.

The storage medium 6 is composed of a DRAM, a hard disk drive (HDD), etc., and stores data from the outside in an area designated by an address output from the MUX 5 by the signal group CNTL or outputs from the MUX 5. The data stored in the area specified by the address is output to the outside. The register 9 is a register for storing the jump destination address, and is a signal LE.
When 5 becomes the active level, the data on the bus LD is loaded and stored, and the stored data is output to the counters 1 to 4. The register 10 is a register for storing the jump source address. When the signal LE6 becomes the active level, the register 10 loads and stores the data on the bus LD and outputs the stored data to the determiner 7. When the values of the counters 1 to 4 match the jump source address stored in the register 10, the determiner 7 sets the signals RS1 to RS4 corresponding to the counters whose values match the jump source address to the active level at a predetermined timing. To do.
For example, when the value of the counter 1 matches the jump source address, the signal RS1 is set to the active level and the counter 1
Will load the jump destination address stored in the register 9. The I / F 8 is an interface for setting a value in the counters 1 to 4, the register 9 or the register 10 from the outside of the storage device, and when the signal CDS from the control device 16 becomes the active level, it is designated by the address on the bus CAD. Load enable signal L corresponding to counters 1 to 4 and register 9 or register 10
E1-LE6 are set to the active level, and the data on the bus CDT is output on the bus LD.

In the following, as an operation example, it is assumed that the storage medium 6 is composed of a DRAM which requires input of signals, data and addresses at the timings shown in FIG. 5, and the data to be written in the storage medium 6 is one word ( Storage medium 6 of the devices 11 to 14 in the unit of 16 bits)
The operation of the storage device of the present invention when accessing the memory will be described. Since the storage medium 6 is configured as described above, the signal group CNTL is D
A signal RAS for taking in a row address by the RAM, a signal CAS for taking in a column address by the DRAM at a falling edge, a write enable signal WE and an output enable signal OE. In the following, rad
Is a row address that is the upper half of the address, for example, the upper 10 bits if the address is 20 bits, and cad
Is a column address which is the lower half of the address, for example, the lower 10 bits if the address is 20 bits,
The upper half of d + cad is rad, and the lower half is ca.
means an address that is d. For example, rad = 10h
If cad = 00h in (hexadecimal), rad + cad = 1
It is 000h. The DRAM stores data at an address designated by rad + cad when the signal WE is at the active level, and r when the signal OE is at the active level.
Outputs the data stored at the address specified by ad + cad. Further, for simplification of description below, the access request signals of two or more devices do not become active levels at the same time, and when one device sets the access request signal to the active level, any other device stores a storage medium. It is assumed that 6 is not accessed.

First, the case where the device 12 writes data after the device 11 writes data from the head address will be described. First, the leading address is set in the counter 1 via the I / F 8. Here, when the number of words of data to be written in the storage medium 6 by the device 11 is known in advance, an address equal to or higher than the address obtained by adding 1 to the number of times of the word to the start address and equal to or lower than the final address is similarly set in the register 9. Addresses greater than or equal to the address set in the register 9 and less than or equal to the final address are set in the counter 2, and addresses greater than or equal to the address set in the counter 2 and less than or equal to the final address are set in the register 10. Therefore, assuming that the start address of the storage area that can be accessed only by a specific device is the third address, the address obtained by subtracting 1 from this is the jump source address, and the jump destination address is closer to the start address than the jump source address. The space is as shown in FIG.

The operation in this case will be described with reference to FIG. First, the device 11 sets the signal RQ1 to the active level. Since the signal RQ1 becomes the active level, the access control device 17 causes the device 11 to store the storage medium 6
To the signal RAS, the signal CAS, the signal ET1, and the signal M at the timing shown in FIG. 6A.
X, the signal RC, and the signal group CNTL are set to the active level. 6A is a timing chart when the counter value does not match the jump source address, and FIG. 6B is a timing chart when it matches. When the data is written in the storage medium 6, the access control device 17 outputs the signal RA.
S, the signal CAS, the signal ET1, the signal MX, the signal RC, and the signal group CNTL are set to the inactive level, and the device 11 sets the signal RQ1 to the inactive level. By repeating the above operation a predetermined number of times, the device 11 can write data from the head address. here,
If the number of words of data to be written in the storage medium 6 by the device 11 is not known in advance, it is equal to or more than the address obtained by adding 1 to the value of the counter 1 at the time when the access of the device 11 is completed via the I / F 8 and the final value. Addresses below the address in register 9 and counter 2 in register 9
An address equal to or more than the address set to No. 2 and less than the final address is set to the register 10, and an address more than or equal to the address set to the counter 2 and less than the final address is set to the register 10. Next, the device 12 brings the signal RQ2 to the active level. Since the signal RQ2 has become the active level, the access control device 17 causes the device 12 to store the storage medium 6
To the signal RAS, the signal CAS, the signal ET2, and the signal M at the timing shown in FIG. 6A.
X, the signal RC, and the signal group CNTL are set to the active level. When data is written in the storage medium 6, the access control device 17 causes the signal RAS, the signal CAS, and the signal ET.
2, the signal MX, the signal RC, and the signal group CNTL are set to the inactive level, and the device 12 sets the signal RQ2 to the inactive level. At this time, when the value of the counter 2 matches the jump source address stored in the register 10, the determiner 7 sets the signal RS2 to the active level at the timing shown in FIG. 6B, and the signal RS2 becomes the active level. Now, the counter 2 loads the jump destination address from the register 9. Therefore, the address accessed next to the jump source address is the jump destination address. By repeating the above operation a predetermined number of times, the device 12 can write data in the area from the jump destination address to the jump source address. As described above, the device 11 and the device 12 can write in the shaded area and the shaded area shown in FIG. 7, respectively. The thick arrows in FIG. 7 indicate the order in which the device 12 writes data.

Secondly, a case where the device 12 writes data after the device 11 has written data in the area from the third address to the final address will be described.
First of all, via the I / F 8, the counter 1 is provided with a third address, the counter 2 is provided with an address equal to or greater than the start address and equal to or less than the address obtained by subtracting 1 from the third address, is set to the register 9 or greater and equal to the counter 2 Set an address less than the set address. Therefore, the address obtained by subtracting 1 from the third address is the jump source address, and the jump destination address is an address closer to the start address than the jump source address, so the storage space is as shown in FIG.

In operation, the device 11 brings the signal RQ1 to the active level. Since the signal RQ1 becomes the active level, the access control device 17 permits the device 11 to access the storage medium 6,
The signal RAS and the signal CA at the timing shown in FIG.
S, signal ET1, signal MX, signal RC and signal group CN
Set TL to the active level. When the data is written in the storage medium 6, the access control device 17 causes the signal RAS,
The signal CAS, the signal ET1, the signal MX, the signal RC, and the signal group CNTL are set to the inactive level, and the device 1
1 sets the signal RQ1 to the inactive level. By repeating the above operation until the value of the counter 1 becomes equal to the final address, the device 11 can write data from the third address to the final address. Next, the device 12 brings the signal RQ2 to the active level. Signal R
Since Q2 has become the active level, the access control device 17 permits the device 12 to access the storage medium 6, and the signal RAS at the timing shown in FIG.
The signal CAS, the signal ET2, the signal MX, the signal RC, and the signal CNTL are set to the active level. When the data is written in the storage medium 6, the access control device 17 causes the signal RAS, the signal CAS, the signal ET2, the signal MX, and the signal RC.
And the signal group CNTL is set to the inactive level, and the device 12 sets the signal RQ2 to the inactive level. At this time, when the value of the counter 2 matches the jump source address stored in the register 10, the determiner 7 sets the signal RS2 to the active level at the timing shown in FIG. 6B, and the signal RS2 becomes the active level. Now, the counter 2 loads the jump destination address from the register 9. Therefore, the address accessed next to the jump source address becomes the jump destination address. By repeating the above operation a predetermined number of times, the device 12 can write data in the area from the jump destination address to the jump source address. As described above, the device 11 and the device 12 can write data in the shaded area and the hatched area shown in FIG. 8, respectively. The thick arrows in FIG. 8 indicate the order in which the device 12 writes data.

Thirdly, a case will be described in which, after the device 11 writes data from the third address, the device 12 writes data from an address equal to or higher than the start address and equal to or lower than the address obtained by subtracting 1 from the third address. First, a third address is set in the counter 1 via the I / F 8, an address obtained by subtracting 1 from the third address is set in the register 10, and an address not less than the start address and not more than the address set in the register 10 is set in the counter 2. Set. Here, if the number of words of data to be written in the storage medium 6 by the device 11 is known in advance, an address obtained by adding 1 to the third address is set in the register 9 in the same manner. Therefore, the address obtained by subtracting 1 from the third address is the jump source address, and the address obtained by adding 1 to the final address of the area where the device 11 writes data is the jump destination address. Since the address is close to the start address, the storage space is as shown in FIG.

In operation, the device 11 brings the signal RQ1 to the active level. Since the signal RQ1 becomes the active level, the access control device 17 permits the device 11 to access the storage medium 6,
The signal RAS and the signal CA at the timing shown in FIG.
S, signal ET1, signal MX, signal RC and signal group CN
Set TL to the active level. When the data is written in the storage medium 6, the access control device 17 causes the signal RAS,
The signal CAS, the signal ET1, the signal MX, the signal RC, and the signal group CNTL are set to the inactive level, and the device 1
1 sets the signal RQ1 to the inactive level. By repeating the above operation a predetermined number of times, the device 11 can write data from the third address. Here, if the number of words of data to be written in the storage medium 6 by the device 11 is not known in advance, 1 is set to the value of the counter 1 at the time when the access of the device 11 to the register 9 via the I / F 8 is completed. Register the added address
Set to. Next, the device 12 brings the signal RQ2 to the active level. Since the signal RQ2 has become the active level, the access side control device 17 permits the device 12 to access the storage medium 6, and the signal RAS, the signal CAS, and the signal ET at the timings shown in FIG. 6A.
2. The signal MX, the signal RC, and the signal group CNTL are set to the active level. When the data is written in the storage medium 6, the access control device 17 causes the signal RAS, the signal CAS,
Signal ET2, signal MX, signal RC and signal group CNTL
Is the inactive level. At this time, the counter 2
If the value of the counter coincides with the jump source address stored in the register 10, the decision unit 7 sets the signal RS2 to the active level at the timing shown in FIG. 6B, and the signal RS2 becomes the active level. The jump destination address is loaded from the register 9. Therefore, the address accessed next to the jump source address becomes the jump destination address. By repeating the above operation a predetermined number of times, the device 12 can write data from an address which is equal to or higher than the head address and equal to or lower than the address set in the register 10. As described above, the device 11 and the device 12 can write data in the shaded area and the shaded area shown in FIG. In FIG. 9, the thick arrow indicates the device 12
Represents the order of writing data.

Fourth, after the device 11 writes data from the third address, the device 12 writes data from an address which is one address after the final address of the area accessed by the device 11 and which is less than the final address. The case will be described. First, the third address is set in the counter 1 and the head address is set in the register 9 via the I / F 8. Here, if the number of words of data to be written in the storage medium 6 by the device 11 is known in advance, the number of words 1
An address equal to or more than the address added with and less than or equal to the final address is set in the counter 2. Next, similarly to the device 11 when the device 11 is the third device, data is written from the third address. Here, when the number of words of data to be written in the storage medium 6 by the device 11 is not known in advance, the device 1 is stored in the counter 2 via the I / F 8.
When the access of 1 is completed, an address equal to or greater than the address obtained by adding 1 to the address stored in the counter 1 and equal to or less than the final address is set. Next, the device 12 brings the signal RQ2 to the active level. Since the signal RQ2 has become the active level, the access control device 17 permits the device 12 to access the storage medium 6,
The signal RAS and the signal CA at the timing shown in FIG.
S, signal ET2, signal MX, signal RC and signal group CN
Set TL to the active level. When the data is written in the storage medium 6, the access control device 17 causes the signal RAS,
The signal CAS, the signal ET2, the signal MX, the signal RC, and the signal group CNTL are set to the inactive level, and the device 1
2 sets the signal RQ2 to the inactive level. At this time, when the value of the counter 2 matches the jump source address stored in the register 10, that is, the final address, the decision unit 7 sets the signal RS2 to the active level at the timing shown in FIG. Since it becomes the active level, the counter 2 jumps from the register 9 to the destination address,
That is, the top address is loaded. Therefore, the address to be accessed next to the final address is the top address. By repeating the above operation a predetermined number of times, the device 12 can write data from an address which is one address after the final address of the area accessed by the device 11 and which is less than the final address. Device 11
Then, the device 12 can write data in the shaded area and the hatched area shown in FIG. Note that, in FIG. 10, thick arrows indicate the order in which the device 12 writes data.

In the above, in the first to fourth cases, the operation when two devices sequentially access has been described.
The operation when three or more devices sequentially access can be described by a combination of the operations in the first to fourth cases. For example, after the device 11 writes data from the third address, the devices 12 from the fourth address to the final address which is equal to or more than the address obtained by adding 1 to the last address of the area accessed by the device 11 and less than the last address When the device 13 writes data from the start address, and the device 14 accesses from an address equal to or higher than the address obtained by adding 1 to the final address of the area accessed by the device 13 and equal to or lower than the address obtained by subtracting 1 from the third address. First causes the storage device to operate in the same manner as in the fourth case, and then in the second case, the address obtained by adding 1 to the address stored in the counter 1 at this point in the register 9 is added, The operation when the address obtained by subtracting 1 from the third address is set in register 10 Then, the same operation as in the third case is performed, and the device 14 accesses the area above the address obtained by adding 1 to the final address of the area accessed by the device 13 and below the address obtained by subtracting 1 from the third address. In the same manner as in the third case, the device 14 accesses the area above the address obtained by adding 1 to the final address of the area accessed by the device 11 and below the address obtained by subtracting 1 from the fourth address. In the second case, the device 1 in register 9
It is sufficient to perform the operation when the address obtained by adding 1 to the final address of the area accessed by 3 is set. FIG. 11 shows the area of the spatial storage accessed by each device in this case. The same applies when four or more devices sequentially access.

As an example of the operation described above, it is assumed that the storage medium 6 is composed of a DRAM which needs to input signals, data and addresses at the timings shown in FIG. 5, and the data to be read from and written to the storage medium 6 is one word ( Although the operation of the storage device of the present invention has been described in the case of the unit of 16 bits), it is clear from the following that the present invention is not limited to this.

First, when the storage medium 6 is composed of a DRAM which requires input of signals, data and addresses at timings different from those shown in FIG. 5, the signal group CNTL and access is permitted. Signal ET1 to ET4 corresponding to the device, signal MX,
Only the timing of setting the signal RC and the signal group CNTL to the active level changes, and the operation of the storage device itself does not change. In addition, the data to be read from and written to the storage medium 6 is 1
The same applies to the case where the storage medium 6 is not a word unit and the storage medium 6 is configured by a hard disk drive, a magneto-optical disk device, or the like.

When a plurality of devices simultaneously set the access request signal to the active level, only one device requests the access request signal after the access control device 17 determines the devices to which the access is permitted according to a predetermined priority. The same operation as when is set to the active level is performed.If another device sets the access request signal to the active level while another device is accessing, access is performed until the access of the device being accessed at the minimum is completed. You just have to wait for permission.

Further, in the system configuration example including the storage device of the present invention shown in FIG. 1, the number of devices that access the storage device for writing or reading data is four. The minimum number of counters in the storage device 15 may be prepared and the same control as described above may be performed. For devices having separate input data buses and output data buses, a read counter and a write counter are provided, and a read access request signal and a write access signal are provided to perform the same control as above. Good.

In the configuration example of the memory device of the present invention shown in FIG. 2, the jump destination address is stored in the register 9 and the signal R
When S1 to RS4 become active levels, the corresponding counters 1 to 4 load the jump destination address from the register 9, but the jump source address is fixed to a certain address as shown in FIG. When changing the signal, the counter may be configured so that the value becomes the jump destination address when the signals RS1 to RS4 become the active level.

Further, in the configuration of the memory device of the present invention shown in FIG. 2, the jump source address is stored in the register 10, and when the values of the counters 1 to 4 become equal to the jump source address, the signal RS is output.
1 to RS4 are set to the active level,
As a circuit configuration example for that purpose, a bus RD and a bus CD1
~ CD4 as an input, and when the data on the buses CD1 to CD4 match the data on the bus RD, the corresponding signals RS1 to R
Although there is a determiner (comparator) that makes S4 an active level, as shown in FIG. 13, when the jump destination address is fixed to a certain address and the jump source address is changed, the determiner 7 uses the buses CD1 to CD4. Input as bus CD1-CD
4 may be a combinational circuit that sets the corresponding signals RS1 to RS4 to the active level at a predetermined timing when the data on 4 corresponds to the jump source address.

[0026]

As described above, according to the present invention, it is possible to continuously access discontinuous areas of the storage space from outside the storage device without resetting the value in the counter inside the storage device. . Therefore, the time and procedure for resetting the value are unnecessary, the processing speed can be improved, and the control can be simplified. In addition, a device that accesses the storage medium can read and write data of an arbitrary amount of data to and from the storage medium, and particularly when the jump destination address is closer to the start address due to the jump source address, the area from the jump destination address to the jump source address Since it becomes the ring buffer area, the storage space can be effectively used.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a system including a storage device of the present invention.

FIG. 2 is a configuration diagram of a storage device of the present invention.

FIG. 3 is a diagram showing a state of a storage space when a jump destination address is set to an address closer to a start address than a jump source address.

FIG. 4 is a diagram showing a state of a storage space when a jump source address is set to an address closer to a start address than a jump destination address.

5 is a diagram showing an example of timings of control signals, data and addresses for the storage medium of FIG.

FIG. 6 is a timing chart of each signal when a DRAM is required to control each signal at the timing shown in FIG. 5 in the storage medium of FIG. 2 and a device accesses the storage medium for reading data. It is a figure which shows an example.

FIG. 7 is a diagram showing a state of a storage space in the first case.

FIG. 8 is a diagram showing a state of a storage space in the second case.

FIG. 9 is a diagram showing a state of a storage space in a third case.

FIG. 10 is a diagram showing a state of a storage space in a fourth case.

FIG. 11 is a diagram showing an example of a storage space state when three or more devices sequentially access.

FIG. 12 is a diagram showing a state of a storage space when a jump destination address is fixed.

FIG. 13 is a diagram showing a state of a storage space when a jump source address is fixed.

[Explanation of symbols]

1 to 4 ... Address counter, 5 ... Multiplexer, 6 ...
Storage medium, 7 ... Judgment device, 8 ... Interface, 9-1
0 ... Register, 11-14 ... Device, 15 ... Storage device, 16 ... Control device, 17 ... Access control device

Claims (1)

[Claims] 1. A storage medium that a plurality of devices access to write or read data, and a plurality of address counters that respectively indicate write or read addresses corresponding to the plurality of devices. First address holding means for holding an arbitrary address in the storage space of the storage medium, and second address holding means for holding an arbitrary address different from the address stored in the first address holding means To compare the value of the address counter with the address stored in the second address holding means, and change the value of the address counter to the value stored in the first address holding means when they match. A storage device comprising control means for controlling.