JPH07130184A - Semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] To realize a static RAM or the like that can handle a plurality of power supply voltages of different potentials. As a result, the number of required photomasks such as static RAMs is reduced to promote cost reduction, the number of product types is reduced, and user convenience is increased. A static RAM or the like having a data input buffer and a data output buffer is provided with a power supply voltage identification circuit that selectively sets the output signal VD to a high level when the absolute value of the power supply voltage exceeds a predetermined value. Unit data input buffer UIB0 of data input buffer IB
Is provided with a MOSFET N8 that is selectively enabled when the output signal VD of the power supply voltage identification circuit is at a high level, and the unit data input buffer U is provided according to the potential of the power supply voltage.
The logic threshold level of the first-stage logic gate such as IB0 is selectively and substantially switched.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, for example, a static RAM having an input circuit such as a data input buffer and an output circuit such as a data output buffer.
The present invention relates to a technology that is particularly effective when used for (random access memory) and the like.

[0002]

2. Description of the Related Art There is a static RAM having an input circuit such as a data input buffer and an output circuit such as a data output buffer. In these static RAM etc.,
The input signal level and the output signal level are defined as so-called input / output interface conditions. Taking the TTL (transistor / transistor logic) interface as an example, for example, the minimum input high level of the input signal is 2.2V (volt). The maximum value of the input low level is 0.8V, the minimum value of the output high level of the output signal is 2.4V, and the maximum value of the output low level is 0.4V. Each input circuit is assumed to have a predetermined logic threshold level to satisfy the above input condition in its first-stage logic gate, and each output circuit has an output MOSFET.
(A metal oxide semiconductor field effect transistor. In this specification, a MOSFET is used as a general term for an insulated gate field effect transistor), which has a predetermined output signal level so as to satisfy the above output conditions in its output stage. It is said that

On the other hand, with the miniaturization and high integration of integrated circuits, the operating power supply for static RAMs is becoming lower in voltage. On the other hand, it is necessary to deal with the conventional products, for example, +3 in the market. There is a situation where a product compatible with a low voltage power supply such as .3V and a product compatible with a conventional + 5V power supply voltage coexist. Needless to say, there is no big difference in the input / output interface conditions between the two products, and in the input circuit, it is necessary to change the logic threshold level of the first-stage logic gate according to the potential of the power supply voltage, and in the output circuit, the output signal level is changed. It will be necessary to switch.

A static RAM capable of supporting a power supply voltage of + 3.3V is described in, for example, "HM62W8127H Series Data Book" published by Hitachi, Ltd. in September 1993, and a power supply voltage of + 5V is supported. The static RAM that can be used is described, for example, in "HM628127H series data book" published by Hitachi, Ltd. in September 1993.

[0005]

The two types of static RAMs described above are constructed on the basis of a common base chip, and have the logic threshold level of the first stage logic gate of the input circuit and the output signal of the output circuit. The level can be selectively switched by, for example, partially changing a part of the photomask for forming the metal wiring layer. In other words, most of these static RAMs are handled as different types of products even though most of them have the same structure, and the number of photomasks to be prepared increases from the manufacturer's point of view. The cost of the type RAM is hindered from being reduced, and the user is forced to select a product according to the power supply voltage, which reduces the convenience.

An object of the present invention is to realize a static RAM or the like which can handle a plurality of power supply voltages having different potentials. Another object of the present invention is static type R
It is to promote the cost reduction of AM and the like, and to improve its convenience.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in a static RAM or the like having an input circuit such as a data input buffer and an output circuit such as a data output buffer, a power supply for selectively setting the output signal to an effective level when the absolute value of the power supply voltage exceeds a predetermined value. A voltage discriminating circuit is provided, and the logic threshold level of the first stage logic gate of the input circuit is selectively switched according to the output signal of the power supply voltage discriminating circuit, and the output impedance of the output stage of the output circuit is selectively switched.

[0009]

According to the above means, the input / output interface conditions of the static RAM or the like can be selectively and automatically switched according to the potential of the power supply voltage.
It is possible to realize a static RAM or the like that can handle a plurality of power supply voltages of different potentials. As a result, it is possible to reduce the number of required photomasks such as static RAMs and promote the cost reduction, and also to use static R
It is possible to reduce the number of product types such as AM and improve the convenience of the user.

[0010]

1 is a block diagram of an embodiment of a static RAM to which the present invention is applied. First, the outline of the configuration and operation of the static RAM of this embodiment will be described with reference to FIG. The circuit elements forming each block in FIG. 1 are not particularly limited, but may be manufactured by a known CMOS (complementary MOS) integrated circuit manufacturing technique.
It is formed on one semiconductor substrate surface such as single crystal silicon.

In FIG. 1, the static RAM is
Memory array M occupying most of the semiconductor substrate surface
Let ARY be its basic component. This memory array M
ARY has a plurality of word lines arranged in parallel in the horizontal direction of the figure, a plurality of complementary bit lines arranged in parallel in the vertical direction, and a grid pattern at intersections of these word lines and complementary bit lines. And a number of static memory cells arranged.

The word lines forming the memory array MARY are coupled to the X address decoder XD on the left side thereof and are alternatively set to the selected state. X address decoder X
The X address buffer XB supplies the i + 1-bit internal address signals X0 to Xi to D, and the timing generation circuit TG supplies the internal control signal CS. Also, X
The address buffer XB has address input terminals AX0-AX0.
The X address signals AX0 to AXi are supplied via AXi, and an internal control signal AL (not shown) is supplied from the timing generation circuit TG to supply the power supply voltage identification circuit VC.
The output signal, that is, the internal signal VD is supplied from the LD. The internal control signals CS and AL are selectively set to high level at predetermined timings when the chip enable signal CEB is set to low level. Also,
For the internal signal VD, for example, the potential of the power supply voltage VCC is + 4V.
When it exceeds, it is selectively set to high level.

The X address buffer XB fetches the X address signals AX0 to AXi supplied via the address input terminals AX0 to AXi in accordance with the internal control signal AL,
The internal address signals X0 to Xi are formed based on these X address signals while being held, and are supplied to the X address decoder XD. In this embodiment, the X address buffer XB includes i + 1 unit address buffers provided corresponding to the X address signals AX0 to AXi, and the ratio between the logic threshold level of the first-stage logic gate and the absolute value of the power supply voltage VCC. Is selectively reduced by setting the internal signal VD to a high level.
The switching of the logical threshold level by such an internal signal VD will be described in detail later in a specific description regarding the data output buffer OB.

The X address decoder XD is selectively operated in response to the high level of the internal control signal CS, decodes the internal address signals X0 to Xi, and selectively selects the corresponding word line of the memory array MARY. To the selected state.

Next, the complementary bit lines forming the memory array MARY are coupled to the Y switch YS below the complementary bit lines, and the common data lines CD0 * to C are selectively added by k + 1 sets.
Dk * (Here, for example, the non-inverted common data line CD0 and the inverted common data line CD0B are collectively denoted by an asterisk such as the complementary common data line CD0 *. Also, when it is valid, it is selectively selected. A so-called inverted signal or the like which is set to a low level is indicated by adding B to the end of its name. The same shall apply hereinafter). A predetermined number of bit selection signals are supplied from the Y address decoder YD to the Y switch YS. Further, the Y address decoder YD has a j + 1-bit internal address signal Y0 to Y + 1 from the Y address buffer YB.
Yj is supplied, and the internal control signal CS is supplied from the timing generation circuit TG. Furthermore, Y address buffer Y
B is supplied with Y address signals AY0 to AYj via address input terminals AY0 to AYj, and an internal control signal AL (not shown) from the timing generation circuit TG.
Is supplied to the internal signal V from the power supply voltage identification circuit VCLD.
D is supplied.

The Y address buffer YB fetches the Y address signals AY0 to AYj supplied through the address input terminals AY0 to AYj in accordance with the internal control signal AL,
The internal address signals Y0 to Yj are formed based on these Y address signals while being held and supplied to the Y address decoder YD. In this embodiment, the Y address buffer YB includes j + 1 unit address buffers provided corresponding to the Y address signals AY0 to AYj, and the ratio between the logic threshold level of the first-stage logic gate and the power supply voltage VCC is X. Similar to the address buffer XB, the internal signal VD is made high level to selectively reduce it. The switching of the logical threshold level by the internal signal VD will be described in detail later in a specific description regarding the data output buffer OB.

The Y address decoder YD is selectively operated in response to the high level of the internal control signal CS, decodes the internal address signals Y0 to Yj, and selectively turns the corresponding bit line selection signal high. Select a level.

On the other hand, the Y switch YS is a memory array M.
A plurality of pairs of switch MOSFETs provided corresponding to each complementary bit line of ARY are included. These switch MOS
One of the FETs is coupled to the corresponding complementary bit line of the memory array MARY, and the other is connected to the complementary common data line C.
Sequentially k + 1 to non-inverted or inverted signal lines of D0 * to CDk *
Commonly coupled every other pair. The gates of the respective switch MOSFETs are commonly coupled by k + 1 pairs, and a corresponding bit line selection signal is supplied from the Y address decoder YD. As a result, each switch MOSFET of the Y switch YS is
When the corresponding bit line selection signal is set to the high level, k + 1 pairs are selectively turned on, and the memory array M
The corresponding k + 1 complementary bit lines of ARY and the complementary common data lines CD0 * to CDk * are selectively connected.

The complementary common data lines CD0 * to CDk * are
It is coupled to the write amplifier WA and further to the sense amplifier SA
Be combined with. Write amplifier WA and sense amplifier SA
Respectively include k + 1 unit circuits provided corresponding to the complementary common data lines CD0 * to CDk *, and the data input buffer IB and the data output buffer OB are also provided as k + 1 units provided corresponding to these unit circuits. Each circuit is provided.

The input terminal of each unit circuit of the write amplifier WA is coupled to the output terminal of the corresponding unit circuit of the input circuit, that is, the data input buffer IB, and the input terminal of each unit circuit of the data input buffer IB corresponds. Data input / output terminals D0-Dk are coupled. On the other hand, the output terminal of each unit circuit of the sense amplifier SA is respectively coupled to the input terminal of the output circuit, that is, the corresponding unit circuit of the data output buffer OB, and the output terminal of each unit circuit of the data output buffer OB corresponds to the corresponding data. Input / output terminals D0-Dk are coupled. An internal control signal WP is commonly supplied from the timing generation circuit TG to each unit circuit of the write amplifier WA. In addition, all the unit circuits of the data input buffer IB are connected to the internal control signal C from the timing generation circuit TG.
S is commonly supplied, and the internal signal VD is commonly supplied from the power supply voltage identification circuit VCLD. Further, the internal control signal OC is commonly supplied from the timing generation circuit TG and the internal signal VD is commonly supplied from the power supply voltage identification circuit VCLD to all the unit circuits of the data output buffer OB.

Each unit circuit of the data input buffer IB is
When the static RAM is selected in the write mode, the write data supplied via the data input / output terminals D0 to Dk is transmitted to the corresponding unit circuit of the write amplifier WA. At this time, each unit circuit of the write amplifier WA is selectively activated by receiving the high level of the internal control signal WP, and the write data transmitted from the data input buffer IB is used as a predetermined complementary write signal.
These complementary write signals are supplied to the complementary common data line CD0.
The data is transmitted from * to CDk * to the selected k + 1 memory cells of the memory array MARY via the Y switch YS and written. In this embodiment, the ratio between the logic threshold level of the first-stage logic gate of each unit circuit of the data input buffer IB and the absolute value of the power supply voltage VCC is
When the internal signal VD is set to the high level, it is selectively reduced. The switching of the logic threshold level by the internal signal VD will be described in detail later.

On the other hand, each unit circuit of the sense amplifier SA is
When the static RAM is selected in the read mode, a minute read signal output from the k + 1 selected memory cells of the memory array MARY via the Y switch YS and the complementary common data lines CD0 * to CDk * is transmitted. It is amplified and transmitted to the corresponding unit circuit of the data output buffer OB. Each unit circuit of the data output buffer OB receives the high level of the internal control signal OC to be selectively brought into an operating state, further amplifies the read signal transmitted from the sense amplifier SA, and outputs the data input / output terminals D0 to D0.
It is sent to the outside of the static RAM via Dk.
In this embodiment, the high level of the output signal output from each unit circuit of the data output buffer OB is selectively reduced by setting the internal signal VD to the high level. The level switching of the output signal by the internal signal VD will be described later in detail.

The timing generation circuit TG is provided with a chip enable signal CE which is externally supplied as a start control signal.
Based on B, the write enable signal WEB and the output enable signal OEB, the above various internal control signals are selectively formed and supplied to each part of the static RAM. In this embodiment, the timing generation circuit TG has three input circuits provided corresponding to each activation control signal, and the ratio between the logic threshold level of the first-stage logic gate of these input circuits and the power supply voltage VCC is When the internal signal VD is set to the high level, it is selectively reduced.
Regarding the switching of the logical threshold level by the internal signal VD, the data output buffer OB will be described later.
This will be described in detail in the concrete description of.

By the way, the static type R of this embodiment
The power supply voltage VCC (first power supply voltage) is supplied to the AM via the external terminal VCC, and the ground potential VSS (second power supply voltage) is supplied to the AM via the external terminal VSS. In this embodiment, the power supply voltage VCC is not particularly limited, but the first power supply voltage potential having a relatively small absolute value such as + 3.3V and the second power supply voltage having a relatively large absolute value such as + 5V. Can take electric potential, static type R
The AM includes a power supply voltage identification circuit VCLD for identifying which potential the power supply voltage VCC is. The power supply voltage identification circuit VCLD, as described later,
When the potential of C exceeds the predetermined value and becomes the second power supply voltage potential, the output signal, that is, the internal signal VD is selectively set to the effective level, that is, the high level. This internal signal VD is
As described above, it is supplied to the data input buffer IB, the X address buffer XB, the Y address buffer YB, and the timing generation circuit TG, and is used to switch the logic threshold level of the first stage logic gate, and to the data output buffer OB. Supplied and its output MO
It serves to switch the output signal level of the output stage including the SFET. The specific configuration of the power supply voltage identification circuit VCLD will be described in detail later.

FIG. 2 shows a circuit diagram of an embodiment of the power supply voltage identification circuit VCLD included in the static RAM of FIG. Further, FIG. 3 shows an operation characteristic diagram of one embodiment of the power supply voltage identification circuit VCLD of FIG.
From these figures, the power supply voltage identification circuit VC of this embodiment is
The specific configuration and operation of the LD will be described. In the circuit diagram below, the channel (back gate)
The MOSFET with an arrow attached to the part is a P-channel type (first conductivity type), and is shown separately from the N-channel type (second conductivity type) MOSFET without an arrow.

In FIG. 2, the power supply voltage identification circuit VCLD is shown.
Includes a total of four P-channel MOSFETs P1 and N-channel MOSFETs N1 to N3 provided in series between the power supply voltage VCC and the ground potential VSS. Of these, the gate of the MOSFET P1 has a ground potential VS.
By being connected to S, it is constantly turned on. In addition, the MOSFETs N1 to N3 are both diode-shaped because their gates and drains are commonly coupled. The MOSFETs N1 to N3 are designed to have a threshold voltage v1 such as 2.5V in total.

The drains of the MOSFETs P1 and N1 which are commonly connected to each other are designated as the internal node n1 and are connected to the P channel M.
The input terminal of the inverter V1 composed of the OSFET P2 and the N-channel MOSFET N4, that is, the MOSFET P2
And N4 are commonly coupled gates. The potential at the output terminal of the inverter V1, that is, the drain commonly coupled to the MOSFETs P2 and N4, becomes the output signal of the power supply voltage identification circuit VCLD, that is, the internal signal VD via the two inverters V2 and V3. The inverter V1 is designed to have a logic threshold level corresponding to the total threshold voltage v1 of the MOSFETs N1 to N3 when the power supply voltage VCC is set to a predetermined potential v2 such as + 4V.

The potential of the power supply voltage VCC is MOSFET N1.
-N3 is lower than the total threshold voltage v1 of the power supply voltage discrimination circuit VCLD, the MOSFETs N1 to N3 are turned off, and the potential of the internal node n1 is substantially the same as the power supply voltage VCC as shown in FIG. Becomes Therefore, the output signal of the inverter V1 is at a low level such as the ground potential VSS, and the output signal of the power supply voltage identification circuit VCLD, that is, the internal signal VD is also at a low level such as the ground potential VSS.

On the other hand, the potential of the power supply voltage VCC is MOSFE.
When it becomes higher than the total threshold voltage v1 of TN1 to N3,
In the power supply voltage identification circuit VCLD, MOSFETs N1 to N
3 is turned on, and the potential of the internal node n1 is clamped at about the total threshold voltage v1 of these MOSFETs. When the potential of the power supply voltage VCC reaches a predetermined potential v2 such as + 4V, the potential of the internal node n1 exceeds its logical threshold level, the output signal of the inverter V1 becomes high level, and the internal signal VD also becomes the power supply voltage. It becomes a high level like VCC.

FIG. 4 shows a circuit diagram of a first embodiment of the data input buffer IB included in the static RAM of FIG. 1, and FIG. 5 shows an operation characteristic diagram of the one embodiment. ing. Based on these figures, the specific configuration and operation of the data input buffer IB and its features will be described. It should be noted that the following description will be centered on the unit data input buffer UIB0, but the other unit data input buffers UIB1 to UIBk have the same configuration, and therefore should be analogized. Further, the following description regarding the switching of the logic threshold level of the first-stage logic gate of the unit data input buffer UIB0 by the internal signal VD will be described in the X address buffer XB and the Y address buffer YB.
It can also be applied to the input circuit of the timing generation circuit TG.

In FIG. 4, the data input buffer IB
Is a k + 1 unit circuit provided corresponding to the data input / output terminals D0 to Dk, that is, a unit data input buffer UI.
B0 to UIBk, and each of these unit data input buffers has a P-channel MOSFET P3 as represented by the unit data input buffer UIB0.
And P4 (first input MOSFET) and N-channel MOSFETs N5 and N6 (second input MOSFET).
2) NOR gate, which is a so-called first stage logic gate. One of the input terminals of these NOR gates, that is, the commonly connected gates of MOSFETs P4 and N6, is connected to the corresponding data input / output terminals D0 to Dk, and the other input terminal, that is, MOSFETs P3 and N6.
An internal control signal CS is commonly supplied to the commonly connected gates of 5. Output node of NOR gate, that is, MOS
The potentials at the commonly coupled drains of the FETs P4 and N5 and N6, after passing through the corresponding inverter V4, are used as the output signals of the unit data input buffers UIB0 to UIBk, that is, the internal input data ID0 to IDk, corresponding unit circuits of the write amplifier WA. Is supplied to.

In this embodiment, the unit data input buffers UIB0 to UIBk further include two N-channel MOSFETs N7 (first MOSF) provided in series between the output node of each NOR gate and the ground potential VSS.
ET) and N8 (second MOSFET). Of these, the output signal of the power supply voltage identification circuit VCLD, that is, the internal signal VD is commonly supplied to the gate of the MOSFET N7. The gate of the MOSFET N8 is an input MOS
It is commonly coupled to the gate of the FET N6, and consequently is coupled to the corresponding data input / output terminals D0 to Dk.

From these facts, the output signals of the unit data input buffers UIB0 to UIBk, that is, the internal input data ID0 to IDk are input from the corresponding data input / output terminals D0 to Dk when the internal control signal CS is at the high level. If the write data is at high level,
Selectively set to high level. At this time, the power supply voltage VC
When C is set to a predetermined potential v2, that is, +4 V or less, and the output signal of the power supply voltage identification circuit VCLD, that is, the internal signal VD is at a low level like the ground potential VSS, the MOSFET N7 is turned off in the unit data input buffers UIB0 to UIBk. Therefore, the logic threshold level of the NOR gate, which is the first-stage logic gate, is MOSFETP3.
And the logic threshold level V of the NOR gate, which is set according to the conductance ratio of P4 and MOSFET N6.
The ratio between LT and the absolute value of power supply voltage VCC is a relatively large value such as 1/2, as shown in FIG. As a result, the logical threshold level of the NOR gate becomes +1.65 V when the power supply voltage VCC is +3.3 V, and the unit data input buffers UIB0 to UIBk can correspond to the first power supply voltage potential having a relatively small absolute value. Becomes

On the other hand, at this time, the power supply voltage VCC is set to a predetermined potential v2, that is, +4 V or more, and the power supply voltage identification circuit VC is set.
When the output signal of the LD, that is, the internal signal VD is at a high level like the power supply voltage VCC, the unit data input buffer U
In IB0 to UIBk, the MOSFET N7 is turned on. Therefore, the logical threshold level of the NOR gate is set according to the conductance ratio of the MOSFETs P3 and P4 and the MOSFETs N6 and N7, and the ratio between the logical threshold level VLT of the NOR gate and the absolute value of the power supply voltage VCC is as shown in FIG. And has a relatively small value such as 1/3. As a result, the logical threshold level of the NOR gate becomes + 1.67V, which is almost the same as when the power supply voltage VCC is + 3.3V, when the power supply voltage VCC is + 5V, and the unit data input buffers UIB0 to UIBk are relatively absolute. The second power supply voltage potential having a large value can be dealt with.

As described above, in the static RAM of this embodiment, the logic threshold level of the first-stage logic gates of the unit data input buffers UIB0 to UIBk of the data input buffer IB, that is, the input interface condition thereof is the potential of the power supply voltage VCC. Is selectively and automatically switched according to the output signal VD of the power supply voltage identification circuit VCLD, and the static RAM can cope with a plurality of power supply voltages of different potentials without switching its internal wiring. Become.

FIG. 7 shows a circuit diagram of an embodiment of the data output buffer OB included in the static RAM of FIG. 1, and FIG. 8 shows an operation characteristic diagram of the embodiment. . Based on these figures, the data output buffer OB
The specific configuration and operation of and the characteristics thereof will be described. It should be noted that the following description will be made on the unit data output buffer UO.
Although it is possible to proceed mainly with B0, analogy with other unit data output buffers UOB1 to UOBk because they have the same configuration.

In FIG. 7, the data output buffer OB
Are k + 1 unit circuits provided corresponding to the data input / output terminals D0 to Dk, that is, unit data output buffers UO.
B0 to UOBk, each of these unit data output buffers has a power supply voltage VCC and a ground potential V as represented by the unit data output buffer UOB0.
Two N-channel type output MOSFETs N10 (first output MOS) provided in a totem pole configuration between SSs.
FET) and N11 (second output MOSFET). Of these, the gate of the output MOSFET N10 is
The inverted signal of the output signal of the NAND gate NA2 is supplied by the inverter V5, and the inverter V6 of the output signal of the NAND gate NA3 is supplied to the gate of the output MOSFET N11.
The inverted signal is supplied. Output MOSFET N10
The source, that is, the drain of the output MOSFET N11,
It is coupled to corresponding data input / output terminals D0-Dk.

The internal output data OD0 to ODk is supplied from the corresponding unit circuit of the sense amplifier SA to one input terminal of the NAND gate NA2, and the other input terminal is supplied from the internal control signal OC from the timing generation circuit TG. Are commonly supplied. Also, Nand Gate NA3
One of the input terminals has a corresponding internal output data OD0.
To ODk are respectively supplied with the inverted signals by the inverter V7, and the internal control signal O is supplied to the other input terminals.
C is commonly supplied.

In this embodiment, each of the unit data output buffers UOB0 to UOBk further has an output terminal corresponding to the power supply voltage VCC, that is, a data input / output terminal D.
P-channel MOSFET provided between 0 and Dk
P6 (third MOSFET) is included. This MOSFET
The output signal of the NAND gate NA1 is supplied to the gate of P6. The output signal of the inverter V5 is supplied to one input terminal of the NAND gate NA1, and the inverted signal of the internal signal VD from the inverter V8 is commonly supplied to the other input terminal.

From these facts, the unit data output buffers UOB0 to UOBk are selectively activated by the internal control signal OC being set to the high level, and the corresponding internal output data OD0 to ODk are set to the high level. Under this condition, a high level output signal is output to the data input / output terminals D0 to Dk. At this time, the power supply voltage VCC is set to a predetermined potential v2, that is, +4 V or less, and the power supply voltage identification circuit VC is set.
When the output signal of the LD, that is, the internal signal VD is at a low level like the ground potential VSS, the unit data output buffer U
In OB0 to UOBk, the output signal of the NAND gate NA1 becomes low level, and the MOSFET P6 is turned on. For this reason, the substantial output impedance in the output stage of each unit data output buffer becomes small, and the high level of the output signal at the data input / output terminals D0 to Dk is as shown in FIG. Raised to VCC. As a result, the power supply voltage VCC is +3.3 to the data input / output terminals D0 to Dk.
When it is set to V, a high level output of approximately + 3.3V is obtained, and the unit data input buffers UIB0 to UIBk can correspond to the first power supply voltage potential having a relatively small absolute value.

On the other hand, at this time, the power supply voltage VCC is set to a predetermined potential v2, that is, +4 V or more, and the power supply voltage identification circuit VC is set.
When the output signal of the LD, that is, the internal signal VD is at a high level like the power supply voltage VCC, the unit data output buffer U
In OB0 to UOBk, the output signal of the NAND gate NA1 becomes high level, and the MOSFET P6 is turned off. Therefore, the unit data output buffers UOB0 to UO
The substantial output impedance in the output stage of Bk becomes large, and the high level of the output signal at the data input / output terminals D0 to Dk is as shown in FIG.
It decreases by the threshold voltage Vthn of the FET N10.
As a result, at the data input / output terminals D0 to Dk, when the power supply voltage VCC is +5 V and the threshold voltage Vthn of the output MOSFET N10 is 1 V, a relatively low high level output such as approximately +4 V is obtained, and unit data output The buffers UOB0 to UOBk can cope with the second power supply voltage potential having a relatively large absolute value while achieving low power consumption.

As described above, in the static RAM of this embodiment, the output impedance of the unit data output buffers UOB0 to UOBk of the data output buffer OB, that is, its output interface condition, is the potential of the power supply voltage VCC, that is, the power supply. Voltage identification circuit VCLD
In this case, the static RAM can be selectively and automatically switched according to the output signal VD, and the static RAM can cope with a plurality of power supply voltages having different potentials without switching its internal wiring.

As shown in the above embodiment, the present invention is applied to a semiconductor device such as a static RAM having an input circuit such as a data input buffer and an output circuit such as a data output buffer. Such an effect can be obtained. That is, (1) a static RAM or the like having an input circuit such as a data input buffer and an output circuit such as a data output buffer, selectively outputs an output signal of an effective level when the absolute value of the power supply voltage exceeds a predetermined value. A power supply voltage identification circuit is provided, and the logic threshold level of the first-stage logic gate of the input circuit is selectively switched according to the output signal of this power supply voltage identification circuit, and the output signal level at the output stage of the output circuit is selectively switched. As a result, the effect that the input / output interface condition of the static RAM or the like can be selectively and automatically switched according to the potential of the power supply voltage is obtained.

(2) According to the above item (1), it is possible to obtain an effect that it is possible to realize a static RAM or the like which can handle a plurality of power supply voltages having different potentials. (3) According to the above items (1) and (2), it is possible to reduce the number of required photomasks such as a static RAM and promote cost reduction. (4) According to the above items (1) and (2), it is possible to reduce the number of types of products such as static RAM and improve the convenience.

The invention made by the inventor of the present invention has been specifically described above based on the embodiments. However, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the static RAM can have a so-called multi-bit configuration in which a plurality of bits of storage data are simultaneously input / output. In addition, the memory array MAR
Y can be divided into a plurality of sub memory arrays, and its block configuration, combination of start control signals and address signals, etc. are not restricted by this embodiment.

In FIG. 2, the power supply voltage identification circuit VCLD
The number of N-channel MOSFETs provided between the internal node n1 and the ground potential VSS can be set arbitrarily, and by inverting the logic condition of the subsequent circuit, the output signal, that is, the logic of the internal signal VD. You can also invert the levels. In FIG. 3, the level at which the internal node n1 is clamped can be set arbitrarily according to the above conditions, and the logic threshold level of the inverter V1 can also be set arbitrarily.

In FIG. 4, the unit data input buffer U
The first-stage logic gates of IB0 to UIBk can be an inverter composed of a P-channel MOSFET P5 and an N-channel MOSFET N9, as shown in FIG. 6, and various logic gates can be used. Further, as a method of switching the logic threshold level of the NOR gate serving as the first-stage logic gate, various embodiments may be considered such as providing a plurality of MOSFETs corresponding to the MOSFET N8. In FIG. 5, the logic threshold level VLT of the first-stage logic gate and the power supply voltage VCC when the internal signal VD is set to the low level or the high level.
The ratio of and can be set arbitrarily.

In FIG. 7, the unit data output buffer U
Output MOSFET N10 provided in OB0 to UOBk
And N11 are a plurality of outputs M arranged in parallel.
It can be replaced with OSFET. Further, when the sense amplifier SA at the previous stage outputs an inverted signal of the internal output data OD0 to ODk, it is not necessary to provide the inverter V7. Further, the power supply voltage identification circuit VC shown in FIG.
LD, unit data input buffer UIB0 shown in FIG.
~ UIBk and the unit data output buffers UOB0 to UOBk shown in FIG. 7, the specific configuration, the polarity and absolute value of the power supply voltage, the conductivity type of the MOSFET, and the like can take various embodiments.

In the above description, the case where the invention made by the present inventor is mainly applied to the static RAM which is the field of application which is the background of the invention has been described.
The present invention is not limited to this, for example, various memory integrated circuit devices such as a dynamic RAM provided with a data input buffer and a data output buffer, and a logic integrated circuit device such as a gate array integrated circuit equipped with these memory integrated circuit devices. Can also be applied to. The present invention can be widely applied to semiconductor devices including at least an input circuit or an output circuit. Further, it goes without saying that the present invention can be applied to only one of the input circuit and the output circuit.

[0050]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a static RAM or the like having an input circuit such as a data input buffer and an output circuit such as a data output buffer, a power supply for selectively setting the output signal to an effective level when the absolute value of the power supply voltage exceeds a predetermined value. By providing a voltage identification circuit and selectively switching the logic threshold level of the first-stage logic gate of the input circuit according to the output signal of this power supply voltage identification circuit, and also selectively switching the output signal level at the output stage of the output circuit, Since the input / output interface conditions can be selectively and automatically switched according to the potential of the power supply voltage, it is possible to realize a static RAM or the like that can handle a plurality of power supply voltages of different potentials. As a result, it is possible to reduce the number of required photomasks such as the static RAM and promote cost reduction, and reduce the number of product types such as the static RAM and improve the convenience of the user.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a static RAM to which the present invention is applied.

2 is a circuit diagram showing an embodiment of a power supply voltage identification circuit included in the static RAM of FIG.

FIG. 3 is an operational characteristic diagram showing an embodiment of the power supply voltage identification circuit of FIG.

FIG. 4 is a circuit diagram showing a first embodiment of a data input buffer included in the static RAM of FIG.

5 is an operational characteristic diagram showing an embodiment of the data input buffer of FIG.

6 is a circuit diagram showing a second embodiment of a data input buffer included in the static RAM of FIG.

7 is a circuit diagram showing an embodiment of a data output buffer included in the static RAM of FIG.

8 is an operation characteristic diagram showing an embodiment of the data output buffer of FIG. 7. FIG.

[Explanation of symbols]

MARY ... Memory array, XD ... X address decoder, XB ... X address buffer, YS ... Y
Switch, YD ... Y address decoder, YB ...
Y address buffer, WA ... write amplifier, SA
..Sense amplifier, IB ... Data input buffer, O
B ... Data output buffer, TG ... Timing generation circuit, VCLD ... Power supply voltage identification circuit. UIB0
UIBk ... Unit data input buffer. UOB0-U
OBk ... Unit data output buffer. P1 to P6 ...
・ P-channel MOSFET, N1 to N11 ... N-channel MOSFET, V1 to V8 ・ ・ Inverter, N
A1 to NA3 ... NAND gates.

Continuation of the front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical indication location H03K 19/003 Z (72) Inventor Sadayuki Morita 5-20-1 Kamimizumotocho, Kodaira-shi, Tokyo LSI Engineering Co., Ltd. (72) Inventor Takao Makiko 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hitate Super LSI Engineering Co., Ltd. (72) Inventor Yoshitaka Kinoshita 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Incorporated company Hitachi Ltd. Semiconductor Division

Claims (4)

[Claims] 1. A semiconductor device, wherein the input / output interface condition is selectively switched according to the potential of a power supply voltage. 2. The semiconductor device comprises: a power supply voltage identification circuit for identifying a potential of a power supply voltage; and an input circuit for selectively switching a logic threshold level of a first-stage logic gate according to an output signal of the power supply voltage identification circuit. 2. The semiconductor device according to claim 1, further comprising an output circuit whose output signal level is selectively switched according to an output signal of the power supply voltage identification circuit. 3. The output signal of the power supply voltage identification circuit is selectively set to a high level when the absolute value of the power supply voltage exceeds a predetermined value, and the first-stage logic gate of the input circuit is a first logic gate. Of the first conductivity type provided between the power supply voltage and the output node of the circuit, and the second input of the second conductivity type provided between the output node of the circuit and the second power supply voltage. A second conductivity type first MOSFET provided in series between the input MOSFET, the output node of the circuit and the second power supply voltage and receiving the output signal of the power supply voltage identification circuit and its gate are predetermined. A second input commonly coupled to the gates of the second input MOSFETs of
A second conductivity type MOSFET, wherein the data output buffer is a second conductivity type first output MOS provided between the first power supply voltage and the corresponding output terminal.
FET, a second output MOSFET of the second conductivity type provided between the output terminal and the second power supply voltage, and the power supply voltage identification circuit provided between the first power supply voltage and the output terminal Or a third MOSFET of a first conductivity type which is selectively turned on at the same time as the first output MOSFET on condition that the output signal is low level. Item 2. The semiconductor device according to item 2. 4. The semiconductor device is a static RAM capable of handling a first power supply voltage potential having a relatively small absolute value and a second power supply voltage potential having a relatively large absolute value, and the input circuit is 3. A data input buffer, an address buffer, and a timing generation circuit of the static RAM, and the output circuit is included in a data output buffer of the static RAM. The semiconductor device according to claim 2 or claim 3.