JPH07142575A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH07142575A JPH07142575A JP5288925A JP28892593A JPH07142575A JP H07142575 A JPH07142575 A JP H07142575A JP 5288925 A JP5288925 A JP 5288925A JP 28892593 A JP28892593 A JP 28892593A JP H07142575 A JPH07142575 A JP H07142575A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- insulating film
- hole
- integrated circuit
- transparent electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 239000011229 interlayer Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 6
- 239000010410 layer Substances 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 27
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 27
- 230000002950 deficient Effects 0.000 abstract description 5
- 235000010627 Phaseolus vulgaris Nutrition 0.000 abstract 1
- 244000046052 Phaseolus vulgaris Species 0.000 abstract 1
- 230000007547 defect Effects 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 238000005513 bias potential Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体集積回路装置に関
し、特に多層配線に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a multi-layer wiring.
【０００２】[0002]
【従来の技術】従来の半導体集積回路装置は、図２に示
すように、シリコン基板１の上に形成した絶縁膜２の上
に選択的に形成した複数の下層のアルミニウム配線３
と、このアルミニウム配線３を含む絶縁膜２の上に形成
した層間絶縁膜４と、アルミニウム配線３上の層間絶縁
膜４に形成したスルーホール５と、スルーホール５を介
して各アルミニウム配線３と互に直列に接続する複数の
上層のアルミニウム配線６とを有し、これらのアルミニ
ウム配線３，６は各スルーホール５を介して数千から数
万個直列接続して構成され、スルーホールにおけるコン
タクトの良否をチェックしていた。2. Description of the Related Art In a conventional semiconductor integrated circuit device, as shown in FIG. 2, a plurality of lower aluminum wirings 3 selectively formed on an insulating film 2 formed on a silicon substrate 1.
An interlayer insulating film 4 formed on the insulating film 2 including the aluminum wiring 3, a through hole 5 formed in the interlayer insulating film 4 on the aluminum wiring 3, and each aluminum wiring 3 via the through hole 5. And a plurality of upper aluminum wirings 6 connected in series with each other. These aluminum wirings 3 and 6 are connected in series through each through hole 5 and are configured to be connected in series. I was checking the quality of.
【０００３】[0003]
【発明が解決しようとする課題】この従来の半導体集積
回路装置では、スルーホールにおける配線の接続不良が
発生した際に、数千から数万個のスルーホールを介して
接続されるスルーホールのコンタクトチェック用素子の
接続不良箇所を特定することが非常に困難であり、その
ため、接続不良の原因の解明に手間取るという問題点が
あった。In this conventional semiconductor integrated circuit device, when a wiring connection failure occurs in a through hole, the contact of the through hole is connected through thousands to tens of thousands of through holes. It is very difficult to identify the connection failure part of the checking element, and therefore there is a problem that it takes time to elucidate the cause of the connection failure.
【０００４】[0004]
【課題を解決するための手段】本発明の半導体集積回路
装置は、半導体基板に形成した光電素子と、前記光電素
子上に形成して前記光電素子の一端に接続し且つ前記光
電素子に光を入射させるための透明電極と、前記透明電
極を含む表面に形成した絶縁膜と、前記絶縁膜に形成し
たコンタクトホールを介して前記透明電極に接続した下
層の第１の配線および前記光電素子の他端にそれぞれ接
続した下層の第２の配線と、前記第１および第２の配線
を含む表面に形成した層間絶縁膜と、前記層間絶縁膜に
形成したスルーホールを介して前記第１の配線と第２の
配線とを接続し前記層間膜の上に形成した上層の第３の
配線とを有する。A semiconductor integrated circuit device according to the present invention includes a photoelectric element formed on a semiconductor substrate, a photoelectric element formed on the photoelectric element and connected to one end of the photoelectric element, and light is applied to the photoelectric element. A transparent electrode for incidence, an insulating film formed on the surface including the transparent electrode, a first wiring in the lower layer connected to the transparent electrode through a contact hole formed in the insulating film, and the photoelectric element The second wiring in the lower layer connected to each end, the interlayer insulating film formed on the surface including the first and second wirings, and the first wiring through the through hole formed in the interlayer insulating film. And an upper third wiring formed on the interlayer film and connected to the second wiring.
【０００５】[0005]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【０００６】図１（ａ），（ｂ）は本発明の一実施例を
示す半導体チップの平面図およびＡ−Ａ′線断面図であ
る。1A and 1B are a plan view and a sectional view taken along the line AA 'of a semiconductor chip showing an embodiment of the present invention.
【０００７】図１（ａ），（ｂ）に示すように、ｎ型の
シリコン基板１の一主面に選択的にｐ+ 型領域７を形成
した後、ｐ+ 型領域７の内側にｐ- 型領域８を形成し、
更にｐ- 型領域８内にｎ型領域９を形成し、ｎ型領域９
の表面にＩＴＯ（Ｉｎｄｉｕｍ Ｔｉｎ Ｏｘｉｄｅ）
膜等の透明電極１０を選択的に形成してアバランシェフ
ォトダイオードを形成する。次に、このアバランシェフ
ォトダイオードを含むシリコン基板１の表面に絶縁膜２
を形成して選択的にエッチングし透明電極１０上の開孔
部１１およびｐ+ 型領域７上のコンタクトホール１２を
形成する。As shown in FIGS. 1A and 1B, after a p + type region 7 is selectively formed on one main surface of the n type silicon substrate 1, ap + type region 7 is formed inside the p + type region 7. -Forming the mold region 8,
Further, an n-type region 9 is formed in the p − -type region 8 and the n-type region 9 is formed.
On the surface of ITO (Indium Tin Oxide)
A transparent electrode 10 such as a film is selectively formed to form an avalanche photodiode. Next, the insulating film 2 is formed on the surface of the silicon substrate 1 including the avalanche photodiode.
Is formed and selectively etched to form an opening 11 on the transparent electrode 10 and a contact hole 12 on the p + type region 7.
【０００８】次に、開孔部１１およびコンタクトホール
１２を含む絶縁膜２の上にアルミニウム膜を堆積してパ
ターニングし、開孔部１１の透明電極１０およびコンタ
クトホール１２のｐ+ 型領域７にそれぞれ接続するアル
ミニウム配線３ａ，３ｂを形成する。Next, an aluminum film is deposited and patterned on the insulating film 2 including the opening 11 and the contact hole 12, and the transparent electrode 10 of the opening 11 and the p + type region 7 of the contact hole 12 are formed. Aluminum wirings 3a and 3b connected to each other are formed.
【０００９】次に、アルミニウム配線３ａ，３ｂを含む
絶縁膜２の上に層間絶縁膜４を堆積し、アルミニウム配
線３ａ，３ｂ上の層間絶縁膜４にスルーホール５を形成
する。次に、スルホール５を含む層間絶縁膜４の上にア
ルミニウム膜を堆積してパターニングし、スルーホール
５を介してアルミニウム配線３ａとアルミニウム配線３
ｂとの間を接続するアルミニウム配線６を形成する。Next, an interlayer insulating film 4 is deposited on the insulating film 2 including the aluminum wirings 3a and 3b, and a through hole 5 is formed in the interlayer insulating film 4 on the aluminum wirings 3a and 3b. Next, an aluminum film is deposited and patterned on the interlayer insulating film 4 including the through holes 5, and the aluminum wiring 3 a and the aluminum wiring 3 are provided through the through holes 5.
An aluminum wiring 6 is formed to connect with b.
【００１０】このように、アルミニウム配線３ａ，３ｂ
を介してアルミニウム配線６の両端に並列に接続された
アバランシェフォトダイオードを有する素子を直列に多
数個を接続してスルーホールにおける接続の良否をチェ
ックするデバイスを構成する。In this way, the aluminum wirings 3a, 3b
A large number of elements having avalanche photodiodes connected in parallel to both ends of the aluminum wiring 6 through are connected in series to form a device for checking the quality of the connection in the through hole.
【００１１】ここで、アルミニウム配線６とアルミニウ
ム配線３ａ又はアルミニウム配線３ｂとを接続するスル
ーホール５のいずれかで接続不良を発生すると、アルミ
ニウム配線３ａとアルミニウム配線３ｂとの間で断線を
生ずるが、同時にアバランシェフォトダイオードに逆バ
イアスの電位が印加され、このアバランシェフォトダイ
オードに光が照射されると断線していたアルミニウム配
線３ａとアルミニウム配線３ｂ間が導通する。従って、
配列されたアバンシェフォトダイオードを順次光ビーム
で走査し、光照射で断線が回復する箇所を見付けること
で容易に断線箇所を捜し当てることができる。Here, if a connection failure occurs in any of the through holes 5 connecting the aluminum wiring 6 and the aluminum wiring 3a or the aluminum wiring 3b, a disconnection occurs between the aluminum wiring 3a and the aluminum wiring 3b. At the same time, a reverse bias potential is applied to the avalanche photodiode, and when the avalanche photodiode is irradiated with light, the broken aluminum wiring 3a and aluminum wiring 3b are electrically connected. Therefore,
The arrayed avanche photodiodes are sequentially scanned with a light beam, and the location where the disconnection is recovered by light irradiation is found, so that the disconnection location can be easily located.
【００１２】なお、アルミニウム配線３ａ，３ｂ，６の
代りに不純物を含む多結晶シリコン膜又はタングステン
やモリブデン等の高融点金属膜又はこれらのシリサイド
膜からなる配線を用いても良く、３層以上の多層配線構
造を採用しても良い。Instead of the aluminum wirings 3a, 3b and 6, a polycrystalline silicon film containing impurities, a refractory metal film such as tungsten or molybdenum, or a wiring made of these silicide films may be used, and three or more layers may be used. A multilayer wiring structure may be adopted.
【００１３】また、アバランシェフォトダイオードの代
りにフォトトランジスタや光導電体素子等を用いること
もできる。Further, a phototransistor, a photoconductor element or the like can be used instead of the avalanche photodiode.
【００１４】[0014]
【発明の効果】以上説明したように本発明は、スルーホ
ールチェック用素子にスルーホール接続不良箇所を検出
するための光電素子を並列に接続することにより、光ビ
ームを光電素子に順次照射してスルーホール接続不良箇
所を容易に検出することができ、スルーホール接続不良
の原因を解明するのが容易になるという効果を有する。As described above, according to the present invention, a photoelectric element for detecting a defective portion of through-hole connection is connected in parallel to a through-hole checking element so that a light beam is sequentially applied to the photoelectric element. This has an effect that a defective portion of the through-hole connection can be easily detected, and the cause of the defective connection of the through-hole can be easily understood.
【図１】本発明の一実施例を示す半導体チップの平面図
およびＡ−Ａ′線断面図。FIG. 1 is a plan view and a cross-sectional view taken along the line AA ′ of a semiconductor chip showing an embodiment of the present invention.
【図２】従来の半導体集積回路装置の一例を示す半導体
チップの平面図およびＢ−Ｂ′線断面図。FIG. 2 is a plan view and a cross-sectional view taken along the line BB ′ of a semiconductor chip showing an example of a conventional semiconductor integrated circuit device.
１ シリコン基板 ２ 絶縁膜 ３ａ，３ｂ，６ アルミニウム配線 ４ 層間絶縁膜 ５ スルーホール ７ ｐ+ 型領域 ８ ｐ- 型領域 ９ ｎ型領域 １０ 透明電極 １１ 開孔部 １２ コンタクトホール1 Silicon Substrate 2 Insulating Films 3a, 3b, 6 Aluminum Wiring 4 Interlayer Insulating Film 5 Through Hole 7 p + Type Region 8 p − Type Region 9 n Type Region 10 Transparent Electrode 11 Open Hole 12 Contact Hole
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 27/14 31/10 7210−4Ｍ Ｈ０１Ｌ 27/14 Ｚ 31/10 Ｚ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical display location H01L 27/14 31/10 7210-4M H01L 27/14 Z 31/10 Z
Claims (2)
光電素子上に形成して前記光電素子の一端に接続し且つ
前記光電素子に光を入射させるための透明電極と、前記
透明電極を含む表面に形成した絶縁膜と、前記絶縁膜に
形成したコンタクトホールを介して前記透明電極に接続
した下層の第１の配線および前記光電素子の他端にそれ
ぞれ接続した下層の第２の配線と、前記第１および第２
の配線を含む表面に形成した層間絶縁膜と、前記層間絶
縁膜に形成したスルーホールを介して前記第１の配線と
第２の配線とを接続し前記層間膜の上に形成した上層の
第３の配線とを有することを特徴とする半導体集積回路
装置。1. A photoelectric device formed on a semiconductor substrate, a transparent electrode formed on the photoelectric device, connected to one end of the photoelectric device and allowing light to enter the photoelectric device, and the transparent electrode. An insulating film formed on the surface, a lower first wiring connected to the transparent electrode via a contact hole formed in the insulating film, and a second lower wiring connected to the other end of the photoelectric element, respectively. The first and second
Of the upper layer formed on the interlayer film by connecting the first wiring and the second wiring through the through hole formed in the interlayer insulating film and the interlayer insulating film formed on the surface including the wiring of 3. A semiconductor integrated circuit device having wiring 3.
ド，フォトトランジスタ又は光導電体素子のいずれかか
らなる請求項１記載の半導体集積回路装置。2. The semiconductor integrated circuit device according to claim 1, wherein the photoelectric element is any one of an avalanche photodiode, a phototransistor, and a photoconductor element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5288925A JP2570993B2 (en) | 1993-11-18 | 1993-11-18 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5288925A JP2570993B2 (en) | 1993-11-18 | 1993-11-18 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07142575A true JPH07142575A (en) | 1995-06-02 |
| JP2570993B2 JP2570993B2 (en) | 1997-01-16 |
Family
ID=17736583
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5288925A Expired - Lifetime JP2570993B2 (en) | 1993-11-18 | 1993-11-18 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2570993B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6664573B2 (en) * | 2001-09-26 | 2003-12-16 | Samsung Electronics Co, Ltd. | Avalanche photodiode |
| CN117672882A (en) * | 2022-08-22 | 2024-03-08 | 中芯国际集成电路制造(北京)有限公司 | Microdefect measurement structure and measurement method |
-
1993
- 1993-11-18 JP JP5288925A patent/JP2570993B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6664573B2 (en) * | 2001-09-26 | 2003-12-16 | Samsung Electronics Co, Ltd. | Avalanche photodiode |
| CN117672882A (en) * | 2022-08-22 | 2024-03-08 | 中芯国际集成电路制造(北京)有限公司 | Microdefect measurement structure and measurement method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2570993B2 (en) | 1997-01-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19960903 |