JPH07146330A - Burn-in testing device - Google Patents

Abstract

PURPOSE:To accurately judge the quality of a device to be measured without requiring any complicated constitution. CONSTITUTION:Clocks (CLK), etc., are impressed upon each device DUT1-DUTn to be measured on a burn-in board 3 from a timing generating circuit 12 through a driver 13. Signals outputted from the (-) output terminal of each device DUT1-DUTn on the board 3 are inputted to a data selector 15 through an edge connector 4. The data selector 15 successively scans the output terminals of the devices DUT1-DUTn. A judgement circuit 16 judges the quality of the devices DUT1-DUTn by comparing signals obtained as a result of scanning with a prefixed reference value. The judgement results of the circuit 16 are written in a fault RAM17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burn-in test apparatus, and more particularly to a burn-in test apparatus capable of performing highly reliable burn-in.

[0002]

2. Description of the Related Art A burn-in system has been conventionally used as a system for carrying out a screening test for removing semiconductor devices having inherent defects and latent failure factors. The burn-in test apparatus includes a burn-in board on which a plurality of devices under test (hereinafter referred to as DUT (device under test)) such as ICs can be mounted, and performs screening by applying temperature stress and voltage stress to the DUT. . The burn-in test apparatus can be roughly classified into a static burn-in test apparatus, a clock burn-in test apparatus, and a dynamic burn-in test apparatus, depending on the method of voltage and signal application. The outline of these burn-in test apparatuses will be described below with reference to FIGS. 3, 4, and 5.

FIG. 3 is a block diagram of a static burn-in test apparatus. The static burn-in test apparatus includes a burn-in board 3, a power supply 10, and the like. The burn-in board 3 has a plurality of sockets 2,
It is provided with a pull-up resistor 6, an edge connector 4 and the like, and is installed in a constant temperature bath while holding a plurality of DUTs 1 to n.
The power supply 10 is installed outside the constant temperature bath. The voltage V from the power supply 10 is supplied to the power supply terminals of the DUTs 1 to n through the edge connector 4.
cc is applied, and the voltage Vcc is applied to the I / O pins other than the power supply terminals of the DUTs 1 to n through the pull-up resistor 6. The DUTs 1 to n are screened in this state, and a DUT having an initial defect or the like can be found. This static burn-in test apparatus can perform screening at low cost when the DUT is a device having a self-diagnosis function, such as a logic integrated circuit such as a microcomputer or ASIC.

FIG. 4 is a block diagram of a clock type burn-in test apparatus. The clock-type burn-in test apparatus includes a timing generation circuit 12 that generates a control signal to be applied to a clock (CLK) terminal and a reset (RESET) input terminal of the DUTs 1 to n, a driver 13, a control unit 11, and the like. The control unit 11 includes a driver 13 and a power source 10.
And the control of the pulse width, delay time, period, etc. of the control signal generated by the timing generation circuit 12. The control signal generated by the timing generation circuit 12 is supplied by the driver 13 via the edge connector 4 to the clock terminals and reset terminals of the DUTs 1 to n.

FIG. 5 is a block diagram of a dynamic burn-in test apparatus. The dynamic burn-in tester applies a predetermined pattern of input signals to all of the input terminals of the DUTs 1 to n and compares the pattern appearing at the output terminals of the DUTs 1 to n with the expected output pattern to determine whether the DUT is good or bad. The judgment is made. In this figure, the control unit 11 controls the operation of each unit. The timing generation circuit 12 supplies a predetermined timing signal to the pattern generation section 20 and the format control section 21. The pattern generator 20 includes DUT1 to DUT1.
a vector RAM for storing a pattern signal sequence applied to n,
An address counter and the like are provided to generate a predetermined pattern signal. The format control unit 21 generates timing signals such as RZ and NRZ required when actually applying to the DUT 1 to n, based on the timing signal from the timing generation circuit 12 and the pattern signal from the pattern generation unit 20. is there. The driver 13 converts the generated timing signal into a predetermined voltage and current level required for the DUT 1 to n, and D via the edge connector 4.
The timing signals are simultaneously supplied to the UTs 1 to n.

The comparator 18 compares the DUT output value output from the DUT1 to n with the expected output value stored in the vector RAM section, and outputs an error signal if they do not match. The fault latch 22 latches the error signal and outputs it to the fault RAM 17. The fault RAM 17 stores the error signal together with the address. According to the dynamic burn-in test apparatus configured as described above, it becomes possible to monitor the states of the DUTs 1 to n in real time for each pattern step.

[0007]

However, the above-mentioned conventional burn-in test apparatus has the following problems.

The static burn-in test apparatus of FIG. 3 and the clock burn-in test apparatus of FIG. 4 both apply a DC voltage and a control signal to the DUT unilaterally in a high temperature atmosphere, and output signals from the DUT. I'm not watching at all. Therefore, even if a defect such as damage of the edge connector 4 or damage to the contact pin of the socket 2 for mounting the DUT occurs due to the repeated burn-in test, such a defect cannot be detected at all. Therefore, the voltage and the signal to be applied to the DUT are not applied at all, and the DUT having a potential failure factor is present.
However, there was a problem that they were shipped to the market without being subjected to burn-in screening. That is, the device configuration can be simplified in a device that does not detect the output signal of the DUT at all, such as a conventional static type or clock type burn-in test device, but it is difficult to accurately determine the quality of the DUT. there were.

Since the dynamic burn-in test apparatus of FIG. 5 compares the output signal of the DUT with the output expected value, the above-mentioned problem does not occur. However, the dynamic burn-in test device has a more complicated device configuration than the static burn-in test device and the clock burn-in test device, and the device price is incomparably high. Also, since the wiring pattern on the burn-in board 3 is complicated, one burn-in board 3
There is a problem that the number of DUTs that can be mounted on the device is reduced and the processing capability is reduced. That is, in a device that detects all output signals of the DUT, such as a dynamic burn-in test device, the quality of the DUT can be accurately determined, but there is a problem that the device configuration becomes extremely complicated.

[0010]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to accurately judge the quality of a device under test in a burn-in test apparatus without requiring a complicated apparatus configuration and to improve processing efficiency.

[0011]

The invention according to claim 1 is
In a burn-in test apparatus for performing a screening test of a plurality of devices under test mounted on a burn-in board, a control signal applying means for applying a control signal to the devices under test, and a plurality of output pins of the device under test. Comparing means for comparing the scanned signal with a predetermined reference signal while sequentially scanning the signals output from some of the output pins, and the quality of the device under test based on the comparison result by the comparing means. The burn-in test apparatus is provided with a determination means for determining.

According to a second aspect of the invention, the comparing means is
2. The burn-in test apparatus according to claim 1, wherein the signals output from the device under test are sequentially scanned in synchronization with the cycle of the control signal.

According to a third aspect of the present invention, in a burn-in test apparatus for performing a screening test of a plurality of devices under test mounted on a burn-in board, some output pins of the plurality of output pins of the device under test are provided. While sequentially scanning the signal output from, comparing means for comparing the scanned signal and a predetermined reference signal, and a determining means for determining the quality of the device under measurement based on the comparison result by the comparing means. The burn-in test apparatus is characterized by being provided.

[0014]

According to the present invention, the control signal applying means applies the control signal to the plurality of devices under test on the burn-in board. The comparing means sequentially scans the signals output from some output pins of the plurality of output pins of the device under test, and compares the scanned signals with a predetermined reference signal. Here, when there is an abnormality in the device under measurement or the like, the output signal differs from the predetermined reference signal. The judging means judges pass / fail of the device under measurement based on the comparison result by the comparing means.

In the present invention, the output signal is compared with the reference signal only for some of the output pins of the device under test. Therefore, it is possible to judge the quality of the device under measurement or the like without requiring a complicated device configuration. Further, since it is only necessary to detect a part of the output pins of the device under test, the wiring pattern on the burn-in board can be simplified, and more devices under test can be mounted on one burn-in board. It becomes possible. That is, the processing efficiency of the burn-in test apparatus is improved.

According to the second aspect of the invention, the comparison means sequentially scans the signals output from the device under test in synchronization with the cycle of the control signal. That is, since the cycle of the control signal and the cycle of scanning in the comparing means are synchronized, the same clock signal can be used to determine both cycles. Therefore, the circuit configuration can be simplified.

According to another aspect of the invention, the comparing means sequentially scans the signals output from some output pins of the plurality of output pins of the device under test, and sequentially scans the signals with the scanned signals. Compare with a defined reference signal. The judging means judges pass / fail of the device under measurement based on the comparison result by the comparing means. According to the present invention, since it is not necessary to apply a control signal such as a clock to the device under test, it is possible to determine the quality of the device under test with a simpler configuration.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A burn-in test apparatus according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a burn-in test apparatus according to the first embodiment of the present invention. This burn-in test device includes a burn-in board 3, a power supply 10, a control unit 11,
The timing generation circuit 12, the driver 13, the address counter 14, the data selector 15, the determination circuit 16, the fault RAM 17, and the like.

The burn-in board 3 has a plurality of sockets 2 to which DUTs can be attached, edge connectors 4, pull-up resistors 5, and the like. Edge connector 4 is Vcc (power supply)
It has a terminal, a GND (ground) terminal, a CLK (clock) terminal, a RESET terminal, and n DUT output terminals. Each of the output terminals of the DUTs 1 to n is connected to each of the DUT output terminals of the edge connector 4. That is, one of the plurality of output terminals of each DUT is wired to the edge connector 4. Each DU
It is not necessary to wire all of the output terminals of T to the edge connector 4, and it is sufficient to wire only some of the output terminals of each DUT to the edge connector 4. Therefore, the wiring pattern on the burn-in board 3 is It can be simplified.

The power supply 10 is connected to DC via the edge connector 4.
The voltage Vcc is supplied to each DUT 1-n. The timing generating circuit 12 is for generating control signals such as a clock and a reset supplied to the DUT. Driver 1
Reference numeral 3 converts the control signal into a predetermined voltage level and supplies it to the DUTs 1 to n via the edge connector 4. The clock signal CLK is a pulse having a high frequency of 100 KHz to several MHz and is used as a clock for operating the DUT. When the DUT is a microcomputer or the like having a test ROM, a test circuit, etc. inside, the reset signal RESET having a cycle long enough to complete the test operation inside the DUT in addition to the clock signal CLK
Supplied to T. In this case, it is possible to obtain the same effect as the dynamic burn-in by the test operation of the DUT itself.

Address counter 14, data selector 1
5, the determination circuit 16, and the fault RAM 17 are for confirming whether or not the signal is normally output from each DUT. The address counter 14 counts the reset signal from the timing generation circuit 12 and supplies it to the data selector 15 and the fault RAM 17. The data selector 15 sequentially scans n DUT output signals in accordance with the count value of the address counter 14 and outputs them to the determination circuit 16. Judgment circuit 16
Is for determining whether or not the burn-in test is normally performed based on the input DUT signal. The fault RAM 17 is a memory for storing the determination result of the determination circuit 16.

The operation of the burn-in test apparatus configured as described above will be described. The timing generation circuit 12 generates control signals such as clock and reset, and supplies them to the input terminals of the DUTs 1 to n via the driver 13. This allows
The DUTs 1 to n are in the operating state. Since a common control signal is input to each of the DUTs 1 to n, the same DUT output signal is output from the output terminal of each DUT if the DUT or the like is operating normally.

The address counter 14 counts the reset signal from the timing generation circuit 12, and the DUT1 to DUT1.
Counting up or counting down is repeated with the number n of n as the final value. The count value of the address counter 14 is input to the data selector 15 and the fault RAM 17 as an address signal.

The data selector 15 sequentially scans the DUT output signals of the DUTs 1 to n according to the address signal and sends the scanned DUT output signals to the decision circuit 16. Burn-in board 3 with one data selector 15
The time required to scan the output signals of all the above DUTs 1 to n is DUT number n × reset signal cycle time. If the number of DUTs on one burn-in board 3 is 2
It is assumed that the number of burn-in boards 3 is 0, the number of burn-in boards 3 is 60, and the reset signal period is 5 seconds. In this case, since the total number of DUTs is 1200, 1200 x 5 seconds = 60
It takes 00 seconds (1 hour 40 minutes). Normally, the burn-in test time is about 40 hours, and therefore 1200 DUTs can be sufficiently judged in this time.

The determination circuit 16 compares the DUT output signal with a predetermined reference value (high level, low level, pulse, etc.), and outputs a fault signal to the fault RAM 17 when the two differ. Fault RAM 17 writes the fault signal to memory along with the address. Therefore, by referring to the contents of the fault RAM 17,
It is possible to easily grasp the DUT in which an error has occurred. That is, after the burn-in is completed, the fault RAM 17 is read out, and the defective DUT can be found based on the address written together with the fault signal.

The burn-in test apparatus according to this embodiment is similar to the conventional dynamic burn-in test apparatus in the DU.
Instead of detecting all the T output signals, only a part of the output signals is detected to judge the quality of the DUT.
In general, it is often possible to determine whether or not the DUT is operating normally by only detecting a part of the output signal of the DUT. Therefore, according to the burn-in test apparatus of the present embodiment, it is possible to accurately judge the quality of the DUT without requiring a complicated apparatus configuration. Further, since it is necessary to detect only a part of the output pins of the DUT, the wiring pattern on the burn-in board 3 can be simplified and more DUTs can be mounted on one burn-in board 3. That is, the processing efficiency is significantly improved.

Next, a burn-in test apparatus according to the second embodiment of the present invention will be described. FIG. 2 is a block diagram of the burn-in test apparatus according to this embodiment. This burn-in test apparatus is of a so-called static type and does not include a circuit (driver or the like) for supplying a control signal such as a clock or reset. Therefore, the edge connector 4 of the burn-in board 3 is connected to the power source Vcc and GN.
Only the D and n DUT output terminals are provided. Power supply 10, control unit 11, timing generation circuit 1
2, the address counter 14, the data selector 15, the decision circuit 16 and the like are constructed in substantially the same manner as in the first embodiment. The comparator 18 compares the DUT output voltage of the DUTs 1 to n with a predetermined reference voltage. The display unit 19 is for displaying the determination result of the determination circuit 16, and is composed of an LED, a liquid crystal, a CRT and the like.

In the burn-in test apparatus constructed as described above, the power supply 10 applies a predetermined voltage Vcc to the DUTs 1 to n. If each DUT is operating normally, D
The UT output voltage becomes substantially equal to the reference voltage. When some abnormality occurs in the DUT, the DUT output voltage deviates from the reference voltage. The comparator 18 compares each DUT output voltage with the reference voltage, and outputs the comparison result to the data selector 15 as a comparator output voltage. The data selector 15 sequentially scans the n comparator output voltages and sends them to the determination circuit 16. The determination circuit 16 compares the output voltage of the comparator with a predetermined reference voltage to determine the quality of each DUT 1-n. The result of this determination is displayed by the display circuit 19.

Therefore, by referring to the display result of the display circuit 19, it is possible to immediately determine which one of the DUTs 1 to n has an abnormality. Since the burn-in test apparatus according to the present embodiment employs the static method, the scan speed in the data selector 15 can be set arbitrarily without being restricted by the clock or the like. Therefore, since the burn-in test apparatus can perform scanning at a higher speed than that of the clock method, it is possible to inspect the socket 2 for damage or the like in a short time.

[0031]

As described above, according to the present invention, the signal output from only a part of the output terminals of the device under test (DUT) is compared with a predetermined reference signal. By doing so, the quality of the device under test is determined. Since it is not necessary to monitor all the output terminals of the device under test, it is possible to judge the quality of the device under test without requiring a complicated apparatus configuration. Further, since the wiring on the burn-in board is simplified, a large number of DUTs can be mounted on one burn-in board, and the processing capacity can be improved. further,
There is also an advantage that the burn-in test apparatus according to the present invention can be realized by making a minimum improvement to the conventional static burn-in apparatus and clock burn-in apparatus, and the existing apparatus can be effectively used.

[Brief description of drawings]

FIG. 1 is a block diagram of a burn-in test apparatus according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a burn-in test apparatus according to a second embodiment of the present invention.

FIG. 3 is a block diagram of a conventional static burn-in test apparatus.

FIG. 4 is a block diagram of a conventional clock-type burn-in test apparatus.

FIG. 5 is a block diagram of a conventional dynamic burn-in test apparatus.

[Explanation of symbols]

 3 Burn-in Board 12 Timing Generation Circuit (Control Signal Applying Means) 13 Driver (Control Signal Applying Means) 15 Data Selector (Comparison Means) 16 Judgment Circuit (Judgment Means) 18 Comparator (Judgment Means)

Claims (3)

[Claims] 1. A burn-in test apparatus for performing a screening test of a plurality of devices under test mounted on a burn-in board, comprising: control signal applying means for applying a control signal to the plurality of devices under test; Comparing means for comparing the scanned signal with a predetermined reference signal while sequentially scanning the signals output from some of the plurality of output pins, and based on the comparison result by the comparing means, A burn-in test apparatus, comprising: a determination unit that determines the quality of a device under test. 2. The burn-in test apparatus according to claim 1, wherein the comparing means sequentially scans the signals output from the device under test in synchronization with the cycle of the control signal. 3. A burn-in test apparatus for performing a screening test on a plurality of devices under test mounted on a burn-in board, wherein signals output from some of the plurality of output pins of the device under test are output. While sequentially scanning, comparing means for comparing the scanned signal and a predetermined reference signal, and a determining means for determining the quality of the device under test based on the comparison result by the comparing means, Burn-in test equipment.