JPH0714920A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] Regarding the method of forming via holes, reduce the damage to the underlying wiring. Constitution: In the step of forming a via hole 9 penetrating the interlayer insulating layer 6 covering the lower wiring 3 having the diffusion blocking layer 4 on the upper surface to expose the diffusion blocking layer 4, etching for forming the via hole 9 in the interlayer insulating layer 6 In the above, a step of providing a stopper layer 5 acting as an etch stopper on the upper surface of the diffusion blocking layer 4, a step of forming a via hole upper portion 9a which penetrates the interlayer insulating layer 6 and exposes the stubber layer 5 using the resist mask 7, Then, the resist mask 7 is removed, and then the stopper layer 5 exposed on the bottom surface of the via hole upper portion 9a is removed by etching using the interlayer insulating layer 6 as a mask and the diffusion stopper layer 4 as an etch stopper. And exposing and forming via holes 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a via hole with less damage to lower layer wiring.

In manufacturing a semiconductor device, a via hole is frequently formed in an interlayer insulating layer because it is electrically connected to a lower layer wiring covered with the interlayer insulating layer. For example,
In an FPGA (Field Programmable Gate Array), a via hole is formed at each intersection of two sets of wiring lines which are composed of a large number of parallel wiring lines and are orthogonal to each other, and an antifuse made of an amorphous silicon thin film is formed.

However, etching at the time of forming such a via hole may damage the lower layer wiring exposed on the bottom surface of the via hole, impair the reliability of the contact, and deteriorate the reliability of the semiconductor device.

Therefore, there is a strong demand for a method of opening a via hole without damaging the lower layer wiring.

[0005]

2. Description of the Related Art A conventional method of forming a via hole for connecting to a lower layer wiring covered with an interlayer insulating layer will be described with reference to an embodiment.

FIG. 3 is a sectional process drawing of a conventional embodiment,
The cross section of the anti-fuse part of PGA is shown. First,
Referring to FIG. 3A, an oxide film 2 made of silicon oxide is formed on the surface of a semiconductor substrate 1 on which a semiconductor element (not shown) is formed.

Next, on the oxide film 2, an Al layer as a material of the lower wiring 3 and a titanium nitride layer as a diffusion blocking layer 4 are sequentially deposited. Then, the titanium nitride layer and the Al layer are sequentially etched and patterned by photoetching to form the lower wiring 3. The lower layer wiring 3 is one wiring forming the antifuse portion of the FPGA, for example, an X wiring. Here, the diffusion blocking layer 4 provided on the upper surface of the lower layer wiring 3 functions as a diffusion barrier for preventing a diffusion reaction between Al of the lower layer wiring 3 and silicon which is a contact material.

Then, a SiO ₂ layer having a flat surface which covers the lower wiring 3 and the diffusion blocking layer 4 is deposited on the entire surface of the substrate 1 as an interlayer insulating layer 5. Next, a resist mask 7 having an opening 8 which defines a region where an antifuse is to be formed is formed by photolithography.

Next, the interlayer insulating layer 5 is RIE (reactive ion etching) using the resist mask 7, and FIG.
Referring to (b), a via hole 9 penetrating the interlayer insulating layer 5 and exposing the diffusion blocking layer 4 is formed on the bottom surface.

Next, referring to FIG. 3C, the resist mask 7 is ashed and removed using oxygen plasma. Next, an amorphous silicon thin film is deposited by CVD to cover the inner surface of the via hole 9 and the interlayer insulating layer 5, and the amorphous thin film 1 is deposited.
Form 0. Next, referring to FIG. 3D, the amorphous thin film 10 covering the inner surface of the via hole 9 and the amorphous thin film 10 deposited on the interlayer insulating layer around the via hole 9 are left, and the others on the interlayer insulating layer 5 are left. The amorphous thin film deposited in the region is removed by photoetching.

Next, the titanium nitride film and the upper wiring 12
The material Al is sequentially deposited and patterned to form the upper wiring 12. The upper layer wiring 12 is usually a Y wiring orthogonal to the lower layer wiring 3.

In this way, an antifuse is formed in which the upper layer wiring 12 and the lower layer wiring 3 are opposed to each other with the amorphous thin film 10 made of amorphous silicon sandwiched between them on the bottom surface of the via hole 9.
The FPGA is manufactured.

However, in forming the via hole penetrating the interlayer insulating layer 5 in the above-described step of forming the via hole, since the interlayer insulating layer 5 made of SiO ₂ is etched by using the reaction gas containing fluorine, the lower layer wiring 3 The diffusion blocking layer 4 made of titanium nitride provided on the upper surface is over-etched and thinned.

As a result, the function of the diffusion barrier deteriorates, causing a diffusion reaction between the lower layer wiring 3 and the silicon thin film 10, increasing the leak current of the antifuse, and impairing the reliability of the antifuse.

When the resist mask 7 is removed after the via hole 9 is formed, the exposed surface of the diffusion blocking layer 4 exposed on the bottom surface of the via hole is altered, and is oxidized by removal by ashing, for example, and the surface of the diffusion blocking layer 4 is removed. An altered layer is formed on the surface. Therefore, the altered layer is sandwiched between the lower layer wiring 3 and the amorphous thin film 10, which changes the write voltage of the antifuse and increases the residual resistance of the antifuse.

[0016]

As described above, in the conventional via hole forming method, when the via hole is formed in the interlayer insulating layer by using RIE, the diffusion blocking layer provided on the lower wiring is Since it appears on the bottom, it is etched and thinned, and the diffusion barrier becomes smaller, which deteriorates reliability.

Further, since the resist mask is removed in a state where the surface of the diffusion blocking layer is exposed at the bottom of the via hole, an altered layer is formed on the surface of the diffusion blocking layer, resulting in deterioration of device characteristics.

According to the present invention, by providing the stopper layer on the diffusion blocking layer, the diffusion blocking layer is prevented from being etched when the via hole is formed, and the diffusion blocking layer is not exposed when the resist mask is removed. An object of the present invention is to provide a method of manufacturing a semiconductor device having high reliability and excellent electrical characteristics by preventing alteration of the surface of the diffusion blocking layer.

[0019]

1 and 2 are cross-sectional process diagrams of an embodiment of the present invention, showing a process of forming an antifuse portion of an FPGA.

In order to solve the above problems, FIG. 1 and FIG.
With reference to FIG. 1, the first structure of the present invention has a diffusion blocking layer 4 made of titanium nitride, tungsten titanium, or tungsten nitride on the upper surface, and a lower layer wiring 3 made of aluminum or an aluminum alloy. Of a semiconductor device, and a step of forming a via hole 9 penetrating an interlayer insulating layer 6 which covers the lower wiring 3 and exposes the diffusion blocking layer 4 on the substrate 1. A step of providing a stopper layer 5 made of a refractory metal silicide on the upper surface of the diffusion blocking layer 4,
Using the step of depositing the interlayer insulating layer 6 made of silicon oxide to cover the lower layer wiring 3 and the resist mask 7 provided on the interlayer insulating layer 6 and having the opening 8 defining the via hole 9, A step of opening a via hole upper portion 9a penetrating the interlayer insulating layer 6 and exposing the stopper layer 5, and then a step of removing the resist mask 7,
The stopper layer 5 exposed on the bottom surface of the via hole upper portion 9a
And removing the diffusion blocking layer 4 by etching using the interlayer insulating layer 6 as a mask to expose the diffusion blocking layer 4 as an etch stopper, and forming a via hole 9. The second structure is the method for manufacturing a semiconductor device according to the first structure, wherein in the method for manufacturing a semiconductor device according to claim 1, the inner surface of the via hole 9 is covered and the amorphous silicon is formed on the interlayer insulating layer 6. A step of depositing an amorphous thin film 10 made of any one of a thin film, an amorphous carbon thin film, and a silicon nitride film (ONO film) having a silicon oxide film above and below, and an upper wiring 12 on the amorphous thin film 10. And forming the amorphous thin film 10 sandwiched between the lower layer wiring 3 and the upper layer wiring 12 as an antifuse.

[0021]

In the structure of the present invention, referring to FIG. 1A, the diffusion blocking layer 4 is provided on the upper surface of the lower wiring 3 and the stopper layer 5 is provided on the uppermost surface.

The stopper layer 5 is formed by referring to FIG.
When the interlayer insulating layer 6 deposited thereon is etched to open a hole to be the via hole upper portion 9a, it is made of a substance that functions as an etching stopper (etch stopper).

In this structure, since the stopper layer is provided when the via hole is opened in the interlayer insulating layer 6, the diffusion blocking layer 4 is not thinned by overetching. For this reason, the diffusion of the lower layer wiring 3 and the contact material can be surely prevented, so that an element having a small leak current and excellent reliability can be manufactured.

Next, in the structure of the present invention, the interlayer insulating layer 6
The resist mask 7 used as an etch mask when opening the via hole upper portion 9a is removed by, for example, ashing.
Thereafter, referring to FIG. 1D, the stopper layer 5 exposed at the bottom of the via hole upper portion 9a is removed by etching using the interlayer insulating layer 6 as a mask. The etching of the stopper layer 5 is performed by selective etching using the diffusion blocking layer 4 as a stopper, such as RIE, plasma etching or chemical etching.

The stopper layer 5 is a resist mask 7
When removed, it is composed of a substance that is hardly altered or is removed by etching even if it is altered. In such a configuration,
Although the stopper layer 5 may be deteriorated by the removal of the resist mask 7, the deterioration of the surface of the diffusion element layer 4 is protected by the stopper layer 5 and can be reliably avoided. Therefore, reliable contact can be realized,
It is possible to prevent inconveniences caused by the inclusion of the deteriorated layer, such as an increase in contact resistance and fluctuations in the write voltage of the antifuse.

In the above-described structure of the present invention, the lower wiring 3 can be made of a conductor such as Al or its alloy. In addition to conductors such as Al or polycrystalline silicon, amorphous thin films that form antifuses, such as amorphous silicon thin films, amorphous carbon, or ONO films are used as materials that contact the lower wiring 3. (A thin film having a three-layer structure including a silicon nitride film having upper and lower silicon oxide films) can be used.

In the structure of the present invention, Al is used as the lower layer wiring 3.
Alternatively, using an alloy thereof, titanium nitride as the diffusion blocking layer 4,
Tungsten titanium or tungsten nitride is used. In the combination of the lower layer wiring 3 and the above contact material, these diffusion element layers 4 can effectively prevent the Al diffusion reaction at the interface between the lower layer wiring 3 and the contact material.

In the semiconductor device, Si is used as the interlayer insulating layer 6.
O ₂ is widely used. Via holes can be formed in the interlayer insulating layer 6 made of SiO ₂ by using RIE using a resist mask and a gas containing fluorine, for example, a gas containing CF ₄ or CHF ₃ gas as a reaction gas. The stopper layer 5 constituting the present invention uses a refractory metal silicide, for example, tungsten silicide, and functions as a stopper in the RIE of the interlayer insulating layer 6 using a gas containing fluorine as a reaction gas.

Therefore, in the etching for opening a via hole in the interlayer insulating layer 6, the diffusion blocking layer 4 which should be over-etched by the etching of the interlayer insulating layer 6 is protected by the stopper layer 5 if the stopper layer 5 is not present. Therefore, it is not over-etched.

Further, these refractory silicides prevent the diffusion of oxygen during the ashing of the resist mask and prevent the alteration of the diffusion blocking layer 4. Next, these refractory metal silicides are removed by a method used in a usual semiconductor manufacturing process, for example, RIE using a gas containing bromine as a reaction gas, plasma etching, or chemical etching. In etching the refractory metal silicide, titanium nitride, tungsten titanium, or tungsten nitride used as the diffusion blocking layer 4 functions as a stopper. Therefore, the lower layer wiring 3 made of Al is
Since it is protected by the diffusion blocking layer 4, it is etched,
Or, no altered layer is produced.

As described above, in the configuration of the present invention,
The stopper layer needs to have a selectivity with respect to the etching of the interlayer insulating layer 6 and further has a selectivity with respect to the diffusion blocking layer in the etching of the stopper layer. Since the selectivity varies depending on the etching, it is performed by appropriately selecting the materials for the interlayer insulating layer, the stopper layer and the diffusion blocking layer according to the etching.

[0032]

The present invention will be described in detail with reference to an embodiment applied to an FPGA. First, referring to FIG. 1A, a Si substrate 1 on the surface of which a semiconductor element is formed
An oxide film 2 made of O ₂ is deposited.

Then, an Al layer having a thickness of 500 nm, a titanium nitride layer having a thickness of 100 nm, and a tungsten silicide layer having a thickness of 100 nm are sequentially deposited on the oxide film 2 by sputtering. Then, patterning is performed by photoetching, and the stopper layer 5 made of tungsten silicide is formed on the uppermost surface.
Further, the diffusion blocking layer 4 made of TiN is formed on the lower layer thereof to form the lower layer wiring 3 made of Al provided on the upper surface. The lower layer wiring 3 is formed as a group of parallel lines extending perpendicularly to the paper surface of FIG. 1 (a), and FIG. 1 (a) shows a cross section of one of the parallel lines.

Next, a flat surface of SiO _{2 having} a thickness of 1000 nm covering the lower wiring 3, the diffusion blocking layer 4 and the stopper layer 5 is formed.
The layer is deposited as an interlayer insulating layer 6. Then, FIG. 1 (b)
Referring to, a resist mask 7 having an opening 8 that defines a via hole is formed immediately above the lower layer wiring 3. Next, the interlayer insulating layer 6 is selectively etched using this resist mask 7, and a through hole penetrating the interlayer insulating layer 6 is opened as a via hole upper portion 9a.

The etching of the interlayer insulating layer 6 is performed by, for example, RIE using a mixed gas of CF ₄ and CHF ₃ as a reaction gas.
Can be used, and at this time, the stopper layer 5 made of tungsten silicide functions as an etch stopper.

Next, referring to FIG. 1C, the resist mask 7 is exposed to oxygen plasma to be ashed and removed.
At this time, almost no altered layer is generated in the stopper layer 5 exposed on the bottom surface of the via hole upper portion 9a. Further, the diffusion blocking layer 4 covered with the stopper layer 5 never deteriorates.

Next, referring to FIG. 1D, the stopper layer 5 exposed on the bottom surface of the via hole upper portion 9a is etched and removed by RIE using bromine chloride as a reaction gas to prevent diffusion on the bottom surface. A via hole 9 exposing the layer 4 is formed. In the etching of the stopper layer 5, the diffusion blocking layer 4 made of titanium nitride has a sufficient etching selectivity, so that the over-etching of the diffusion blocking layer 4 is extremely small.

Next, referring to FIG. 2E, an amorphous silicon thin film 10 having a thickness of 100 nm is deposited on the inner surface of the via hole and the exposed surface of the interlayer insulating layer 6 by, for example, the CVD method. Then, the amorphous silicon covering the inner surface of the via hole 9 and the amorphous silicon extending on the interlayer insulating layer 6 are etched to leave the region around the opening of the via hole 9 and to etch the amorphous silicon on the interlayer insulating layer 6. Then, the amorphous thin film 10 made of an island-shaped amorphous silicon thin film that covers the inner surface of the via hole 9 is formed.

Next, referring to FIG. 2 (f), the thickness 10
A 0 nm titanium nitride film and an Al layer having a thickness of 1 μm are deposited by, for example, sputtering and patterned to form an upper wiring 12 having a titanium nitride film 11 on the lower surface. This upper layer wiring 12 is patterned as a group of parallel lines orthogonal to the lower layer wiring 3, and in the via holes 9 formed at each intersection with the lower layer wiring 3, the amorphous thin film 10 is divided into upper and lower layer wirings 12 and 3. An antifuse having a sandwiching structure is formed. The titanium nitride film 11 is provided to prevent a diffusion reaction between Al of the upper wiring 12 and the amorphous thin film 10.

The antifuse formed according to this embodiment has a diffusion blocking layer of sufficient thickness between the amorphous thin film 10 made of a silicon thin film and the lower wiring 3 made of Al, so that the diffusion reaction is prevented. Low leakage current and high manufacturing yield.

Further, since the altered layer is not formed on the surface of the diffusion blocking layer 4 when the resist mask 7 is ashed, the write voltage of the antifuse and the residual resistance (ON resistance) after writing rise. It is possible to avoid the inconvenience. Therefore, a highly reliable element can be manufactured.

In the above-described embodiment, an amorphous carbon thin film or an ONO film can be used instead of the amorphous silicon thin film as the amorphous thin film forming the antifuse.

Amorphous carbon is deposited by plasma CVD, for example. When the amorphous thin film is carbon, the amorphous thin film can be etched at the same time as the resist ashing, so that the process can be simplified.

The ONO film is formed by depositing a silicon thin film and then thermally oxidizing it to directly deposit silicon oxide to form an oxide film of 20 nm, for example. Then, it can be formed by depositing silicon nitride and then thermally oxidizing its surface.
As a result, for example, the upper and lower oxide films of 20 nm,
It is possible to form an ONO film having a three-layer structure made of a silicon nitride thin film having a film thickness converted to O ₂ of 50 nm. The etching of the ONO film can be performed by a well-known method.

[0045]

As described above, according to the present invention, when the via hole for connecting to the lower layer wiring having the diffusion blocking layer on the surface is opened in the interlayer insulating layer, the diffusion blocking layer exposed on the bottom surface of the via hole. Without over etching
Further, since the surface of the diffusion blocking layer is not altered when the resist is ashed, it is possible to provide a method of manufacturing a semiconductor device having high reliability and excellent electrical characteristics, and improving the performance of the semiconductor device. It greatly contributes to.

[Brief description of drawings]

FIG. 1 is a sectional process drawing of an embodiment of the present invention (No. 1)

FIG. 2 is a sectional process diagram of an embodiment of the present invention (No. 2)

FIG. 3 is a sectional process diagram of a conventional example.

[Explanation of symbols]

 1 Substrate 2 Oxide Film 3 Lower Wiring 4 Diffusion Blocking Layer 5 Stopper Layer 6 Interlayer Insulating Layer 7 Resist Mask 8 Opening 9 Via Hole 9a Via Hole Top 10 Amorphous Thin Film 11 Titanium Nitride Film 12 Upper Wiring

Claims (2)

[Claims] 1. A substrate (1) having a lower layer wiring (3) made of aluminum or an aluminum alloy and having a diffusion blocking layer (4) made of titanium nitride, titanium-tungsten, or tungsten nitride on the upper surface.
The step of forming the upper layer and the step of forming a via hole (9) penetrating the interlayer insulating layer (6) deposited to cover the lower layer wiring (3) and exposing the diffusion blocking layer (4). In the method of manufacturing a semiconductor device having the method, the step of providing a stopper layer (5) made of refractory metal silicide on the upper surface of the diffusion blocking layer (4), and the interlayer insulating layer made of silicon oxide to cover the lower wiring (3) Using the step of depositing (6) and a resist mask (7) provided on the interlayer insulating layer (6) and having an opening (8) for defining the via hole (9), the interlayer insulating layer ( 6) a step of opening a via hole upper part (9a) which penetrates the stopper layer (5) and then removes the resist mask (7), and then a bottom surface of the via hole upper part (9a) The stopper layer (5) exposed in , The interlayer insulating layer (6) is used as a mask to remove the diffusion blocking layer (4) by etching using the diffusion blocking layer (4) as an etch stopper to expose the diffusion blocking layer (4) and form the via hole (9). A method of manufacturing a semiconductor device, comprising: 2. The method for manufacturing a semiconductor device according to claim 1, wherein an amorphous silicon thin film, an amorphous carbon thin film, and an upper and lower oxide film are formed on the interlayer insulating layer (6) covering the inner surface of the via hole (9). Silicon nitride film having silicon film (ONO film)
A step of depositing an amorphous thin film (10) made of any one of the above, forming an upper layer wiring (12) on the amorphous thin film (10), and forming the lower layer wiring (3) and the upper layer wiring ( 12) and a step of forming the amorphous thin film (10) sandwiched between the amorphous thin film and the amorphous thin film as an antifuse.