JPH0715026A - Semiconductor element - Google Patents
Semiconductor elementInfo
- Publication number
- JPH0715026A JPH0715026A JP3045991A JP4599191A JPH0715026A JP H0715026 A JPH0715026 A JP H0715026A JP 3045991 A JP3045991 A JP 3045991A JP 4599191 A JP4599191 A JP 4599191A JP H0715026 A JPH0715026 A JP H0715026A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- type inp
- contact
- metal electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000013078 crystal Substances 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 22
- 239000010410 layer Substances 0.000 description 77
- 239000000758 substrate Substances 0.000 description 15
- 238000004519 manufacturing process Methods 0.000 description 13
- 229910004298 SiO 2 Inorganic materials 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- 229910000673 Indium arsenide Inorganic materials 0.000 description 4
- 239000004642 Polyimide Substances 0.000 description 4
- 230000000052 comparative effect Effects 0.000 description 4
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000005019 vapor deposition process Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Landscapes
- Electrodes Of Semiconductors (AREA)
- Photovoltaic Devices (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はＩｎＰを用いた半導体素
子に利用する。特に、金属電極と半導体層との接触抵抗
の低減に関する。本発明は、特に受光素子で利用するに
適する。FIELD OF THE INVENTION The present invention is applied to a semiconductor device using InP. In particular, it relates to reduction of contact resistance between the metal electrode and the semiconductor layer. The present invention is particularly suitable for use in a light receiving element.
【０００２】[0002]
【従来の技術】受光素子の遮断周波数を大きくするに
は、容量の低減のために素子の微細化が必要である。し
かし、素子を微細化すると、オーミックの電極面積も小
さくなり、金属と半導体層との接触抵抗が大きくなる。
その結果、素子の直流抵抗が大きくなり、ＣＲ時定数も
大きくなって、遮断周波数は大きくならない。2. Description of the Related Art In order to increase the cutoff frequency of a light receiving element, it is necessary to miniaturize the element in order to reduce the capacitance. However, when the element is miniaturized, the ohmic electrode area is also reduced and the contact resistance between the metal and the semiconductor layer is increased.
As a result, the DC resistance of the element increases, the CR time constant also increases, and the cutoff frequency does not increase.
【０００３】このような課題を解決するため従来から、
ｐｎ接合の横方向から受光する素子や、基板側から受光
する素子が提案されている。横方向から受光する素子に
ついては、例えば、ボワーズ他、エレクトロニクス・レ
ターズ第22巻第905 頁、1986年 (J.E.Bowers et al., E
lectron.Lett. 22 9051986) に示されている。また、基
板側から受光する素子については、例えば、マキウチ
他、エレクトロニクス・レターズ第24巻第109 頁、1988
年 (M.Makiuchi et al., Electron.Lett. 24 1091988)
に示されている。In order to solve such a problem, conventionally,
An element that receives light from the lateral direction of the pn junction and an element that receives light from the substrate side have been proposed. For an element which receives light from the lateral direction, see, for example, Boise et al., Electronics Letters, Vol. 22, p. 905, 1986 (JE Bowers et al., E.
lectron. Lett. 22 905 1986). As for the element which receives light from the substrate side, see, for example, Makiuchi et al., Electronics Letters, Vol. 24, page 109, 1988.
Year (M. Makiuchi et al., Electron. Lett. 24 1091988)
Is shown in.
【０００４】[0004]
【発明が解決しようとする課題】しかし、横方向から受
光する素子では、ｐｎ接合領域に実際に入射する光はわ
ずかであり、入射損が大きい欠点があった。また、基板
側から受光する素子では、基板を加工してマイクロレン
ズを形成する必要があるなど、製造工程が複雑となる欠
点があった。However, in the element which receives light from the lateral direction, the light actually incident on the pn junction region is small, and there is a drawback that the incident loss is large. In addition, in the element that receives light from the substrate side, there is a drawback that the manufacturing process becomes complicated, such that the substrate needs to be processed to form a microlens.
【０００５】本発明は、以上の課題を解決し、電極面積
が小さくても接触抵抗が小さい半導体素子を提供するこ
とを目的とする。It is an object of the present invention to solve the above problems and provide a semiconductor element having a small contact resistance even if the electrode area is small.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体素子は、
ｐ型ＩｎＰ層と金属電極との間に、このｐ型ＩｎＰ層か
ら金属電極に向かって混晶比ｘがほぼ0.47から０まで段
階的に変化するｐ型のＧａx Ｉｎ1-x Ａｓコンタクト層
を備えたことを特徴とする。コンタクト層は、それぞれ
が臨界膜厚程度の厚さで形成された混晶比ｘの異なる複
数の層を含むことが望ましい。The semiconductor device of the present invention comprises:
Between the p-type InP layer and the metal electrode, a p-type Ga x In 1-x As contact layer in which the mixed crystal ratio x changes stepwise from approximately 0.47 to 0 from the p-type InP layer toward the metal electrode. It is characterized by having. It is desirable that the contact layer includes a plurality of layers each having a different mixed crystal ratio x, each layer having a thickness of about the critical thickness.
【０００７】[0007]
【作用】混晶比ｘが0.47のＧａx Ｉｎ1-x Ａｓは、その
格子定数がＩｎＰの格子定数と実質的に等しく、ＩｎＰ
上へのエピタキシャル成長が可能である。このような層
をｐ型ＩｎＰ層上に成長させた後、混晶比ｘを段階的に
小さくして、エネルギバンドギャップのより小さなＩｎ
Ａｓ、すなわち混晶比ｘ＝０になるように成長させる。
混晶比ｘを小さくすれば格子定数も変化するが、各層の
膜厚を臨界膜厚程度にしておけば、転位の発生を防ぐこ
とができる。このようにして成長させたＩｎＡｓ層に金
属電極を接続する。ＩｎＡｓ層と金属電極との接続によ
り、接触比抵抗を低く抑えることができ、表面キャリア
濃度を高めることができる。The Ga x In 1-x As having a mixed crystal ratio x of 0.47 has a lattice constant substantially equal to that of InP.
Epitaxial growth on top is possible. After growing such a layer on the p-type InP layer, the mixed crystal ratio x is gradually reduced to obtain In having a smaller energy band gap.
As, that is, grown so that the mixed crystal ratio x = 0.
When the mixed crystal ratio x is reduced, the lattice constant also changes, but dislocations can be prevented by setting the thickness of each layer to about the critical thickness. A metal electrode is connected to the InAs layer thus grown. By connecting the InAs layer and the metal electrode, the contact specific resistance can be suppressed low and the surface carrier concentration can be increased.
【０００８】[0008]
【実施例】図１は本発明第一実施例の半導体素子を示す
断面図である。以下の説明において「上」とは、基板に
対する結晶成長の方向をいう。1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention. In the following description, “upper” means the direction of crystal growth with respect to the substrate.
【０００９】この半導体素子は、基板１上に形成された
ｐ+ 型ＩｎＰ層２と、このｐ+ 型ＩｎＰ層２に電気的に
接続される金属電極４とを備える。金属電極４として
は、ｐ側の電極として従来から用いられている材料、例
えばＡｕＺｎ／Ａｕを用いる。ここで本実施例の特徴と
するところは、ｐ+ 型ＩｎＰ層２と金属電極４との間
に、ｐ+ 型ＩｎＰ層２から金属電極４に向かって混晶比
ｘがほぼ0.47から０まで段階的に変化するｐ型のＧａx
Ｉｎ1-x Ａｓコンタクト層３を備える。このコンタクト
層３は、ｐ+ 型Ｇａ0.47Ｉｎ0.53Ａｓ層31とｐ+ 型Ｇａ
x Ｉｎ1-x Ａｓ層32（ｘ＝0.47→０）とにより構成され
る。This semiconductor device comprises ap + type InP layer 2 formed on a substrate 1 and a metal electrode 4 electrically connected to this p + type InP layer 2. As the metal electrode 4, a material conventionally used as a p-side electrode, for example, AuZn / Au, is used. Here it is an aspect of this embodiment, between the p + -type InP layer 2 and the metal electrode 4, from the p + -type InP layer 2 on the metal electrode 4 of a mixed crystal ratio x is approximately 0.47 to 0 P-type Ga x that changes in stages
An In 1-x As contact layer 3 is provided. The contact layer 3 includes a p + -type Ga 0.47 In 0.53 As layer 31 and a p + -type Ga layer.
x In 1-x As layer 32 (x = 0.47 → 0).
【００１０】コンタクト層３をｐ型にする方法として
は、ｐ型不純物をドーピングしながら結晶成長させる方
法や、イオン注入、拡散法などの従来からの方法を用い
ることができる。As a method of making the contact layer 3 p-type, a conventional method such as a method of crystal growth while doping a p-type impurity, an ion implantation method or a diffusion method can be used.
【００１１】コンタクト層３は、それぞれ臨界膜厚程度
の厚さで形成された混晶比ｘの異なる複数の層を含む。
混晶比ｘを小さくすると、それに伴ってＧａx Ｉｎ1-x
Ａｓのバンドギャップエネルギが小さくなる。具体的に
は、混晶比ｘ＝0.47のときのバンドギャップエネルギに
は0.72evであるのに対し、混晶比ｘ＝０のＩｎＡｓでは
0.35eVである。このようにバンドギャップエネルギの小
さな層を本来金属と接触させたい半導体層の上に成長さ
せることにより、接触抵抗を低減できる。The contact layer 3 includes a plurality of layers each having a mixed crystal ratio x formed with a thickness of about the critical thickness.
When the mixed crystal ratio x is reduced, the Ga x In 1-x
The band gap energy of As becomes small. Specifically, the band gap energy when the mixed crystal ratio x = 0.47 is 0.72 ev, whereas in InAs where the mixed crystal ratio x = 0,
It is 0.35 eV. In this way, contact resistance can be reduced by growing a layer having a small bandgap energy on a semiconductor layer which is originally desired to be brought into contact with a metal.
【００１２】コンタクト層３の効果を調べるため、比較
例１：半絶縁性ＩｎＰ基板上にｐ+ 型ＩｎＰ層を成長さ
せたもの、比較例２：半絶縁性ＩｎＰ基板上にｐ+ 型Ｉ
ｎＰ層を成長させ、さらに、ｐ+ 型Ｇａ0.47Ｉｎ0.53Ａ
ｓ層を成長させたもの、実施例：半絶縁性ＩｎＰ基板上
にｐ+ 型ＩｎＰ層を成長させ、さらに混晶比ｘが0.47か
ら０に段階的に変化するｐ型Ｇａx Ｉｎ1-x Ａｓ層を成
長させたもののそれぞれについて、ＡｕＺｎ／Ａｕとの
接触比抵抗と、表面キャリア濃度とを測定した。接触比
抵抗については、トランスミッションライン法により行
った。その結果は、 接触比抵抗（Ω・cm2 ） 表面キャリア濃度（cm-3） 比較例１ 2.0×10-4 3.7×1018 比較例２ 1.5×10-5 ３×1019 実施例 1.5×10-6 ３×1019 であった。すなわち、接触比抵抗を大幅に低減でき、コ
ンタクト層がない場合に比較して表面キャリア濃度を一
桁程度高めることができた。In order to investigate the effect of the contact layer 3, Comparative Example 1: a p + type InP layer grown on a semi-insulating InP substrate, Comparative Example 2: p + type I on a semi-insulating InP substrate
An nP layer is grown, and p + type Ga 0.47 In 0.53 A
s layer grown, Example: p + type InP layer grown on a semi-insulating InP substrate, and p type Ga x In 1-x in which the mixed crystal ratio x changes stepwise from 0.47 to 0 For each of the grown As layers, the contact resistivity with AuZn / Au and the surface carrier concentration were measured. The contact specific resistance was measured by the transmission line method. The results show that contact specific resistance (Ω · cm 2 ), surface carrier concentration (cm -3 ), Comparative Example 1 2.0 × 10 -4 3.7 × 10 18 Comparative Example 2 1.5 × 10 -5 3 × 10 19 Example 1.5 × 10 -6 It was 3 × 10 19 . That is, the contact specific resistance could be significantly reduced, and the surface carrier concentration could be increased by about one digit as compared with the case without the contact layer.
【００１３】接触比抵抗が低下するのは、表面キャリア
濃度が一桁程度高くなることに加えて、表面層のエネル
ギーバンドギャップが1/3 以下になるので、コンタクト
層と金属電極との接合部でトンネル電流が大きくなるた
めと考えられる。The contact specific resistance decreases because the surface carrier concentration increases by about one digit and the energy band gap of the surface layer becomes 1/3 or less. It is thought that this is because the tunnel current increases.
【００１４】図２は本発明の第二実施例を示す断面図で
あり、図３ないし図10はその製造方法を示す。この実施
例は本発明をＰＩＮ型の受光素子に実施したものであ
る。FIG. 2 is a sectional view showing a second embodiment of the present invention, and FIGS. 3 to 10 show a manufacturing method thereof. In this embodiment, the present invention is applied to a PIN type light receiving element.
【００１５】この受光素子は、半絶縁性ＩｎＰ基板10上
にｎ+ 型ＩｎＰ層11、ｎ- 型Ｇａ0.47Ｉｎ0.53Ａｓ層1
2、ｎ- 型ＩｎＰ層13およびｐ+ 型ＩｎＰ層14がエピタ
キシャルに積層され、ｐ+ 型ＩｎＰ層14の側から光が入
射する構造をもつ。ｎ+ 型ＩｎＰ層11にはＡｕＳｎ／Ａ
ｕ電極18が接続され、ｐ+ 型ＩｎＰ層14にはｐ型Ｇａx
Ｉｎ1-x Ａｓコンタクト層15を介してＡｕＺｎ／Ａｕ電
極19が接続される。This light receiving element comprises an n + type InP layer 11 and an n − type Ga 0.47 In 0.53 As layer 1 on a semi-insulating InP substrate 10.
2. The n − -type InP layer 13 and the p + -type InP layer 14 are epitaxially stacked, and light is incident from the p + -type InP layer 14 side. AuSn / A is used for the n + type InP layer 11.
The u electrode 18 is connected to the p + -type InP layer 14 and the p-type Ga x is formed.
The AuZn / Au electrode 19 is connected via the In 1-x As contact layer 15.
【００１６】この受光素子の詳細な構造について、その
製造方法により説明する。The detailed structure of this light receiving element will be described by its manufacturing method.
【００１７】この受光素子を製造するには、まず、図３
に示すように、半絶縁性ＩｎＰ基板10上にｎ+ 型ＩｎＰ
層11、ｎ- 型Ｇａ0.47Ｉｎ0.53Ａｓ層12、ｎ- 型ＩｎＰ
層13およびｐ+ 型ＩｎＰ層14をエピタキシャルに成長さ
せ、さらに、コンタクト層15を成長させる。コンタクト
層15の上にはＳｉＯ2 膜16を堆積させる。To manufacture this light receiving element, first, referring to FIG.
As shown in FIG. 3, n + type InP is formed on the semi-insulating InP substrate 10.
Layer 11, n − type Ga 0.47 In 0.53 As layer 12, n − type InP
The layer 13 and the p + type InP layer 14 are grown epitaxially, and the contact layer 15 is further grown. A SiO 2 film 16 is deposited on the contact layer 15.
【００１８】コンタクト層15については、最初にＩｎＰ
と格子定数が実質的に等しいＧａxＩｎ1-x Ａｓ（ｘ＝
0.47) をエピタキシャル成長させ、その後に、混晶比ｘ
を段階的に小さくして、ｘ＝０のＩｎＡｓまで成長させ
る。組成を変化させるとき、転位が生じないように、各
層の膜厚を臨界膜厚程度にする。また、コンタクト層15
をｐ型にするには、ｐ型不純物をドーピングしながら結
晶成長させてもよく、イオン注入や拡散法を用いてもよ
い。Regarding the contact layer 15, first, InP is used.
And Ga x In 1-x As (x =
0.47) is epitaxially grown, and then the mixed crystal ratio x
Is gradually reduced to grow to InAs at x = 0. When changing the composition, the film thickness of each layer is set to about the critical film thickness so that dislocation does not occur. In addition, the contact layer 15
In order to make the p-type into a p-type, crystal growth may be performed while doping a p-type impurity, or ion implantation or a diffusion method may be used.
【００１９】ｎ+ 型ＩｎＰ層11ないしコンタクト層15の
結晶成長は、例えば成長圧力76Torrの減圧ＭＯＶＰＥに
より、 成長温度 (℃) ドーパント 膜厚 (μm) ｎ+ 型ＩｎＰ層11 500 Ｓ 0.5 ｎ- 型Ｇａ0.47Ｉｎ0.53Ａｓ層12 600 なし 0.3 ｎ- 型ＩｎＰ層13 600 なし 0.2 ｐ+ 型ＩｎＰ層14 600 Ｚｎ 0.1 コンタクト層15 Ｇａ0.47Ｉｎ0.53Ａｓ 600 Ｚｎ 0.03 Ｇａx Ｉｎ1-x Ａｓ 470 Ｚｎ 0.06 x=0.47からx=0 まで９段階 各膜厚は約７nm の条件で行う。Crystal growth of the n + -type InP layer 11 or the contact layer 15 is carried out by, for example, a reduced pressure MOVPE at a growth pressure of 76 Torr at a growth temperature (° C.) dopant film thickness (μm) n + -type InP layer 11 500 S 0.5 n − -type Ga 0.47 In 0.53 As layer 12 600 None 0.3 n − type InP layer 13 600 None 0.2 p + type InP layer 14 600 Zn 0.1 Contact layer 15 Ga 0.47 In 0.53 As 600 Zn 0.03 Ga x In 1-x As 470 Zn 0.06 x 9 steps from = 0.47 to x = 0 Each film thickness is about 7 nm.
【００２０】このようにして得られたエピタキシャル基
板に対して、図４、図５に示すように、二段階のメサエ
ッチングを行う。図４に示した第一段階のメサエッチン
グでは、半絶縁性ＩｎＰ基板10が露出するまでエッチン
グを行い、ｎ+ 型ＩｎＰ層11からＳｉＯ2 膜16までの層
を含むメサを形成する。図５に示した第二段階のメサエ
ッチングでは、ｎ+ 型ＩｎＰ層11を露出させ、ｎ- 型Ｇ
ａ0.47Ｉｎ0.53Ａｓ層12からＳｉＯ2 膜16までの層を含
むメサを形成する。エッチング剤としては、３ＨＣｌ＋
Ｈ3 ＰＯ3 および５Ｈ2 ＳＯ4 ＋Ｈ2 Ｏ2 ＋Ｈ2 Ｏを用
いる。As shown in FIGS. 4 and 5, the epitaxial substrate thus obtained is subjected to two-step mesa etching. In the first stage mesa etching shown in FIG. 4, etching is performed until the semi-insulating InP substrate 10 is exposed to form a mesa including layers from the n + type InP layer 11 to the SiO 2 film 16. In the second stage mesa etching shown in FIG. 5, the n + -type InP layer 11 is exposed and the n − -type G
A mesa including layers from 0.47 In 0.53 As layer 12 to SiO 2 film 16 is formed. 3HCl + as etching agent
H 3 PO 3 and 5H 2 SO 4 + H 2 O 2 + H 2 O are used.
【００２１】二段のメサが形成された後、図６に示すよ
うに、プラズマ化学気相成長（ｐ−ＣＶＤ）法により全
面にＳｉＯ2 膜17を堆積させる。続いて、図７に示すよ
うに、ＳｉＯ2 膜17のうちｎ+ 型ＩｎＰ層11の上面に形
成された部分に窓を開け、ＡｕＳｎ／Ａｕ電極18を蒸着
する。また、図８に示すように、コンタクト層15の上の
ＳｉＯ2 膜16および17に窓を開け、ＡｕＺｎ／Ａｕ電極
19を蒸着する。After the two-step mesas are formed, a SiO 2 film 17 is deposited on the entire surface by plasma chemical vapor deposition (p-CVD), as shown in FIG. Subsequently, as shown in FIG. 7, a window is opened in a portion of the SiO 2 film 17 formed on the upper surface of the n + type InP layer 11, and an AuSn / Au electrode 18 is vapor-deposited. Further, as shown in FIG. 8, windows are opened in the SiO 2 films 16 and 17 on the contact layer 15 to form AuZn / Au electrodes.
Evaporate 19.
【００２２】電極を蒸着した後、図９、図10に示すよう
に、電極部分を残して素子の表面にポリイミド20を塗布
し、このポリイミド20の上に、それぞれＡｕＳｎ／Ａｕ
電極18、ＡｕＺｎ／Ａｕ電極19に接続されるＣｒＡｕパ
ッド21、22を形成する。After vapor deposition of the electrodes, as shown in FIGS. 9 and 10, polyimide 20 is applied to the surface of the device, leaving the electrode portions, and AuSn / Au is applied onto the polyimide 20, respectively.
CrAu pads 21 and 22 connected to the electrode 18 and AuZn / Au electrode 19 are formed.
【００２３】以上の実施例では、本発明を受光素子に実
施した例を示したが、ＩｎＰ系の素子であれば、半導体
レーザやトランジスタの場合にも本発明を同様に実施で
き、接触抵抗を低減できる。In the above embodiments, the present invention is applied to the light receiving element. However, the present invention can be applied to the semiconductor laser or the transistor as long as it is an InP type element, and the contact resistance can be improved. It can be reduced.
【００２４】[0024]
【発明の効果】以上説明したように、本発明の半導体素
子は、ｐ型ＩｎＰ層と金属電極との間に、混晶比ｘが0.
47から０まで段階的に変化するｐ型のＧａx Ｉｎ1-x Ａ
ｓコンタクト層を設けることにより、ｐ型ＩｎＰ層と金
属電極との直接接続の場合に比べて接触抵抗を約二桁低
減できる。したがって、素子を微細化してもＣＲ時定数
の増加を抑えることができ、遮断周波数を大きくできる
効果がある。本発明は、特に受光素子の入射側の構造に
利用して特に効果がある。As described above, in the semiconductor device of the present invention, the mixed crystal ratio x is 0 between the p-type InP layer and the metal electrode.
P-type Ga x In 1-x A that gradually changes from 47 to 0
By providing the s contact layer, the contact resistance can be reduced by about two orders of magnitude as compared with the case where the p-type InP layer and the metal electrode are directly connected. Therefore, even if the element is miniaturized, an increase in the CR time constant can be suppressed and the cutoff frequency can be increased. The present invention is particularly effective when applied to the structure on the incident side of the light receiving element.
【図１】 本発明第一実施例の半導体素子を示す断面
図。FIG. 1 is a sectional view showing a semiconductor device of a first embodiment of the present invention.
【図２】 本発明の第二実施例を示す断面図。FIG. 2 is a sectional view showing a second embodiment of the present invention.
【図３】 第二実施例の製造方法を示す図であり、結晶
成長工程を示す図。FIG. 3 is a diagram showing the manufacturing method of the second embodiment and a diagram showing a crystal growth step.
【図４】 第二実施例の製造方法を示す図であり、第一
段階のメサエッチング工程を示す図。FIG. 4 is a view showing the manufacturing method of the second embodiment, showing the mesa etching step in the first step.
【図５】 第二実施例の製造方法を示す図であり、第二
段階のメサエッチングを示す図。FIG. 5 is a view showing the manufacturing method of the second embodiment, showing a second stage of mesa etching.
【図６】 第二実施例の製造方法を示す図であり、ｐ−
ＣＶＤによるＳｉＯ2膜形成工程を示す図。FIG. 6 is a diagram showing a manufacturing method of the second embodiment, p−
Shows the SiO 2 film forming process by CVD.
【図７】 第二実施例の製造方法を示す図であり、ｎ+
電極蒸着工程を示す図。FIG. 7 is a diagram showing a manufacturing method of the second embodiment, in which n +
The figure which shows an electrode vapor deposition process.
【図８】 第二実施例の製造方法を示す図であり、ｐ+
電極蒸着工程を示す図。FIG. 8 is a diagram showing the manufacturing method of the second embodiment, p +
The figure which shows an electrode vapor deposition process.
【図９】 第二実施例の製造方法を示す図であり、ポリ
イミド塗布工程を示す図。FIG. 9 is a view showing the manufacturing method of the second embodiment, showing a polyimide coating step.
【図10】 第二実施例の製造方法を示す図であり、電極
パッド形成工程を示す図。FIG. 10 is a diagram showing the manufacturing method of the second embodiment, and a diagram showing an electrode pad forming step.
１ 基板 ２ ｐ+ 型ＩｎＰ層 ３ コンタクト層 31 ｐ+ 型Ｇａ0.47Ｉｎ0.53Ａｓ層 32 ｐ+ 型Ｇａx Ｉｎ1-x Ａｓ層 ４ 金属電極 10 半絶縁性ＩｎＰ基板 11 ｎ+ 型ＩｎＰ層 12 ｎ- 型Ｇａ0.47Ｉｎ0.53Ａｓ層 13 ｎ- 型ＩｎＰ層 14 ｐ+ 型ＩｎＰ層 15 コンタクト層 16、17 ＳｉＯ2 膜 18 ＡｕＳｎ／Ａｕ電極 19 ＡｕＺｎ／Ａｕ電極 20 ポリイミド 21、22 ＣｒＡｕパッド1 substrate 2 p + type InP layer 3 contact layer 31 p + type Ga 0.47 In 0.53 As layer 32 p + type Ga x In 1-x As layer 4 metal electrode 10 semi-insulating InP substrate 11 n + type InP layer 12 n - type Ga 0.47 In 0.53 As layer 13 n - -type InP layer 14 p + -type InP layer 15 contact layer 16, 17 SiO 2 film 18 AuSn / Au electrode 19 AuZn / Au electrode 20 polyimide 21, 22 CrAu pad
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 8422−4Ｍ Ｈ０１Ｌ 31/10 Ｈ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display area 8422-4M H01L 31/10 H
Claims (3)
気的に接続される金属電極とを備えた半導体素子におい
て、 前記ｐ型ＩｎＰ層と前記金属電極との間に、前記ｐ型Ｉ
ｎＰ層から前記金属電極に向かって混晶比ｘがほぼ0.47
から０まで段階的に変化するｐ型のＧａx Ｉｎ1-x Ａｓ
コンタクト層を備えたことを特徴とする半導体素子。1. A semiconductor device comprising a p-type InP layer and a metal electrode electrically connected to the p-type InP layer, wherein the p-type InP layer is provided between the metal electrode. I
The mixed crystal ratio x is approximately 0.47 from the nP layer toward the metal electrode.
P-type Ga x In 1-x As that changes stepwise from 0 to 0
A semiconductor device comprising a contact layer.
度の厚さで形成された混晶比ｘの異なる複数の層を含む
請求項１記載の半導体素子。2. The semiconductor device according to claim 1, wherein the contact layer includes a plurality of layers each having a different mixed crystal ratio x, each layer having a thickness of about a critical thickness.
ｐ型ＩｎＰ層はその受光素子の光入射側の層である請求
項１または２記載の半導体素子。3. The semiconductor element according to claim 1, wherein the semiconductor element is a light receiving element, and the p-type InP layer is a layer on the light incident side of the light receiving element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3045991A JP2694260B2 (en) | 1991-02-19 | 1991-02-19 | Semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3045991A JP2694260B2 (en) | 1991-02-19 | 1991-02-19 | Semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0715026A true JPH0715026A (en) | 1995-01-17 |
| JP2694260B2 JP2694260B2 (en) | 1997-12-24 |
Family
ID=12734603
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3045991A Expired - Fee Related JP2694260B2 (en) | 1991-02-19 | 1991-02-19 | Semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2694260B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10189479A (en) * | 1996-12-26 | 1998-07-21 | Matsushita Electron Corp | Semiconductor device |
| JP2010177286A (en) * | 2009-01-27 | 2010-08-12 | Nec Corp | Semiconductor light receiving element and process of fabricating the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6262566A (en) * | 1985-09-12 | 1987-03-19 | Fujitsu Ltd | Photo-semiconductor device |
| JPH02199825A (en) * | 1989-01-27 | 1990-08-08 | Nec Corp | Manufacture of electrode |
-
1991
- 1991-02-19 JP JP3045991A patent/JP2694260B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6262566A (en) * | 1985-09-12 | 1987-03-19 | Fujitsu Ltd | Photo-semiconductor device |
| JPH02199825A (en) * | 1989-01-27 | 1990-08-08 | Nec Corp | Manufacture of electrode |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10189479A (en) * | 1996-12-26 | 1998-07-21 | Matsushita Electron Corp | Semiconductor device |
| JP2010177286A (en) * | 2009-01-27 | 2010-08-12 | Nec Corp | Semiconductor light receiving element and process of fabricating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2694260B2 (en) | 1997-12-24 |
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