JPH0715355A - Equalization / decoding device - Google Patents

Abstract

(57) [Abstract] [Purpose] To reduce the decoding error by removing the low frequency noise, and to realize higher density recording and reproduction. [Structure] For a given input data sequence, a recording code that can uniquely define a signal sequence by a plurality of states and state transitions between these states is decoded. Therefore, the equalizer 301 having the characteristics of correcting the deteriorated signal component and attenuating the low frequency component is composed of the equalizer 202, the delay device 203, and the subtractor 204. A decoder 205 is provided which decodes a data sequence from the output of the equalizer 301 by the Viterbi decoding method. By doing so, the equalizer 301 reduces crosstalk noise and improves S / N. In addition, the decoder 206 can reduce the decoding error rate for the same S / N.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an equalization / decoding device for effectively decoding a signal digitally recorded or transmitted at a high rate with a low error rate.

[0002]

2. Description of the Related Art Consider the case of recording and reproducing digital data on a magnetic tape or the like. By digitizing data, the recording density can be increased and the amount of recordable data can be increased. In order to increase the recording density, the wavelength of the recording signal is shortened and the magnetic tape is narrowed. In addition, azimuth recording is also performed by providing an azimuth angle in the gap of each magnetic head so as to prevent the leakage magnetic flux from an adjacent track from being picked up. When the wavelength of the recording signal is λ, the azimuth angle is θ, and the track width where the heads overlap is W, the azimuth loss L is expressed by the following equation (1).

[Equation 1]

As can be seen from the equation (1), the longer the recording wavelength λ, in other words, the lower the frequency, the smaller the azimuth loss L becomes. Therefore, when a certain track is reproduced, a low frequency signal from an adjacent track is picked up. This is so-called crosstalk noise.

In the case of magnetic recording, since the recording / reproducing system generally shows a differential characteristic, assuming that the recording code sequence recorded on the magnetic tape is {b _K }, an ideal reproducing output on the assumption that there is no waveform interference. The sequence {x _K } is given by the following equation (2).

[Equation 2] However, when T _R is a 1-bit period, the code with the subscript k is a sample value at time (k · T _R ).

In practice, the reproduced waveform has a blunted shape due to the attenuation characteristic of the high frequency component in the magnetic recording system. Here, if the isolated reproduction waveform for the transition of the code “0” → “1” is h (t) and hi = h (i · T _R ), the actual reception sequence {y _K } is the following (3). It is represented by a formula.

[Equation 3] However, n _K 'is a sample value of noise added externally during reproduction.

When the equation (3) is rewritten with frequency components, the following equation (4) is obtained.

[Equation 4] Note that X (f), H (f), N '(f) and Y (f) are obtained by Fourier transform of x (t), h (t), n' (t) and y (t), respectively. Is a function.

In high-density recording required for a digital VTR, decoding based on the amplitude level of a reproduced signal is necessary, and for this purpose, waveform interference must be removed. As can be seen from the equation (4), in order to correct the high frequency component attenuated in the reproduction process, the equalization output Z shown in the equation (5) is obtained by performing the waveform equalization having the characteristic of 1 / H (f).
(f) is obtained and waveform interference can be eliminated.

[Equation 5] However, the equalization noise N (f) is expressed by equation (6).

[Equation 6]

Since the frequency characteristic H (f) of the reproducing system is a high frequency attenuation characteristic, the inverse characteristic 1 / H (f) naturally becomes a high frequency emphasis characteristic. Therefore, the equalization noise N (f) in equation (6) is
Indicates a high-frequency emphasis characteristic. The higher the recording density, the larger the amount of waveform interference and the higher the amount of equalization noise emphasized in the high frequency range, so that the signal-to-noise (S / N) ratio is significantly deteriorated.

In order to suppress this equalization noise, a method of suppressing a high-frequency noise component has been performed, and this method is called partial response class IV. FIG. 7 is a block diagram showing the configuration of an equalization / decoding device according to this method. In the figure, a reproduction signal of the magnetic recording device is given to the input terminal 101. The equalizer 102 is a circuit for inputting a reproduction signal and removing waveform interference, and its output is given to the delay device 103 and the adder 104. The delay device 103 is a delay device having one sampling period, and its output is given to the adder 104.

The adder 104 is a circuit for adding input signals, and its output is given to the decoder 105. Decoder 10
Reference numeral 5 is a circuit for decoding a signal modulated at the time of recording, and the signal is output from the output end 106. Where equalizer 1
02, the delay device 103, and the adder 104 constitute an equalizing means for giving an equalized output to the decoder 105.

In the conventional equalization / decoding device having the above-described structure, the equalizer 102 removes waveform interference from the reproduction signal input to the input terminal 101. Time t = k
If the output of the equalizer 102 at T _R is x _K , the output of the delay device 103 is the time t = (k− of the equalizer 102.
1) Output the signal at T _R and its value is x _K-1 . Therefore, assuming that the output of the adder 104 at time t = k · T _R is p _K , the following expression (7) is obtained.

[Equation 7]

The delay operator D = exp (-j
By rewriting using (2πfT _R ), the following equation (8) is obtained.

[Equation 8] When the equation (8) is expressed by frequency components, the following equation (9) is obtained.

[Equation 9] Here, f _R is 1 / T _R, which is the clock frequency.
Therefore, the total frequency characteristic E (f) of the equalizer shown in FIG.
Becomes the following expression (10).

[Equation 10]

A curve a of FIG. 8 shows the frequency characteristic of the amplitude of the output of the equalizer 102 of FIG. 7, and a curve b is a spectrum showing the frequency characteristic of the output amplitude of the adder 104 up to f _R / 2. . As shown in FIG. 8, it can be seen that high frequency noise is removed. Therefore, when the high-frequency equalization noise accounts for a large proportion of the total noise, the noise power is reduced and the decoding error can be reduced.

[0014]

However, in such a conventional equalization / decoding apparatus, although the high frequency equalization noise is suppressed, the low frequency crosstalk noise is emphasized to the contrary. When the track pitch is small, the ratio of crosstalk noise to the total noise increases. In this case, the amount of emphasis of low-frequency crosstalk noise is larger than the amount of suppression of high-frequency equalization noise. This results in an increase in noise power, which causes a problem that decoding errors increase.

The present invention has been made in view of such conventional problems, and an object of the present invention is to realize an equalization / decoding apparatus which enables higher density recording and reduces decoding errors. .

[0016]

According to the invention of claim 1 of the present application, an arbitrary encoded input data sequence {b _K } (k is an integer indicating discrete time) is applied to a recording medium or a signal transmission path. , Equalization for uniquely decoding a signal sequence {p _K } from a received sequence obtained from a recording medium or a signal transmission path by a plurality of states defined by a signal sequence in a predetermined sampling period and state transitions between these states A decoding device, an equalization means for correcting the frequency characteristic of the signal component of the input reception sequence, a likelihood calculation means for calculating the likelihood of state transition from the output of the equalization means and the signal sequence, From the output of the likelihood calculation means and the metric indicating the likelihood of each state one sampling before, a metric calculation means for calculating a new metric at the present time, and the most probable state of reaching each of the states Is characterized in that it comprises the survival data holding means for sequentially updating holds the signal sequence {p _K} corresponding to the transition, the.

According to the invention of claim 4 of the present application, an arbitrary encoded input data sequence {b _K } (k is an integer indicating discrete time) is given to a recording medium or a signal transmission path, and the recording medium or the signal transmission is performed. An equalization / decoding device that uniquely decodes a signal sequence {p _K } from a received sequence obtained from a path by a plurality of states defined by a signal sequence of a predetermined sampling period and state transitions between these states, , An equalizing means for correcting the frequency characteristic of the signal component of the input received sequence, a likelihood calculating means for calculating the likelihood of the state transition from the output of the equalizing means, the signal sequence and the prediction noise, and a likelihood calculating A metric calculation means for calculating a new metric at the present time from the output of the means and a metric indicating the likelihood of each state one sampling before, and the most probable state transition to each state. A survival data holding means for sequentially updating and holding the corresponding data series, an equalization output holding means for sequentially updating and holding a plurality of outputs of the equalization means, a noise series from the equalization output holding means and the survival data holding means. It is characterized by comprising: a noise extracting means for extracting; and a predictive noise calculating means for calculating predictive noise using the noise sequence of the noise extracting means.

[0018]

According to the invention of claim 1 of the present application having such characteristics, when an arbitrary input data sequence {b _K } is input to the recording / reproducing apparatus at a high density, inter-code interference occurs and the signal is reproduced at the time of reproduction. Although the output is deteriorated, the equalizer corrects the deteriorated signal component to generate an equalized reproduction output. When this signal is given to the decoding means, the likelihood calculation means calculates the likelihood of state transition from the output signal sequence of the equalization means. Next, the metric calculation means calculates a new metric at the present time from the metric indicating the likelihood of each state at the immediately previous time. And the survival data holding means is
The data sequence corresponding to the most probable state transition leading to each state is sequentially updated and held. In this way, the signal sequence {p _K } is generated by the multiple states and the state transition between these states.
Can be uniquely decoded, and the error rate of decoding can be reduced in the state where uncorrelated noise is added.

According to the invention of claim 4 of the present application, in addition to the operation of the invention of claim 1, the equalization output holding means sequentially updates and holds a plurality of outputs of the equalization means, and the noise extraction means etc. A noise sequence is extracted from the converted output holding means and the survivor data holding means. The prediction noise calculation means calculates the prediction noise using the noise sequence of the noise extraction means. In this way, even when correlated noise is added, it is converted into uncorrelated noise, and the signal can be decoded using the Viterbi decoding method. In addition, deterioration of S / N due to crosstalk can be suppressed.

[0020]

In this section, first, an outline of the equalization / decoding apparatus of the present invention will be shown, and then the first and second embodiments will be concretely described. FIG. 1 is a block diagram showing the overall configuration of an equalization / decoding device of the present invention. In the figure, the reproduction signal of the magnetic recording apparatus is given to the input terminal 201. The equalizer 202 is a circuit that inputs a reproduction signal and removes waveform interference, and its output is given to the delay unit 203 and the + input terminal of the subtracter 204. The delay device 203 is a delay device having one sampling period, and its output is given to the minus input terminal of the subtractor 204.

The subtractor 204 is a circuit for subtracting the output of the delay unit 203 from the output of the equalizer 202, and its output is given to the decoder 205. The decoder 205 is a circuit for decoding the signal modulated at the time of recording, and the signal is output to the output terminal 206.
Is output from. Here, the equalizer 202, the delay device 203,
The subtractor 204 constitutes an equalizer 301 that gives an equalized output to the decoder 205.

In the equalization / decoding apparatus thus configured, assuming that the output of the equalizer 202 at time t = k · T _R is x _K , the output of the delay unit 203 is the time t of the equalizer 202. = (K−1) · T _R output equals _K−1 . Therefore, when the output of the subtractor 204 at time t = k · T _R is p _K , the following equation (11) is obtained.

[Equation 11]

When the equation (11) is rewritten using the delay operator D = exp (-j2πfT _R ) as in the equation (8), the equation (12) is obtained.

[Equation 12] When the obtained expression (12) is expressed by frequency components, (13)
The formula is obtained.

[Equation 13] Here, f _R indicates the clock frequency, which coincides with 1 / T _R.

Therefore, the total frequency characteristic E (f) of the equalizer that can obtain {p _K } shown in FIG. 1 is given by the following equation (14).

[Equation 14]

A curve a of FIG. 9 represents the frequency characteristic of the output amplitude of the equalizer 202 of FIG. 1, and a curve b is a spectrum showing the frequency characteristic of the output amplitude of the subtractor 204 up to f _R / 2. As can be seen from the equation (14) and FIG. 9, the low frequency component of the reproduction output sequence is largely removed, and the crosstalk noise can be considerably eliminated.

Letting A be the peak value of the isolated reproduction waveform and σ be the effective value of noise, the S / N value a is defined as in equation (15).

[Equation 15] Assuming that there is no correlation between noises, the decoding error rate P ₁ when using the equalization / decoding device of the present invention is expressed by the following equation (16).

[Equation 16]

By the way, the error rate P _{2 in the} case of using the conventional partial response class IV is given by the following equation (17).

[Equation 17] Here, the complementary error function Q used in the equations (16) and (17) is
It is defined by the following equation (18).

[Equation 18]

FIG. 10 is a graph showing the relationship between the S / N value and the decoding error rate when the equalization / decoding devices of the conventional example and the present embodiment are used. Here, the dB value of S / N is (19)
Define with an expression.

[Formula 19]

As described above, according to the equalizing means 301 of FIG. 1, not only the crosstalk noise is removed, but also an error rate lower than that of the conventional method can be achieved even for the same S / N value. For example, if the S / N value is 15 dB, assuming that the noise has no correlation, the partial response class IV
In contrast, the error rate is 1.4 × 10 ⁻⁴ , whereas the error rate is 2.8 × 10 ^{−8 in} the equalization / decoding device of the present embodiment, and the error rate is greatly improved.

By using the equation (2), the equation (11) can be rewritten as the following equation (20).

[Equation 20] The expression (21) is obtained from the output {p _K } of the subtractor 204 without passing through the output {x _K } of the equalizer 202 and the recording code sequence {b _K }.
It can be directly decoded. In each of the following embodiments of the present invention, decoding is performed using the "Viterbi decoding method" suitable for such a system.

FIG. 11 is a state transition diagram in this embodiment, and FIG. 12 is a trellis diagram. In this embodiment, the state up to the point two bits before is held as shown in equation (20). The state up to 2 bits before is Si (b _K-2 , b
_K-1 ) and four states Si (i = 0 to 3) are defined. Figure 1
As shown on the left side of 2, the state S ₀ represents (0,0), S ₁ represents (0,1), S ₂ represents (1,0), and S ₃ represents (1,1). Further, in FIGS. 11 and 12, the symbol attached to the arrow represents b _K / p _K.

Assuming that the noise sample value at the output of the equalizer is n _K , the output z _K of the equalizer containing noise is represented by the following equation (21), which becomes the input of the decoder 205. .

[Equation 21]

Next, a first embodiment of the present invention will be described. The state at time t = k · T _R is S (k) (S ₀ ~
(Any value of S ₃ ), and assuming that the noise sample values for each bit cell are independent of each other, a data sequence of length L [b ₁ , b ₂ , ..., With an initial state of S (0).
b _l ] on the state transition diagram corresponding to the path [S (0); b ₁ ,
b _2, ..., when the b _l] is given, the input sequence of the decoder _{[z 1, z 2, ...} , z l] The following negative log likelihood function (2
It becomes the formula 2).

[Equation 22] Here, the likelihood function p [z _k | S (k−1); b _k ] changes from the state S (k−1) at time (k−1) to the state S (k) at time k. Is the probability of inputting z _k into and decoding b _k .

From equation (22), it can be seen that the negative log-likelihood function of a given path is expressed as the sum of the negative log-likelihood functions of the individual branches forming the path. Therefore, if the branch length is expressed by a negative logarithmic likelihood function, the path with the smallest length can be selected and the corresponding data sequence, that is, the maximum likelihood sequence can be decoded by the following method. .

The minimum value of the length of the path leading to each state at a certain time is called a metric, but for the present invention, t
= K · T _{R, when} the metric for each state S _i (i = 0 to 3) is represented by m _K (S _i ) (i = 0 to 3), the relationship as shown in the following equation (23) is obtained from FIG. 11. Is obtained.

[Equation 23]

Assuming that the noise sample value n _K is Gaussian noise with a mean value of 0 and a variance of σ ² , the input z _{K of the} decoder is Gaussian with a mean value of p _K and a variance of σ ² from equation (21). It becomes a variable. Therefore, for example, from the state S (k-1) = S ₀ to b
By inputting the _K = 1, in case of transition to the state S (k) = S ₁ is the likelihood function p is p = 1 / {((2π ) 1/2 ·
It is expressed as σ} exp (−n _K ² / 2σ ² ). From FIG. 11, p _K =
Since it is A, if equation (21) is modified, then n _k = z _K −A. Substituting this n _k into the above-mentioned likelihood function p, the following equation (24) is obtained.

[Equation 24] However, A is the amplitude (0-P) of the reproduced waveform.

Similarly, the other negative logarithmic likelihood functions in the equation (23) can be calculated respectively, and the first term and the second term on the right side of the equation (24) appear as common terms in all of them. Therefore, even if the common term is removed and the result is further divided by 1 / σ ² , normality is not lost. Thus normalized metrics m _K as shown in the following (25) to (28) _{'(S i) (i =} 0~3) is obtained.

[Equation 25]

[Equation 26]

[Equation 27]

[Equation 28]

Where l _Kij is the state S (k-1) = S _i (i = 0
.About.3) to the state S (k) = _S.sub.j (j = 0.about.3), which represents the length of the branch, and is calculated by the following equation (29).

[Equation 29] However, if S ₀ is selected as the initial state, the following (3
Equation (0) holds.

[Equation 30]

At time t = k · T _R , the state S _j (j = 0)
~ 3), only the path having the metric m _K ′ (S _j ) (j = 0 to 3) given by the equations (25) to (28) may become the maximum likelihood path. Left as having
The others are discarded. This path is called the surviving path, the probability of surviving path at time k · T _R is one of at time (k-1) · T _R becomes larger with k. This unified path is decoded as the maximum likelihood path.

Here, theoretically, (25) to (28)
Although the metric can be calculated by the formula, the following overflow prevention measures are practically necessary to prevent the metric from overflowing. That is (25)-
As can be seen from the equation (28), the absolute size of the metric is not important, and the relative magnitude relationship between the metrics is only important. That is, correct decoding is possible if the likelihood difference between the metrics can be maintained. _{This, m K-1 '(S} 0) m K-1 as the relative value to zero'
Even if (S _i ) (i = 1 to 3) is expressed, it is shown that the magnitude relation of the likelihoods is maintained accurately. Therefore, after the calculation of equations (25) to (28) is completed, m _K ′ (S _i ) (i = 0 to 3) to m _K ′ (S ₀ ).
And again setting m _K ′ (S _i ) (i = 0 to 3), the overflow of the above metric can be prevented. Since the newly obtained m _K ′ (S ₀ ) is zero, it can be omitted in the metric calculation, and the following formulas (31) to (34) are obtained as the metric calculation formula.

[Equation 31]

[Equation 32]

[Expression 33]

[Equation 34]

Next, a specific configuration example of the equalization / decoding device in the first embodiment will be described with reference to the block diagrams of FIGS. 2 and 3. In FIG. 2, the equalizing means 301 is a digital filter which inputs a reproduction signal and performs equalization with the frequency characteristic of the equation (14), and its output is given to the decoder 205. The other parts of FIGS. 2 and 3 show the decoder 205, and the output of the equalizing means 301 is the branch length calculators 302-3.
Given to 05.

The branch length calculators 302 to 305 are circuits for calculating the second to seventh expressions of the expression (29). That is, the branch length calculator 302 calculates A / 2−z _k , and the branch length calculator 303
Calculates 2 (A−z _k ), and the branch length calculator 304 calculates 2 (A−z _k ).
(A + z _k ) is calculated, and the branch length calculator 305 calculates A / 2 +
This is a circuit for calculating z _k . The adder 306 is a circuit that adds the output of the branch length calculator 302 and the output of the subtractor 316 described later. Similarly, the adder 307 is the branch length calculator 30.
3 and the output of the subtractor 316 are added, and the adder 308
Is the output of the branch length calculator 304 and the output of the subtractor 315, the adder 309 is the output of the branch length calculator 305 and the output of the subtractor 317, and the adder 310 is the output of the branch length calculator 305. And the output of the subtractor 315.

The comparator / selector 311 is a circuit which inputs the output of the adder 302 and the initial value S ₀ = 0 and selects the minimum value as the metric m _k ′ (S ₀ ). The minimum value and the switching control. Output a signal. As for the switching control signal, "0" is output when the left term of the equation (31) is selected, and "1" is output when the right term is selected. Similarly, comparison selector 3
Reference numeral 12 is a circuit which inputs the output of the adder 307 and the output of the branch length calculator 302 and selects the minimum value thereof as the metric m _k ′ (S ₁ ). The comparison selector 313 is an adder 308.
And the output of the adder 309 are input, and the minimum value thereof is selected as the metric m _k ′ (S ₂ ). The comparison / selection unit 314 is a circuit that inputs the output of the adder 310 and the output of the subtractor 317 and selects the minimum value thereof as the metric m _k ′ (S ₃ ). The switching control signals of the comparison selectors 312 to 314 are (32) as in the case of the comparison selector 311.
It is assumed that "0" is output when the left term of each of equations (34) is selected, and "1" is output when the right term is selected.

The subtractor 315 subtracts the output of the comparison selector 311 from the output of the comparison selector 312, and outputs the metric m _k-1 '(S ₁ ) at time ( _{k- 1} ) with a time T _R delay. Circuit. Similarly, the subtractor 316 is a circuit that subtracts the output of the comparison selector 311 from the output of the comparison selector 313 and outputs the metric m _k-1 ′ (S ₂ ) at time (k−1). Subtractor 31
A circuit 7 subtracts the output of the comparison selector 311 from the output of the comparison selector 314 and outputs the metric m _k-1 '(S ₃ ) at time k-1.

The shift register 318 shown in FIG.
It is a circuit that holds the bit string corresponding to the survivor path to ₀ . Similarly, the shift register 319 corresponds to the bit string corresponding to the surviving path to the state S ₁ , the shift register 320 corresponds to the bit string corresponding to the surviving path to the state S ₂ , and the shift register 321 corresponds to the surviving path to the state S ₃ . This is a circuit that holds each bit string.

The switch 322 is based on the switching control signal output from the comparison selector 311, and in the formula (31), mi
When the left term of the n function is selected, the shift register 31
When the right term of the min function is selected, the contents of 8 are retained as they are, and the shift register 318 is set in the shift register 32.
This is a circuit for instructing to copy the contents of 0. After that, in either case, the contents of the shift register 318 are shifted to the right by one bit, and the binary value "0" corresponding to the state S ₀ is fed.

Similarly, the switch 323 is used for the comparison selector 31.
Based on the switching control signal of 2, in equation (32), min
When the left term of the function is selected, the shift register 319
Is a circuit for instructing the shift register 319 to copy the contents of the shift register 320 when the right term of the min function is selected. After this, in any case, the shift register 319
2 corresponding to state S ₁ by shifting the contents of
The decimal value "1" is fed.

The switch 324 copies the contents of the shift register 319 to the shift register 320 when the left term of the min function is selected in the equation (33) based on the switching control signal of the comparison selector 313, and the min A circuit for instructing the shift register 320 to copy the contents of the shift register 321 when the right term of the function is selected. After this, in either case, the contents of the shift register 320 are shifted to the right by one bit, and the binary value “0” corresponding to the state S ₂ is fed.

The switch 325 copies the contents of the shift register 319 to the shift register 321 when the left term of the min function is selected in the equation (34) based on the switching control signal of the comparison selector 314, and the min When the right term of the function is selected, it is a circuit for instructing to hold the content of the shift register 321 as it is. After that, in any case, the contents of the shift register 321 are shifted to the right by one bit, and the binary value "1" corresponding to the state S ₃ is fed.

A buffer is provided in each of the shift registers 318 to 321, and the updated contents of the shift register are always held in this buffer. When copying from the shift register A to the shift register B, the contents of the buffer of the shift register A are copied to the shift register B. By doing this, copying between shift registers can be performed smoothly.

Here, the branch length calculators 302 to 305 and the adders 306 to 310 constitute a likelihood calculating means for calculating the likelihood of the state transition from the output of the equalizing means 301 and the signal sequence. Further, the comparison selectors 311 to 314 and the subtractors 315 to 317 calculate a new metric at the present time from the output of the likelihood calculating means and the metric indicating the certainty of each state at the immediately previous time. It constitutes a metric calculation means for performing. In addition, shift registers 318 to 32
1 and the switches 322 to 325 constitute a survival data holding unit that sequentially updates and holds the data series corresponding to the most probable state transition.

In the equalizing / decoding apparatus of the first embodiment configured as described above, the equalizing output z is output from the equalizing means 301.
_{Given k} , the branch length calculator 302 calculates 0.5-z
_K , the branch length calculator 303 calculates 2 · (1-z _K ), the branch length calculator 304 calculates 2 · (1 + z _K ), and the branch length calculator 305
Calculates 0.5 + z _K respectively. After that, the adder 306 calculates the right term of the min function of Expression (31) and the adder 307 calculates (3
2) the right term of the min function of the equation, the adder 308 the left term of the min function of the equation (33), and the adder 309 the min of the equation (33).
The right term of the function and the adder 310 respectively calculate the left term of the min function of Expression (34).

The comparison selector 311 calculates the value of the expression (31), the comparison selector 312 calculates the value of the expression (32), and the comparison selector 313 calculates the value of the expression (33). Bowl 3
14 calculates the value of equation (34). The subtractor 315 subtracts the output of the comparison selector 311 from the output of the comparison selector 312, and outputs the metric m _k-1 '(S ₁ ). Similarly, the subtractor 316 uses the output of the comparison and selection unit 313 to compare and select the comparison and selection unit 311.
Is subtracted and the metric m _k-1 '(S ₂ ) is output. The subtractor 317 outputs the output of the comparison selector 314 to the comparison selector 3
The output of 11 is subtracted, and the metric m _k-1 '(S ₃ ) is output.

As a result of the above signal processing, if the lengths of the shift registers 318 to 321 are sufficiently long, the surviving paths are unified near the final stage of the shift register, and the output is the same regardless of which shift register is taken out. The result is obtained. However, the shift registers 318-321
If the length is not sufficient, the value may differ depending on the output shift register. In such cases, it is most reasonable to choose the output from the surviving paths with the smallest metric.

Among the metrics calculated based on the equations (31) to (34), the most probable survival path is obtained,
The signal is decoded when the output is taken from the shift register holding this survivor path. For example, if the minimum value of the metric is m _K '(S ₀ ), then the output is in state S _0.
Shift register 31 holding the surviving path to
Take out from 8.

As described above, an equalization / decoding device which can largely remove the influence of crosstalk noise in the output of the equalizing means 301 and can obtain the maximum likelihood decoding sequence can be easily realized. The equalization / decoding device of the first embodiment described so far can decode the maximum likelihood sequence only for uncorrelated noise such that the expression (22) holds. However, the equation (22) itself does not hold for correlated noise, and the maximum likelihood sequence cannot be decoded. However, when the noise correlation is relatively small, the equalization / decoding device of this embodiment can also decode the quasi-maximum likelihood sequence. In this case, the adverse effect of the noise correlation on the decoding error rate is sufficiently small, so there is practically no problem.

However, when the noise correlation is large, this effect cannot be ignored, and there is room for further improvement. Therefore, as a second embodiment, an equalization / decoding device that can decode the maximum likelihood sequence even when the equalization noise has a correlation will be described.

In the equalization / decoding apparatus of the first embodiment, the survivor paths leading to each of the four states S _i (i = 0 to 3) regarding the recording code are held. Therefore, a noise sequence {n _Ki } (i = 0 to 3) for each surviving path is obtained by the output sequence {z _K } of the equalizer and this surviving path, but only one true noise sequence is obtained. is there. Regarding the statistical properties of the true noise sequence, it matches the statistical properties of the original noise that can be known in advance.

In this case, the residual noise of the difference between the predicted noise series predicted from the true noise series and the true noise series becomes random noise. Conversely, the statistical properties of the noise sequence for the erroneous survivor path differ from the statistical properties of the original noise. For such false noise sequences, subtracting the noise predicted using statistical properties from the equalizer output serves to amplify the noise as a whole. Also, the correlation of noise is not removed. Therefore, the value of the negative likelihood function for the signal sequence obtained by subtracting the prediction noise from the true noise sequence is
The value is smaller than the value of the negative likelihood function of the signal sequence obtained by subtracting the prediction noise from the erroneous noise, and correct decoding is possible with a higher probability than in the past.

As described above, the principle of the second embodiment can be realized by embodying the following expression (35).

[Equation 35] Here, z _Ki (i = 0 to 3) in the equation (35) is the noise sequence {n _Ki corresponding to the surviving path from the output z _{K of the} equalization means to the state S _i (i = 0 to 3). } Is a value obtained by subtracting the prediction noise n _Ki ′ from ## _{EQU1 ##}

[Equation 36] The prediction noise n _Ki 'is given by the equation (37).

[Equation 37] Here, { _cm } is a prediction coefficient and q is the number of noises used for prediction.

Since the residual noise can be regarded as uncorrelated Gaussian noise having a mean value of 0 and a variance σ ² , the likelihood function in the equation (35) is expressed by the equation (38) as in the case of the equation (24).

[Equation 38]

Similar to the case of the first embodiment, the first term on the right side of the equation (38) is common, and 1 / 2σ of the second term on the right side is used.
^{Since 2 is} also a common factor, it can be deleted. In this way, the normalized metric as in the following equations (39) to (42) is obtained.

[Formula 39]

[Formula 40]

[Formula 41]

[Equation 42] Where l _Kij is the length of the normalized branch that transits from the state S (k-1) = S _i (i = 0 to 3) to the state S (k) = S _j (j = 0 to 3). And is given by the following equation (43).

[Equation 43]

In this embodiment as well, the same measure as in the first embodiment is taken in order to prevent the metric overflow. That is, it represents a metric normalized by the following equations (44) to (47).

[Equation 44]

[Equation 45]

[Equation 46]

[Equation 47]

Now, the equalization / decoding apparatus of the second embodiment will be specifically described with reference to the block diagrams of FIGS. In this figure, the equalizing means 301 and the branch length calculator 40
6 to 413, adders 414 to 419, comparison selector 420
~ 423, Subtractors 424-426, Shift Register 42
7 to 430 and switches 431 to 434 are respectively provided as in the first embodiment, and the functional description of those circuits will be omitted. Unlike the first embodiment, subtractors 402 to 405 are provided before the branch length calculators 403 to 413, and a memory 435 is provided at the output end of the equalizer 401. Further, noise extraction predictors 436 to 439 are provided at the output terminals of the shift registers 427 to 430, respectively.

The equalizing means 301 in FIG. 4 is an equalizing digital filter having the frequency characteristic of the equation (14), and its equalized output z _k is given to the + input ends of the subtracters 402 to 405 and the memory 435. . The subtractor 402 uses the noise sequence {n _k0 } corresponding to the surviving path to reach the state S ₀ from the output of the equalizing means 301 as shown in equation (36), and the prediction obtained by the noise extraction predictor 436. This is a circuit for subtracting the noise n _K0 '.

Similarly, the subtractor 403 uses the noise sequence {n _k1 } corresponding to the surviving path reaching the state S ₁ from the output of the equalizer 301 to obtain the prediction noise n _k1 obtained by the noise extraction predictor 437. It is a circuit that subtracts'. Subtractor 404
Is a circuit for subtracting the prediction noise n _k2 'obtained by the noise extraction predictor 437 from the output of the equalizing means 301 using the noise sequence {n _k2 } corresponding to the surviving path to the state S ₂ . The subtractor 405 outputs the noise sequence {n _K3 } corresponding to the surviving path from the output of the equalizer 301 to the state S ₃ .
Is a circuit for subtracting the prediction noise n _K3 'obtained by the noise extraction predictor 439 by using.

The branch length calculators 406 to 413 are circuits for calculating the normalized branch length in the equation (43). The branch length calculator 406 is l _K00 , and the branch length calculator 407 is l
_The branch length calculator 408 _outputs l _K12 , the branch length calculator 409 _outputs l _K13 , the branch length calculator 410 _outputs l _K20 , the branch length calculator 411 _outputs l _K21 , and the branch length calculator 412 _outputs l _K21.
The branch length calculator 414 for _K32 is a circuit for calculating l _K33 , respectively.

The adder 414 is the left term of the min function of the equation (46), the adder 415 is the left term of the min function of the equation (47), and the adder 416 is the right term of the min function of the equation (44). 417
Is the right term of the min function in equation (45), and the adder 418 is (4
The right term of the min function of the equation (6) and the adder 419 are
This is a circuit that calculates the right term of the min function.

The comparison selector 420 of FIG. 5 is the branch length calculator 4.
06 and the output of the adder 416 are compared, the smaller one is output, and 2 is output when the output of the branch length calculator 406 is selected.
When the output of the adder 416 is selected as the binary value "0", the binary value "1" is output to the switch 431 as a switching control signal. Similarly, the comparison selector 421 compares the outputs of the branch length calculator 407 and the adder 417, outputs the smaller one, and adds the binary value “0” when the output of the branch length calculator 407 is selected. When the output of the device 417 is selected, the binary value "1" is output to the switch 432 as a switching control signal. The comparison selector 432 compares the outputs of the adder 414 and the adder 418, outputs the smaller one, and
When the output of 4 is selected, the binary value "0" is added to the adder 418.
When the output of 1 is selected, the binary value “1” is output to the switch 433 as a switching control signal. Further, the comparison selector 423 compares the outputs of the adder 415 and the adder 419, outputs the smaller one, and outputs the binary value “0” when the output of the adder 415 is selected and the output of the adder 419. 2 if selected
The binary value "1" is output to the switch 434 as a switching control signal. Thus, the four comparison selectors 420 to 423 are
The min functions in equations (44) to (47) are respectively calculated.

Next, the subtractor 424 is a circuit for subtracting the output of the comparison selector 420 from the output of the comparison selector 421, and the output thereof is given to the adders 414 and 415. Similarly, the subtractor 425 is a circuit that subtracts the output of the comparison selector 420 from the output of the comparison selector 422, and the output thereof is given to the adders 416 and 417. The subtractor 426 is
This is a circuit for subtracting the output of the comparison / selection device 420 from the output of the comparison / selection device 423.
Given to.

The shift registers 427 to 430 shown in FIG.
The switches 431 to 434 perform the same operation as in the first embodiment. That is, the shift register 427 holds the bit string corresponding to the surviving path reaching the state S ₀ , the shift register 428 holds the bit string corresponding to the surviving path reaching the state S ₁ , and the shift register 429.
Holds the bit string corresponding to the surviving path leading to the state S ₂ , and the shift register 430 holds the bit string corresponding to the surviving path leading to the state S ₃ . In addition, switch 4
Reference numerals 31 to 434 are circuits that form a copy path between the shift registers in order to sequentially update the bit string corresponding to the surviving path.

Now, the memory 435 of FIG.
It is a memory that always holds the latest q outputs in 1. The noise extraction predictor 436 of FIG.
The output of the inputs the output of the shift register 427, from the q ideal reproduction output corresponding to the surviving path leading to the state S _0, obtains a q-number of noise that corresponds to the surviving path leading to the state S _0, This is a circuit for calculating the prediction noise n _K0 'from these noises and the equation (37).

Similarly, the noise extraction predictor 437 uses the memory 4
35 output and shift register 428 output are input,
From the q ideal reproduction output corresponding to the surviving path leading to the state S _1, obtains a q-number of noise that corresponds to the surviving path leading to the state S _1, the prediction from these noise and (37) below the noise n _K1 It is a circuit that calculates'. Noise extraction predictor 43
8 inputs the output of the memory 435 and the output of the shift register 429, and outputs from q ideal reproduction outputs corresponding to the surviving paths reaching the state S ₂ to q ideal reproducing outputs reaching the state S _2. The noises of (3
This is a circuit for calculating the prediction noise n _K2 'from the equation (7). The noise extraction predictor 439, the output of the memory 435, inputs the output of the shift register 430, from the q ideal reproduction output corresponding to a surviving path leading to the state S _3, the surviving path to the state S _{3 Is} a circuit that _obtains q noises corresponding to and calculates the prediction noise n _K3 'from these noises and the equation (37).

These prediction noises n _Ki '(i = 0 to 3) are given to subtractors 402 to 405, respectively, and subtracted from the output of the equalizing means 301. By repeating such an operation for each time, the correlation of noise is effectively removed, and an equalization / decoding device that generates a true maximum likelihood decoding sequence can be realized.

Here, the branch length calculators 406 to 413 and the adders 414 to 419 constitute a likelihood calculating means for calculating the likelihood of the state transition from the output of the equalizing means 301 and the signal sequence. Further, the comparison / selectors 420 to 423 and the subtractors 424 to 426 calculate a new metric at the present time from the output of the likelihood calculation means and the metric indicating the likelihood of each state at the immediately preceding time point. It constitutes a metric calculation means for performing. In addition, shift registers 427-43
0 and the switches 431 to 434 constitute a survival data holding unit that sequentially updates and holds the data series corresponding to the most probable state transition.

Further, the memory 435 constitutes an equalization output holding means for sequentially updating and holding a plurality of outputs of the equalization means 301. The noise extraction predictors 436 to 439 constitute noise extraction means for extracting a noise series from the equalized output holding means and the survival data holding means. Further, the subtractor 402-
Reference numeral 405 constitutes a predictive noise calculating means for calculating predictive noise using the noise sequence of the noise extracting means.

As in the case of the first embodiment, if the lengths of the shift registers 427 to 430 are sufficiently long, the surviving paths are unified near the final stage of the shift register.
Equivalent results are obtained from the output of any shift register. However, the shift registers 427-4
If 30 is not long enough, it is most reasonable to choose the output from the surviving paths with the smallest metric. That is, the most probable survival path having the smallest value among the metrics calculated based on the equations (44) to (47) is obtained, and the output may be taken out from the shift register holding this survival path. In this way, even when there is a correlation between noises, it is possible to realize an equalization / decoding device that eliminates the influence of crosstalk noise, as in the first embodiment.

[0078]

As described above, according to the first to third aspects of the present invention, the equalizing means is provided when decoding the recording code sequence in the state where the uncorrelated noise is added to the reproduction sequence signal. As a result, it is possible to suppress the crosstalk noise of low frequency components. Further, by providing the decoding means including the likelihood calculation means, the metric calculation means, and the survival data holding means, it is possible to reduce the decoding error rate in the same S / N. Therefore, the effect that the recording density of the recording device can be improved is obtained.

According to the inventions of claims 4 to 6 of the present application, in addition to the effects of the inventions of claims 1 to 3, by adding the equalized output holding means and the noise extracting means to the decoding means, there is a correlation. The signal can be decoded using the Viterbi decoding method even in the presence of noise. Further, deterioration of S / N due to crosstalk can be suppressed as compared with the conventional method, and an equalization / decoding device can be realized with almost the same circuit scale as the conventional method.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an equalization / decoding device according to first and second embodiments of the present invention.

FIG. 2 is a block diagram (part 1) showing a specific configuration of the equalization / decoding device according to the first exemplary embodiment of the present invention.

FIG. 3 is a block diagram (part 2) showing a specific configuration of the equalization / decoding device according to the first exemplary embodiment of the present invention.

FIG. 4 is a block diagram (part 1) showing a specific configuration of an equalization / decoding device in a second exemplary embodiment of the present invention.

FIG. 5 is a block diagram (No. 2) showing a specific configuration of the equalization / decoding device according to the second exemplary embodiment of the present invention.

FIG. 6 is a block diagram (No. 3) showing a specific configuration of the equalization / decoding device according to the second exemplary embodiment of the present invention.

FIG. 7 is a block diagram showing an overall configuration of an equalization / decoding device in a conventional example.

FIG. 8 is an explanatory diagram showing frequency characteristics of a conventional equalizing means.

FIG. 9 is an explanatory diagram showing frequency characteristics of the equalizing means of this embodiment.

FIG. 10 is an error rate of a decoded signal when the equalization / decoding device of the present example and the conventional example are used.

FIG. 11 is a state transition diagram in the equalization / decoding device of the present exemplary embodiment.

FIG. 12 is a trellis diagram in the equalization / decoding device of the present embodiment.

[Explanation of symbols]

201 input end 202 equalizer 203 delay device 204,315-317,402-405,424-4
26 Subtractor 205 Decoder 206 Output terminal 301 Equalization means 302 to 305, 406 to 413 Branch length calculator 306 to 310, 414 to 419 Adder 311 to 314, 420 to 423 Comparison selector 318 to 321, 427 to 430 Shift register 322-325, 431-434 Switch 435 Memory 436-439 Noise extraction predictor

Claims (6)

[Claims] 1. An encoded arbitrary input data sequence {b
_K } (k is an integer indicating discrete time) is applied to a recording medium or a signal transmission path, and a plurality of states defined by a signal sequence of a predetermined sampling period from a reception sequence obtained from the recording medium or the signal transmission path. An equalization / decoding device for uniquely decoding a signal sequence {p _K } by a state transition between these states, and equalizing means for correcting the frequency characteristic of a signal component of an input received sequence; From a likelihood calculation means for calculating the likelihood of the state transition from the output of the conversion means and the signal sequence, and from the output of the likelihood calculation means and a metric indicating the likelihood of each state one sampling before, survival data holding sequentially updated holding and metric calculating means for calculating a signal sequence {p _K} corresponding to the most likely state transitions leading to each of the states a new metric at the current time Equalizing and decoding apparatus characterized by comprising a means. 2. The equalizer means inputs an signal obtained from the recording medium or a signal transmission path and removes waveform interference, and a delay for delaying the output of the equalizer by one sampling period. And a subtractor for subtracting the output of the delay device from the output of the equalizer.
The described equalization / decoding device. 3. The equalizing means generates a signal sequence {p _K } based on the result of subtracting twice the signal one sampling before from the addition result of the current signal and the signal two sampling before. The equalization / decoding device according to claim 1, wherein the equalization / decoding device is a device. 4. An arbitrary encoded input data sequence {b
_K } (k is an integer indicating discrete time) is applied to a recording medium or a signal transmission path, and a plurality of states defined by a signal sequence of a predetermined sampling period from a reception sequence obtained from the recording medium or the signal transmission path. An equalization / decoding device for uniquely decoding a signal sequence {p _K } by a state transition between these states, and equalizing means for correcting the frequency characteristic of a signal component of an input received sequence; Likelihood calculating means for calculating the likelihood of the state transition from the output of the converting means, the signal sequence and the prediction noise, and a metric representing the likelihood of each output of the likelihood calculating means and each state one sampling before. Therefore, the metric calculation means for calculating new metric at the present time, and the surviving data for sequentially updating and holding the data series corresponding to the most probable state transition leading to each state. Holding means, equalization output holding means for sequentially updating and holding a plurality of outputs of the equalization means, noise extraction means for extracting a noise sequence from the equalization output holding means and the survival data holding means, An equalization / decoding device comprising: a prediction noise calculation unit that calculates the prediction noise using the noise sequence of the noise extraction unit. 5. The equalizing means inputs an signal obtained from the recording medium or a signal transmission path and removes waveform interference, and a delay for delaying the output of the equalizer by one sampling period. And a subtractor that subtracts the output of the delay device from the output of the equalizer.
The described equalization / decoding device. 6. The equalizing means uses the current data and 2
The equalization / decoding according to claim 4, wherein a signal sequence {p _K } obtained based on a result obtained by subtracting twice the signal before one sampling from the addition result of the signals before sampling is output. apparatus.