JPH07161838A - Capacitor device and method of manufacturing the capacitor device - Google Patents

Abstract

PURPOSE: To easily manufacture a ferroelectric capacitor which can be used for a semiconductor storage device by allowing a capacitor dielectric to be a single-crystalline ferroelectric layer, while an electrode is provided vertical to a substrate. CONSTITUTION: On the surface of a purified substrate 1, a buffer layer 2 is deposited for adaptation to thermal expansion behavior and crystallographic lattice behavior. And over it, a ferroelectric layer 3 is provided by a deposition method such that tight and homogeneous epitaxial layer of desired composition and stoichiometry can be generated on a large surface. Further, an insulating layer 4 is deposited, and the ferroelectric layer 3 and the insulating layer 4 are structured together, forming a ferroelectric wave 5. Then, on the side surface of the ferroelectric wave 5, an electrode layer 6 is provided, thus constituting a ferroelectric capacitor. Thus, a ferroelectric capacitor having a single- crystalline ferroelectric layer can be manufactured easily and is used suitably for a semiconductor storage device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor device and a method for manufacturing the capacitor device.

A thin layer of perovskite composed of a ferroelectric material, for example, the system of zircon-lead titanate (PZT), is
Used as a dielectric in ferroelectric capacitors in new types of semiconductor memory devices. Unlike the silicon-containing materials that have been used in the case of semiconductor memory devices to date, memory cell devices with ferroelectric capacitors have two essential advantages. Ferroelectric polarization can be switched between two states by applying an appropriate voltage. In this way, the information written in the storage device is
It is maintained even after the operating voltage is cut off, so that a nonvolatile data storage device can be obtained. Moreover, ferroelectrics have a dielectric constant that is increased by a factor of about two, so that a ferroelectric capacitor, at the same volume, has a higher dielectric constant than conventional capacitors used in memory cells. It has a correspondingly high capacitance. Therefore, it is possible to store charges or information in an essentially smaller area. This has a higher storage capacity, as it allows the use of flat-plate ferroelectric capacitors and thus eliminates the need to exhaust the "third dimension" to the storage cells. It enables the manufacture of highly integrated semiconductor members and simplification of the memory device structure.

[0003]

2. Description of the Related Art Semiconductor memory devices having ferroelectric capacitors are disclosed in, for example, R. Cuppens, PK Larsen and GACM.
Spierings, Microelectronic Engineering 19 (199
2), pages 245-252. This semiconductor memory device has a stacked layer structure oriented parallel to the substrate, and the individual layers of this layer structure are formed in sequence. Therefore, all individual layers and thus the interfaces between the layers are necessarily exposed to the operating conditions for obtaining the next layer, in particular the operating temperature. However, ferroelectric layers with the above-mentioned advantageous properties require high working temperatures of 450 to about 900 ° C. for their production. This requires a base electrode with sufficient thermal stability, in which case the selection of suitable materials is severely limited. Moreover, the limited thermal stability of the base electrode causes a limitation of working temperature and working time during the deposition of the ferroelectric layer. This results in a disadvantageous property that cannot be optimized, which is further exacerbated by the diffusion process between the electrode and the ferroelectric layer.

In order to achieve the optimum advantageous properties of ferroelectric capacitors, epitaxially grown single crystal ferroelectric layers are required. However, such a ferroelectric layer cannot be produced on the platinum-based electrodes that have hitherto been mainly used, since the platinum-based electrodes can only be obtained polycrystalline on silicon. This is because it can not be obtained and can be obtained in a state in which it is not crystallographically oriented, or it can be obtained only in a weakly oriented state.

[0005]

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an improved ferroelectric capacitor having a single crystal ferroelectric layer that can be easily manufactured and used in semiconductor memory devices. It is to be.

[0006]

According to the present invention, the above-mentioned problems are solved by the capacitor device according to claim 1.

[0007]

Further forms of the invention and a method of manufacturing the capacitor arrangement can be read from any one of the further claims.

The capacitor according to the invention has electrodes arranged perpendicular to the substrate. This has the advantage that the electrodes can be applied after the ferroelectric layer has been produced. Therefore, the generation or deposition of the ferroelectric layer does not depend on the electrode material and the method of forming the electrode.
Therefore, the ferroelectric layer is formed as an epitaxial layer on the single crystal semiconductor substrate. One or, optionally, multiple buffer layers between the substrate and the ferroelectric layer
hten) can be used for crystal lattice matching and as a diffusion barrier. As a result, the single crystal ferroelectric layer has the optimum properties for capacitors. The ferroelectric layer exhibits a pronounced hysteretic behavior, can be easily polarized or switched, and retains this property even after about 10 ¹⁶ switching cycles. The interface to the electrode is stable because it is no longer exposed to the conditions for layer deposition of the ferroelectric layer. Therefore, no disturbing diffusion process takes place between the electrode and the ferroelectric layer, since the electrode can only be applied at a moderately elevated temperature. This greatly expands the choice for the electrode material, since it is no longer necessary to pay attention to the thermal stability of the electrode.

Silicon has been chosen as the preferred substrate material, since it promotes the epitaxy of the ferroelectric layer and is required for the manufacture of semiconductor memory devices for triggering, writing and reading. This is because it is suitable for accommodating integrated circuits. However, in principle, other semiconductor substrates on which highly integrated circuits can be implemented are likewise suitable.

Ferroelectric materials suitable for the present invention include, for example:
It is a perovskite composed of a system of zircon and lead titanate (PZT). The properties of this material vary widely by doping and are optimized with respect to various parameters. Suitable doping substances for PZT are, for example, manganese, lanthanum, nickel or niobium or else selected from the group of transition metals, in particular from the 3rd to 8th subgroups of the periodic table of the elements.

Other suitable ferroelectrics are, for example, bismuth titanate and barium titanate, strontium or barium niobates or other ferroelectric compounds.
Of particular advantage is a unipolar ferroelectric, which is certainly very difficult to manufacture, however, in the oriented state it is possible to It has only an axis. Capacitors oriented in this way exhibit a particularly simple polarizability with significantly different switching states. In general, the ferroelectrics suitable for the invention must have a high polarizability and a good switchability and must be epitaxially producible.

For ferroelectric layer epitaxy, a buffer layer is necessary due to the matching of the crystal lattice. This buffer layer is likewise a single crystal epitaxial layer, which must be electrically isolated and sufficiently thin. To obtain superconducting layers, a series of buffer layers have already been developed, which layers can also be used in the case of the method according to the invention. Suitable materials are, for example, zirconium oxide, yttrium oxide, magnesium oxide or yttrium-stabilized zirconium oxide.

Next, a method of manufacturing the capacitor device according to the present invention will be described in detail with reference to an embodiment and four drawings attached thereto.

These figures are schematic cross-sectional views showing various processing steps in the manufacture of a capacitor device and a semiconductor memory device manufactured from it.

[0015]

EXAMPLE FIG. 1: As a substrate (1), for example, [10
0] -Select oriented silicon wafers. Board (1)
On the cleaned surface of, the buffer layer (2) is first deposited for matching the thermal expansion behavior and the crystallographic lattice behavior. The film thickness of the buffer layer is about 50 to 200 nm.
For this purpose, a method of promoting the epitaxial growth of the buffer layer (2) is selected. Suitable methods are eg sputter, MOCVD or MBE (molecular beam epitaxy).
Is. Depending on the material of the ferroelectric layer to be applied later, matching the crystal lattice may require a separate buffer layer in order to carry out the necessary crystal lattice matching in some smaller steps. is there. Moreover, at least one buffer layer (2) is used in a further process as a barrier layer from diffusion from the substrate into the ferroelectric layer and in the reverse direction.

Further, a ferroelectric layer (3) is applied on the buffer layer (2). This application is likewise carried out by a suitable deposition method which is capable of producing on a large surface a tight and homogeneous epitaxial layer of the desired composition and stoichiometry. Advantageously, a method is selected which is compatible with the methods commonly used in microelectronics. Essentially this method
It is a method already used for the production of buffer layers, which can be used to produce high quality layers.

Since the film thickness of the ferroelectric layer (3) is proportional to the capacitor area to be provided later and hence the capacitance of the capacitor, it has been used so far in the flat plate structure of the known semiconductor memory device having the ferroelectric layer. It is required to have a film thickness that is as thick as possible, for example, 1 μm, which clearly exceeds the film thickness.

In the next step, an insulating layer (4) is deposited on the ferroelectric layer (3). The choice of suitable material for this insulating layer depends on the type of ferroelectric layer (3). An insulating layer made of silicon oxide, silicon nitride or glass, which is commonly used in silicon semiconductor technology, is suitable. The thickness of the insulating layer (4) can be freely selected and is, for example, 1 μm. Since the insulating layer is used as a mask in the subsequent structuring method, the film thickness can also be chosen thicker, since some removal occurs during structuring.

In the next step, the ferroelectric layer (3) and the insulating layer (4) applied thereon are structured together. Advantageously, for this structuring, mutually parallel strip masters are selected, the width of the remaining web corresponding to the electrode spacing of the subsequent capacitor. A suitable electrode spacing is in each case less than 500 nm, in particular 200-40
It is 0 nm. This ensures that the polarization of the capacitor can be reliably switched at the working voltage commonly used in small electronics, for example 5 volts. The spacing of the webs from each other depends on the desired integration density or area provided for the semiconductor memory cells belonging to each capacitor. For example, a semiconductor memory device having a storage capacity of 1 gigabit per memory cell, which is envisioned, has an area of about 1 μm ² , and on top of this area, a read transistor and a circuit belonging thereto are provided in addition to a capacitor. Must be placed together. Therefore, the degree of horizontal size commonly used for this storage device is 0.5 μm.
It is within the following range.

The structuring can be carried out by the known "dry state" processes, for example plasma etching or reactive ion etching. Photoresist technology is used to define the structured master, in which case the insulating layer (4) to be etched next during further processing is due to the underlying ferroelectric layer (3). Can be used as a mask. Two of the webs (5) obtained by etching from the ferroelectric layer (3) are shown in FIG. 2 by way of example, with the still intact insulating layer (4) on the webs. This structuring method is advantageously adjusted anisotropically to the extent that vertical sidewalls of the web (5) are produced.

The capacitor is then equipped with electrodes defined by the ferroelectric web (5). Various methods are suitable for this. For example, it is possible to deposit a similar electrode layer on the entire device shown in FIG. 2 and in the next step structure so that only the side walls of the web are covered with the electrode layer. It is also possible to do so. It is also possible then to fill the recesses between the webs (5) with another insulating material or dielectric. In order to further define the electrodes, the sides of the web are exposed completely or partially, for example by etching corresponding holes or depressions adjacent to and parallel to the web (5). Furthermore, these recesses can be selectively filled with electrode material. In the case of the method of depositing a similar electrode layer on the whole device, after the similar deposition and the structuring of the electrode layer, the still remaining spaces between the electrode-coated webs are likewise filled with a dielectric. To do.

FIG. 3 shows the device thus produced in schematic cross-section. The individual capacitors are
It consists only of a ferroelectric (5) structured in the form of a web of width d and two electrode layers (6) each applied to the sides of the web (5). Two adjacent capacitors in each case are separated from each other by a dielectric (7) existing between them and covered by a residue (8) which was originally an insulating layer (4). Has been done.

The masking technique and the mask orientation can be carried out particularly easily, since all the structuring processes used up to now can be carried out along parallel structure lines. In the next step, the capacitors are finally subdivided by structuring steps across the web into individual capacitors of the desired size or capacitance.

The capacitor device manufactured according to the present invention forms the central part of a ferroelectric semiconductor memory device, and for this ferroelectric semiconductor memory device a possible structure is shown in FIG.
In a schematic cross section. Storage cell
A first electrode (12), a second electrode (6) and a ferroelectric (5) arranged between these electrodes and on the buffer layer (2).
And a strong conductive capacitor having The first electrode (12) of the capacitor is coupled to a drive line by which the storage cell can be "written" or the capacitor can be polarized. In the immediate vicinity of the capacitor, a field-effect transistor consisting of source and drain regions (9), (13) and a gate electrode (11) connected to the word line is arranged as a read transistor. The second electrode (6) of the capacitor is coupled to the first source and drain region (13) of the field effect transistor, and the bit line is coupled to the second source and drain region (9). Has been done.

The semiconductor memory device in which the capacitor device according to the invention with an integrated circuit is used has the following advantages in summary: The capacitor exhibits optimum switching behavior due to the monocrystalline ferroelectric layer. . In addition, single crystal materials have the additional advantage of being able to be precisely structured, which is especially sub-μm for semiconductor memory chips with high capacity (256 megabits and above). Storage capacitors in the range of dimensions are needed. A known semiconductor memory device having a ferroelectric capacitor uses a polycrystalline ferroelectric layer, which cannot be precisely structured and has an unclean interface and thus an interface. May cause problems. Furthermore, unlike this known ferroelectric capacitor,
During the deposition of the ferroelectric layer at optimally high temperatures up to 0 ° C., the interface problems that may occur in combination with the layers underlying it are avoided. This also avoids the effect of producing fatigue (fatigue process) after approximately 10 ¹⁰ switching cycles in the known ferroelectric semiconductor memory device.

The electrode materials customary in semiconductor technology can be used, so that the manufacture of ferroelectric capacitors is comfortably possible with known semiconductor processing steps and methods.

Further, according to the present invention, it is possible to manufacture a semiconductor memory device chip with an increased memory device capacity, since the required area of the semiconductor memory device chip is the same as that of a known ferroelectric capacitor. On the other hand, as well as with respect to the known conventional storage cells, it is clearly reduced. Moreover, ferroelectric capacitors or storage cells with ferroelectric capacitors are non-volatile and insensitive to electromagnetic radiation, for example α rays.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing step of a capacitor device according to the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing step of the capacitor device according to the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing step of the capacitor device according to the present invention.

FIG. 4 is a cross-sectional view of a semiconductor memory device obtained from a capacitor device according to the present invention.

[Explanation of symbols]

1 substrate, 2 buffer layer, 3 ferroelectric layer, 4
Insulation layer, 5 webs, 6 and 12 electrodes

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/822

Claims (12)

[Claims] 1. A capacitor device on a single crystal semiconductor substrate (1), wherein the capacitor dielectric is a single crystal ferroelectric layer (5) and the electrodes (6) are arranged perpendicular to the substrate (1). Capacitor device characterized in that 2. A device according to claim 1, wherein a single crystal ferroelectric layer is arranged on at least one buffer layer (2), which buffer layer enables epitaxial growth of the ferroelectric layer (3). 3. A device according to claim 1, wherein the material of the ferroelectric layer (3) is selected from the system of zircon and lead titanate. 4. The device according to claim 1, wherein the substrate (1) is made of silicon crystals. 5. Device according to claim 1, wherein the electrodes (6, 12) are made of platinum. 6. The capacitor according to claim 1, wherein each capacitor is a part of a semiconductor memory cell having at least one selection transistor integrated in the semiconductor substrate (1). The described device. 7. The buffer layer (2) is zirconium oxide,
7. Device according to any one of the preceding claims, selected from yttrium-stabilized zirconium oxide, magnesium oxide, yttrium oxide or strontium titanate. 8. A method of manufacturing a capacitor device having a single crystal ferroelectric layer (3) on a single crystal semiconductor substrate (1), comprising: first forming at least one epitaxial buffer layer (2) on a semiconductor substrate (1). 1) on top of: -epitaxially depositing a ferroelectric layer (3) on at least one buffer layer (2);-creating an insulating layer (4) on the ferroelectric layer (3);-insulating layer Structuring (4) and the ferroelectric layer (3) into a web (5) having substantially vertical side walls, the electrode material until at least the side walls of the web (5) are covered with the electrode material. A method of manufacturing a capacitor device, characterized in that it is deposited and-structures each capacitor to electrically separate the web (5) and the electrode material (6). 9. The method according to claim 8, wherein a layer of lead zirconium titanate is deposited as the ferroelectric layer (3) by a method selected from sputtering, MOCVD and MBE. 10. Method according to claim 8 or 9, wherein a dry etching method is used for structuring the ferroelectric layer (3). 11. The method according to claim 8, wherein the width of the web (5) determines the electrode spacing of the capacitor and the width is selected in the range from 200 to 500 nm. 12. The method according to claim 8, wherein the capacitor device is post-processed into a highly integrated semiconductor memory device by integrating a read circuit and a write circuit in a semiconductor substrate.