JPH0716189Y2 - Break circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention is a program evaluation device for debugging a software program, etc., and analyzes an execution instruction code to determine a break instruction signal (stop instruction signal) or a trace instruction. The present invention relates to a break circuit that outputs a signal (execution trace instruction signal).

(Prior Art) Conventionally, as a technology in such a field, there is, for example, one as shown in FIG. 2 and FIG. The configuration will be described below with reference to the drawings.

2 and 3 are block diagrams of the break circuit in the conventional program evaluation apparatus.

The break circuit of FIG. 2 includes a latch circuit 1 and a logic circuit 2 for analyzing an instruction code, and the logic circuit 2 is composed of, for example, inverters 3 and 4 and an AND gate 5. In this break circuit, the latch circuit 1 takes in the execution instruction code CD by the latch signal LC, and the output Q of the latch circuit 1
Is analyzed by the logic circuit 2 and the break designating signal BK and the trace designating signal TC are output to a break generating circuit (not shown).

The break circuit shown in FIG. 3 includes a memory 6 which operates in response to a read / write control signal R / W, instead of the logic circuit 2 shown in FIG. The execution instruction code CD is latched by the latch circuit 1, and the latch circuit output Q is set to the address A0 of the memory 6.
By inputting to the memory 6 as .about.A7, the memory contents are read according to the execution instruction code CD. This allows
Read contents D0, D1 of memory 6 by execution instruction code CD
Changes, and the read contents D0 and D1 change to the break instruction signal BK.
Is output in the form of a trace instruction signal TC.

(Problems to be Solved by the Invention) However, the break circuit having the above configuration has the following problems.

In the circuit of FIG. 2, since the logic state of the logic circuit 2 is fixed, a plurality of execution instruction codes CD having different contents cannot be analyzed. Therefore, multiple execution instruction codes CD
When the analysis is performed, the number of logic circuits 2 corresponding to that is required, and there is a problem that the number of parts increases and the debug efficiency decreases accordingly.

Since the memory 6 is used in the circuit of FIG. 3, it is possible to analyze a plurality of execution instruction codes CD having different contents. However, the first byte of the execution instruction code CD (however, the byte is an arbitrary unit of data and usually points to 8 bits), the second byte, ... When the break instruction signal BK or the trace instruction signal TC is output when the instruction code CD matches the designated code, the latch circuits 1 and the memories 6 are provided for the maximum number of instruction codes, and read from each of the latch circuits 1 and the memory 6. The determined contents must be judged by the judging means to generate the break instruction signal BK or the trace instruction signal TC. Therefore, there is a problem that the number of parts is increased and the debug efficiency is reduced, which is not technically satisfactory.

The present invention provides a break circuit, which has been solved as a problem that the above-mentioned conventional technology has, by solving a problem that a plurality of instruction codes or an instruction composed of a plurality of instruction codes cannot be efficiently analyzed with a small number of parts. is there.

(Means for Solving the Problem) FIG. 1 is a block diagram of a break circuit in the program evaluation device of the present invention. The break circuit includes, for example, an instruction code fetching unit 10 that fetches an execution instruction code CD by a fetching control signal LC, and the output side of the instruction code fetching unit 10 writes / writes by a read / write control signal R / W.
An instruction code analysis unit 20 having a readable memory and using the execution instruction code CD as a lower address input of the memory
And a first counting means which is operated by a count signal CK and whose counting operation is controlled by the first read data output from the memory, and the output of the first counting means is set to an upper address of the memory. And a page updating circuit unit 30 which operates according to the count signal CK, and second counting means for counting the number of machine codes per instruction (the number of machine codes of executed instructions), and the output of the second counting means. And the output of the first counting means are compared with each other, and if the two coincide with each other, the second read data output from the memory is validated to output the break instruction signal BK or the trace instruction signal TC. 40 and 40 are provided.

(Operation) According to the present invention, since the break circuit is configured as described above, the execution instruction code CD is, for example, the instruction code fetching unit 10
Are latched by, and the latch output is given to the instruction code analysis unit 20 as a lower address. The counting operation is performed in the page update circuit unit 30 by the first read data output from the instruction code analysis unit 20, and the counting result is
It is given to the instruction code analysis unit 20 in the form of a high-order address.
As a result, the execution instruction code from the first byte (word) to the last byte (word) of the execution instruction code CD or the execution instruction code of a plurality of byte (word) instructions can be analyzed in the same memory. Further, in the byte number comparison unit 40, the number of executed instruction codes is counted, the count value is compared with the count value of the instruction code analysis unit 20, and when the two match, the instruction code analysis unit 20 outputs Since the read data of No. 2 is valid and the break instruction signal or the trace instruction signal is output, the instruction code can be monitored accurately with a small number of parts. Therefore, the above problem can be solved.

(Embodiment) FIG. 4 shows an embodiment of FIG. 1 of the present invention and is a circuit diagram of a break circuit having a maximum machine code number of 3 bytes and a code bit length of 8 bits.

In this break circuit, the instruction code acquisition unit 10 is a latch circuit 11, the instruction code analysis unit 20 is a writable / readable memory (hereinafter referred to as RAM) 21, and the page update circuit unit 30 is a 2-input AND gate 31 and a binary. -It is composed of the up counter 32. Furthermore, the byte number comparison unit 40 includes a binary up counter 41 and a logic circuit 42, and the logic circuit 42 has a 2-input EOR gate (exclusive OR gate) 43, 44, a 2-input NOR gate 45, and a 2-input AND gate.
It consists of a gate 46.

The latch circuit 11 which constitutes the instruction code fetching section 10 is a circuit which latches the execution instruction code CD by the fetch control signal LC and outputs it from the output terminal Q to the RAM 21. In addition,
The output control terminal OE of the latch circuit 11 is grounded. RA
In response to the read / write control signal R / W, M21 reads the latch circuit output as a lower address from the input terminal ADR _L , and the binary up counter output in the page update circuit section 30 as an upper address from the input terminal ADR _H. It has a function of outputting the first and second read data read or read from the output terminals D0 and D1 to the AND gate 31 in the page update circuit unit 30 and the AND gate 46 in the logic circuit 42, respectively. There is. The output terminal D0 for outputting the first read data of the RAM 21 and the count signal CK which is the count-up timing control signal are used in the AND gate 3 in the page update circuit unit 30.
It is connected to the clock terminal of the binary up counter 30 via 1, the output terminals QA and QB of the binary up counter 32 are connected to the input terminal ADR _{H of the} RAM21, and it is logically compared with the machine code number. EOR 43,44 in circuit 42
It is connected to the.

In the byte count comparison unit 40, a binary up counter
The clock terminal of 41 is connected to the count signal CK, and its output terminals QA and QB are connected to the EORs 43 and 44 in the logic circuit 42. The outputs of the EORs 43 and 44 are connected to one input side of the AND gate 46 via the NOR gate 45, and the other input side is
The RAM 21 is connected to the output terminal D1 for outputting the second read data, and the AND gate 46 outputs the block signal BK or the trace signal TC to supply it to a break generation circuit (not shown).

The RAM21 can read / write data according to the input from the console, etc., and the binary up counters 32 and 41 are initialized to the "L" level by the clear signal CL immediately after the execution of one instruction. The structure is such that

Next, the operation will be described.

Before starting the evaluation (execution) of the program, write the combination of instruction codes that you want to break during execution to RAM21. For example, when the branch to the address 2OO _H ~2FF _H a branch instruction JUMP, illustrating the case of a break. Here, the instruction code is O4 _H , nn, O2 _H (however, nn = O to FF _H ).
And

First of all, writing the data "1" to the address O4 _H of RAM21, then writes all "1" to the address 100 _H ~1FF _H (1 page of the area of the storage area in the RAM). Further address 2O2 _H
Write data “3” or “2” to Data "0" is written in the other addresses. Then, the clear signal CL is used to output the outputs of the counters 32 and 41 to the logic "0".
Set to ".

After finishing the above settings, the evaluation of the program is started. Here, as the execution instruction code CD O4 _H, 22 _H, O2
_The case where _H is executed will be described.

Counter 32, when executing the instruction code O4 _H, as the output terminal D0 is "H" level of the RAM 21, is counted up in synchronization with the count signal CK, the output QA becomes "H" level. Thus, RAM 21 is the address 100 _H ~1FF _H (1
Page) will be selected. Also counter
41 is counted up by the count signal CK. And since all the 100 _H ~1FF _H of RAM21 data "1" is written, regardless of the execution instruction code CD, the counter 32 in synchronization with the count signal CK is counted up, the output terminal QA, QB respectively "L" level, becomes "H" level, the RAM21 address 200 _H ~2FF _H is select (select). The other counter 41 is also counted up, and its output terminals QA and QB become the same as the output of one counter 32.

When the latch circuit 11 latches the instruction code O2 _H, the contents of the address 2O2 _H of RAM21 is read, the output terminal D of the RAM21
1 becomes "H" level. At this time, since the outputs of both counters 32 and 41 match, the output of the output terminal D1 of the RAM 21 becomes valid by the AND gate 46, and the break signal BK or trace signal TC output from the AND gate 46 becomes " H
It becomes "level and is supplied to a break generation circuit (not shown).

Next, the specified code is 21 _H, an OO _H, illustrating the operation when an instruction code executed was _{14 H, 21 H, OO H} .

First, before starting the evaluation of the program,
The data "1" to the address 21 _H of the RAM 21, writing data "0" data "3" or "2" to the address 100 _H write, to another address. Then, the clear signal CL sets the outputs of the counters 32 and 41 to the "L" level, and then the evaluation of the program is started.

When the latch circuit 11 latches the instruction code 14 _H , the content of the address 14 _H of the RAM 21 is read by the latch output. Since this read data is "0", one counter 32 is not counted up, only the other counter 41 is counted up in synchronization with the count signal CK, and its output terminal QA becomes "H" level.

When the instruction code 21 _H is latched by the latch circuit 11, by the latch output, is read the contents of the address 21 _H of the RAM 21, the output terminal D0 is "H" level. Then AN
The D gate 31 opens and the counter 3 synchronizes with the count signal CK.
2, 41 are counted up, the output terminal QA of one counter 32 becomes “H” level, the output terminal QA of the other counter 41 becomes “L” level, and the output terminal QB of counter 41 becomes “H” level.
"It becomes a level.

Then, the instruction code OO _H is latched by the latch circuit 11, and R
The contents of the address 100 _H of AM21 output terminal D1 is read becomes "H" level. However, since the output values of the counters 32 and 41 are different, the AND gate 46 is closed via the EOR gates 43 and 44 and the NOR gate 45, and the output of the AND gate 46 is "L".
“It remains at the level.

The present embodiment has the following advantages.

(A) The instruction code analysis unit 20 is composed of a RAM 21, and the RAM 21
Enter the execution instruction code CD as the lower address of RAM2
By providing a counter 32 whose count operation is controlled by the read data of 1 and using the output of the counter 32 as a higher address of the RAM 21, the same byte from the first byte (word) of the execution instruction code CD to the last byte (word) (Word) Analyze instruction code up to eye.

(B) Counter 41 that counts the number of executed instruction codes
Is provided and the output value of the RAM 32 is compared with the output value of the counter 32, and the output data of the RAM 21 is validated when both counter values match. Therefore, 1 byte (word) can be obtained with a small number of parts.
It is possible to monitor all execution instruction codes CD, from instructions to multi-byte (word) instructions. In addition, in the case of a multi-byte (word) instruction, a plurality of partial instruction codes can be designated, thereby improving the debugging efficiency. For example, as a break condition or trace condition, MOV, 20 _H, the internal RAM nn _H (Evaluation Chip n
store the contents of n _H at address 20 _H ) to monitor the status of address 20 _H of the internal RAM of the evaluation chip,
Only the PUSH / POP (register save / restore) instructions can be traced to check the usage status of the stack area.

The present invention is not limited to the illustrated embodiment, and for example, the instruction code fetching unit 10 may be configured by a register or the like, the instruction code analysis unit 20 may be configured by a memory other than RAM, or the binary up counters 32, 41. Can be replaced by a down counter or the like, or the logic circuit 42 can be configured by another gate circuit or the like, and various modifications can be made.

(Effects of the Invention) As described in detail above, according to the present invention, the execution instruction code is input to the instruction code analysis unit as a lower address, and the output of the instruction code analysis unit causes the page update circuit unit to output the same. While changing the upper address to the instruction code analysis unit to analyze the executed instruction code, the output of the instruction code analysis unit and the number of executed instruction codes are compared by the byte number comparison unit 40, and both are compared. Since the output of the instruction code analysis unit is enabled when they match, it is possible to simultaneously specify an instruction consisting of a plurality of instruction codes as a plurality of traces or break conditions with a small number of parts, and improve the efficiency of debugging and the like.

[Brief description of drawings]

FIG. 1 is a block diagram of the break circuit of the present invention, FIGS. 2 and 3 are block diagrams of a conventional break circuit, and FIG. 4 is a circuit diagram of the break circuit showing the embodiment of FIG. 10 …… Instruction code capture part, 11 …… Latch circuit, 20 ……
Instruction code analysis unit, 21 ... RAM, 30 ... Page update circuit unit, 32,41 ... Binary up counter, 40 ... Byte number comparison unit, 42 ... Logic circuit.

Claims (1)

[Scope of utility model registration request] 1. An instruction code analysis unit having a writable / readable memory for outputting first and second read data, and having an execution instruction code as a lower address input to the memory, and an output from the memory. A page updating circuit section having a first counting means whose counting operation is controlled by the first read data, the output of the first counting means being the upper address of the memory, and the number of machine codes per instruction Second read data which is output from the memory when the output of the second count means and the output of the first count means are compared and the two coincide with each other. And a byte number comparison unit for outputting a break instruction signal or a trace instruction signal, and analyzing the execution instruction code to output the break instruction signal or the trace instruction signal. Break circuit according to claim.