JPH07170228A - Received signal quality detection circuit - Google Patents

Abstract

PURPOSE:To detect the quality of a signal with a simple circuit by showing the received signal quality with the count value of an integral counter. CONSTITUTION:This circuit is composed of an integral counter 12 and a timing synchronizing circuit 13. The integral counter 12 samples an output from a direct conversion IC 11 just by a number N (N is a natural number) of times decided for each symbol length. When the signal at that time is 'Hi', it is counted but when it is 'Lo', nothing is counted. Corresponding to a number H of counted 'Hi', a distance ¦H-(N/2)¦ from a threshold value N/2 can be provided, the quality of the output from the direct conversion IC 11 can be detected, and either 'Hi' or 'Lo' can be decided corresponding to the polarity of [H-(N/2)]. The timing synchronizing circuit 13 outputs a reset signal so that the integration circuit 12 can perform its operation for each symbol. Then, the quality of the signal can be led out of the number counted by the integral counter 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a received signal quality detection circuit applied to a direct conversion detection circuit used in a pager or the like.

[0002]

2. Description of the Related Art Generally, it is necessary to measure a reception level and a noise level in order to detect the quality of a signal.
For example, in a transmission system such as a pager system using the FSK modulation method, direct conversion I
C may be used.

[0003]

In such a case, I
Since the output of C is a binary signal, it is difficult to measure the reception level and the noise level. In addition, installing a circuit that detects the reception level and noise level in addition to the direct conversion detection circuit causes an increase in circuit scale,
The cost will also increase.

An object of the present invention is to solve the problem of the prior art that the signal quality is difficult to detect from the output of the direct conversion detection circuit and the circuit becomes complicated, and the signal quality is detected with a simple circuit. It is an object of the present invention to provide a detection circuit of a received signal quality capable of performing.

[0005]

In order to achieve this object, the received signal quality detection circuit according to the present invention determines the "H" level state of the output of the direct conversion IC used in the reception detection circuit as one symbol. An integration counter that counts at a sampling rate of N (N is a natural number) times and a timing synchronization circuit that reads and resets the output of the integration counter for each symbol are provided, and the count value of the integration counter indicates the received signal quality. It is configured as shown.

[0006]

Principle of the invention Generally, the FSK detection by the direct conversion system is based on the principle of binary determination of the rotation direction of the carrier vector of the received FSK modulated signal.
It is not possible to extract analog detection information like the frequency discrimination circuit from the detection output. However, when the reception level is lowered due to the occurrence of fading or random FM noise is generated, a glitch of the opposite polarity to the received signal due to the instantaneous reverse rotation operation of the carrier vector due to the noise component is generated in the output. Appears as 2. The present invention focuses on this phenomenon and is based on the principle of detecting the received signal quality by quantifying the frequency of glitch occurrence.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention, as shown in FIG.
And timing synchronization circuit 13. The integration counter 12 samples the output from the direct conversion IC 11 by a predetermined number N (N is a natural number) for each symbol length (FIG. 3). If the signal at that time is "Hi", it is counted, and if it is "Lo", it is not counted. The number H of “Hi” s counted gives the distance | H− (N / 2) | from the threshold value N / 2, the quality of the output of the direct conversion IC 11 can be detected, and (H− (N It is possible to determine "Hi" or "Lo" by the polarity of / 2)).
The timing synchronization circuit 13 outputs a reset signal so that the integration counter 12 performs its operation for each symbol. For example, consider the case where the number N of times of sampling by the integration counter 12 is 100. At this time, if the number H of counting “Hi” is 51 to 100, “Hi” is set to 1 to
If it is 50, "Lo" is determined, but at the same time, the signal quality can be derived from this number. That is,
When H is near 100 or 0, | H- (N / 2) | is 5
It is close to 0, indicating good quality. On the other hand, when H is around 50, | H− (N / 2) | becomes a value close to 0, which means that the quality is inferior.

[0008]

As described in detail above, according to the present invention, the quality of the received signal can be detected from the output of the direct conversion IC with a simple circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of the present invention.

FIG. 2 is a time chart showing the output of the direct conversion IC when the reception level is low.

FIG. 3 is a diagram showing an example of sampling the output of a direct conversion IC.

[Explanation of symbols]

 11 Direct conversion IC 12 Accumulation counter 13 Timing synchronization circuit

Claims (1)

[Claims] 1. An integration counter for counting the "H" level state of the output of a direct conversion IC used in a reception detection circuit at a sampling rate of N (N is a natural number) times per symbol, and an output of the integration counter. And a timing synchronization circuit for reading and resetting the symbol for each symbol, and a reception signal quality detection circuit configured such that the count value of the integration counter indicates the reception signal quality.