JPH07181925A - Display drive - Google Patents

Abstract

(57) [Abstract] [Purpose] One gradation power supply is used to display all gradations, and the circuit scale is also reduced. [Structure] Conventionally, a gradation power source that requires only the number of gradations,
It becomes possible to replace it with a gradation signal supply unit that supplies a periodic signal. Since this gradation signal supply unit is a digital circuit, it is integrated as a control circuit and gradation signal supply circuit 1 in the same integrated circuit as the control circuit. Is possible and the drive circuit is revolutionarily simplified. Further, conventionally, the gradation power source is
As the output of the driver, the charge and discharge current of the data line of the display body is supplied through the analog switch, and each requires a considerable current capacity, but instead of the conventional analog switch group, the logic part and the output part are driven. Installed in 3,
Select the periodic signal according to the image data in the logic section,
Since the required current capacity is secured in the output circuit, the analog switch, which conventionally required a considerable current capacity, was required for the number of gradations, but only one output circuit is required.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display drive device used in a drive circuit of an active matrix type liquid crystal display device for displaying gray scales.

[0002]

22 is a circuit diagram showing a configuration of a portion corresponding to one output in a conventional digital driver. In FIG. 22, sampling data storage means M _smpi into which 3-bit display data D _{0 to} D ₂ and sampling pulse Tsmp _i (where i is a signal or circuit corresponding to the i-th data line) are input. Each output Q of each is connected to the data input D of the output holding storage means MH _i . The output pulse OE is input to the input CK of the output holding storage means MH _i . Further, each output Q of the output holding storage means MH _i is connected to each input terminal of the output selection circuit DEC _i which is a decoder circuit, and each output terminal is connected to each of the analog switches ASW _{0 to} ASW _0.
Each is connected to SW ₇ . Further, the eight gradation voltage sources (V _{0 to} V ₇ ) are respectively analog switches AS.
W ₀ ~ASW ₇ to be connected, the output of the analog switches ASW ₀ ~ASW ₇ is connected to the output terminal OUT _i.

The circuit of this digital driver is a circuit for realizing eight gradation display corresponding to 3-bit display data, and an actual driver is composed of a large number of circuits shown in FIG. ing. By using these plural drivers, there are as many circuits as shown in FIG. 22 corresponding to the number of data lines of the display body (here, there are M lines).

FIG. 23 is a timing waveform chart in each main part of the digital driver of FIG. In FIG. 23, one horizontal line of the display body, that is, the image data Data corresponding to one cycle of the vertical synchronizing signal _Hsyn is once taken into the sampling data storage means M _smpi by the sampling pulse Tsmp _i given at an appropriate time, The output holding memory means MH is collectively operated by an output pulse OE given from the control circuit at an appropriate time after all the data corresponding to one horizontal line picture element is sampled.
moved to _i . Further, the output selection circuit DEC _i corresponds to the output values (input signals d _{0 to} d ₂ ) of the data held in the output holding storage means MH _i , and has eight floors input from outside the driver. The data lines are driven by outputting the output signals S _{0 to} S ₇ so as to select and output any one of the adjustment voltage sources (V _{0 to} V ₇ ). For example, if the data value is S
_In the case of ₃ , the analog switch ASW ₃ is in the “ON” state, and the gradation voltage source V ₃ is output from the output terminal OUT _i as the driver output On.

Further, FIG. 24 shows a circuit diagram showing a configuration of one output portion of a 4-bit driver in the case of designing based on the conventional method. In FIG. 24, an output selection circuit DEC which is a decoder circuit is different from the case of the 3-bit driver.
_i is an output signal S ₀ corresponding to 4-bit input signals d _{0 to} d _3.
~ S ₁₅ is to be output. Further, analog switches ASW _{0 to} ASW corresponding to these output signals S _{0 to} S ₁₅ are provided.
₁₅ is provided, and one of the 16 gradation voltage sources (V _{0 to} V ₁₅ ) is selected by the output selection circuit DEC _i and output from the output terminal OUT _i .

[0006]

The above-mentioned conventional digital driver requires the same number of gradation power supplies as the number of gradations. For example, if the data is 4 bits, 16 gradation power supplies are required. By the way, since this gradation power source serves as a source for supplying a charging / discharging current of the data line of the display through an analog switch as an output of the driver, it requires a considerable current capacity. Therefore, it is generally manufactured by combining an operational amplifier and a transistor for current amplification, and the cost occupying the whole driving circuit and the mounting area occupying on the substrate are not small at all. In fact, for example, in a display device using a conventional 3-bit driver, its control circuit board (here, the control circuit board is a circuit portion of the drive circuit excluding the driver and its driving power supply circuit). That is, the main components are the interface circuit between the control signal generation circuit of the driver and the main unit,
6 to 7 of a power supply circuit for gradation and common electrode)
It occupies a relatively large area, and the large scale of this circuit is not only a cost but also a heavy burden on the module design. If a 4-bit display device is developed on the extension of the conventional drive circuit, the area of the control circuit board is inevitably large, and the commerciality of the module is greatly impaired.

The present invention solves the above-mentioned conventional problems, and provides a display driving device capable of displaying all gradations without using a so-called gradation power source and greatly reducing the circuit scale. The purpose is to

[0008]

A display driving device according to the present invention includes a gradation signal supply section for outputting a vibration signal vibrating between binary voltages, and the gradation signal according to a plurality of bits of image data. A selection control unit that outputs a selection control signal that selectively controls a vibration signal from the supply unit, and a logic unit that outputs a vibration signal corresponding to the selection control signal among the plurality of vibration signals from the gradation signal supply unit. , And an output unit for converting the level of the vibration signal output from the logic unit and outputting the level-converted signal, whereby the above object is achieved.

Further, preferably, the vibration signal output from the gradation signal supply unit in the display driving apparatus of the present invention is a plurality of periodic signals (m (k)) having a duty ratio of m (k): n (k). ，
n (k) is zero and a positive integer, and k is a zero and a positive integer equal to or less than the number of gradations, whereby the above object is achieved.

Further, preferably, in the display driving device of the present invention, the output section has a buffer structure, and thus the above object is achieved.

Further, preferably, the driving power source of the output section in the display driving apparatus of the present invention is common to at least one of the gradation signal supply section, the selection control section and the logic section, thereby achieving the above object. To be done.

Further, preferably, only one of the high level side and the low level side of the driving power source of the output section in the display driving apparatus of the present invention is common to at least one of the gradation signal supply section, the selection control section and the logic section. There, the above object is achieved thereby.

Further, preferably, the driving power source of the output section in the display driving apparatus of the present invention is independently supplied from the gradation signal supply section, the selection control section and the logic section, whereby the above object is achieved. To be done.

Further, in the display driving device of the present invention, a plurality of periodic signals (m (k), n (k) having a duty ratio of m (k): n (k) in the ON period and the OFF period are zero and positive. , K is zero or a positive integer equal to or less than the number of gradations), and the duty ratio of the periodic signal is synchronized with at least one of the one output period, the horizontal output period, and the vertical output period of the image signal. m
(k): In synchronization with the gradation signal supply unit that reverses n (k) and the duty ratio inversion of the periodic signal from the gradation signal supply unit,
A common electrode driving section that alternately outputs a voltage between predetermined potentials, and is synchronized with at least one of one output period, a horizontal output period, and a vertical output period of the image signal from the gradation signal supply unit. Of the gradation signal and the average value of the cyclic signal of the gray scale voltage obtained from the output from the common electrode driving section are sequentially inverted and driven, and the above object is achieved thereby.

Further, in the display driving device of the present invention, a plurality of periodic signals (m (k), n (k) having a duty ratio of m (k): n (k) between the ON period and the OFF period are zero and positive. , K is zero or a positive integer equal to or less than the number of gradations, and is synchronized with at least one of an image signal output period, a horizontal output period, and a vertical output period, and the high level of the periodic signal is output. And a common electrode drive unit that alternately outputs a voltage between predetermined potentials in synchronization with the inversion of the periodic signal from the gradation signal supply unit. A grayscale voltage obtained from the periodic signal from the grayscale signal supply unit and the output from the common electrode drive unit in synchronization with at least one of an image signal output period, a horizontal output period, and a vertical output period. The average value of the periodic signal of The above-mentioned object can be achieved by the.

Further, in the display driving device of the present invention,
The magnitude relationship between the average values of the periodic signals from the gradation signal supply unit is
It has the same magnitude relation as the magnitude relation of the value k of the image data corresponding to the periodic signal, or has the opposite magnitude relation, whereby the above object is achieved.

Further preferably, in the display driving device of the present invention, the average value of the gradation voltage obtained from the vibration voltage and the periodic signal from the gradation signal supply unit is the gradation voltage of the display object to be driven. It is determined so as to follow the γ characteristic of the luminance characteristic, and thereby the above-mentioned object is achieved.

Further, in the display driving device of the present invention, the duty ratios of the plurality of periodic signals of the grayscale signal supply section are made different from each other, so that the magnitude relationship of the average values of the grayscale voltages obtained from the periodic signals is made larger. To decide,
Thereby, the above object is achieved.

Further, preferably, in the display driving apparatus of the present invention, one or both of the signals corresponding to the maximum value or the minimum value of the data value k in the vibration signal or the periodic signal from the gradation signal supply section. , High level or low level constant voltage, whereby the above object is achieved.

Further, in the time period in which the gradation signal supply unit in the display driving apparatus of the present invention outputs so that the magnitude relation of the average value of the gray scale signals is the magnitude relation opposite to the magnitude relation of the data value k. , The common electrode drive section outputs the potential on the low level side, and the grayscale signal supply section outputs so that the magnitude relationship of the average value of the grayscale signals is the same magnitude relationship as the magnitude relationship of the data value k. In the time limit, the common electrode drive section outputs the high-level potential, and thus the above-mentioned object is achieved.

Further, in the time period in which the gradation signal supply section in the display driving device of the present invention outputs so that the magnitude relationship of the average value of the gray scale signals becomes the same magnitude relationship as the magnitude relationship of the data value k. , The common electrode drive section outputs the potential on the low level side, and the grayscale signal supply section outputs the grayscale signal so that the magnitude relationship of the average values of the grayscale signals is the magnitude relationship opposite to the magnitude relationship of the data value k. In the time limit, the common electrode drive section outputs the high-level potential, and thus the above-mentioned object is achieved.

Further, preferably, in the display driving device of the present invention, a part of a plurality of necessary periodic signals is supplied from the gradation signal supply unit, and one of the periodic signals supplied from the gradation signal supply unit is supplied. The inversion signal of the part is used to form a periodic signal other than a part of the periodic signal, whereby the above object is achieved.

Further, preferably, in the display driving apparatus of the present invention, the period signal supplied from the gradation signal supply unit is synchronized with the inversion time period of the signal for inverting the high level and the low level for each output period. It has a control pulse generating section for obtaining a control signal by means of which the above-mentioned object is achieved.

[0024]

With the above structure, the grayscale power supply, which conventionally requires only the number of grayscales, can be replaced with the grayscale signal supply section for supplying the periodic signal. Since the grayscale signal supply section is a digital circuit, It can be integrated in the same integrated circuit as the control circuit, revolutionarily simplifying the drive circuit.
Further, conventionally, the gradation power supply supplies the charging / discharging current of the data line of the display body through the analog switch as the output of the driver, which requires a considerable current capacity, respectively. A logic unit and an output unit are provided to select a periodic signal according to the image data in the logic unit, and the required current capacity is secured in the output circuit. Only one output circuit is required for the number of adjustments. Therefore, one gradation power supply can display all gradations, and the circuit scale can be reduced.

Further, it is obtained from the periodic signal from the gradation signal supply section and the output from the common electrode drive section in synchronization with at least one of the one output period, the horizontal output period and the vertical output period of the image signal. Since the average value of the periodic signal of the gradation drive voltage is sequentially driven to be inverted, the polarity is inverted at least every one of the output period of the image signal, the horizontal output period, and the vertical output period to prevent flicker. The deterioration of the liquid crystal is prevented. Further, when the polarity is inverted every one vertical period, the flicker tends to be larger than when the polarity is inverted every one output period or each horizontal output period, but the power consumption can be reduced. .

Furthermore, since a part of the periodic signal is obtained by using the inverted signal thereof, the periodic signal from the gradation signal supply unit is reduced, and the number of input terminals and signal lines can be reduced, and the circuit system can be reduced. Will be easier. In addition, since the control signal generator has the control pulse generator that obtains the control signal in synchronization with the inversion time period of the signal that inverts the high level and the low level in each output period of the periodic signal supplied from the gradation signal supply unit, It is not necessary to supply control pulses, the number of input terminals and signal lines can be reduced, and the circuit system is simplified.

[0027]

EXAMPLES Examples of the present invention will be described below.

FIG. 1 is a block diagram of a liquid crystal display device showing an embodiment of the present invention. In FIG. 1, a control circuit for generating a control signal and a gradation signal and a gradation signal supply circuit 1 are supplied with voltages Vd and GND from a driving power supply,
Further, image data R, G, B, a clock signal CK, a horizontal synchronizing signal and a vertical synchronizing signal are input from the main unit. The control circuit and the gradation signal supply circuit 1 are respectively connected to a plurality of drivers 3 for applying a gradation drive voltage corresponding to the image data R, G, B to each picture element of the liquid crystal display body 2 for liquid crystal display. The reference gradation signal, the image data R, G, B, the clock signal CK, each control signal, and the like are input from the control circuit and the gradation signal supply circuit 1 to the driver 3. In addition, the driver 3 receives the voltages Vd and GND from the driving power source and the power source voltage V from the output buffer power source 4 to which they are input.
_SH and V _SL are given independently. Further, the common electrode driving means 5 to which the control circuit and the gradation signal supply circuit 1 are connected is connected to the common electrode of the liquid crystal display body 2 and supplies the common voltage Vcom to the common electrode. The above-mentioned control circuit, gradation signal supply circuit 1, driver 3 and common electrode driving means 5 constitute a display driving device 6.

Here, the control circuit and the gradation signal supply circuit 1 output a plurality of gradation signals which are periodic signals having a duty ratio of an on period and an off period. The driver 3 is provided with a logic circuit and an output circuit in place of the conventional analog switch, and the control circuit and the gradation signal supply circuit 1 are provided.
Any of the plurality of periodic signals from the above is selected according to the image data. Further, the power supply voltages V _SH and V _SL of the output circuit of the driver 3 are given independently of the drive power supplies Vd and GND of the driver 3, but under certain conditions, only one or both of them may be applied. You may share it. For example, if the drive power supply GND and the power supply voltage V _SL are made common, the driver 3
Only the power supply voltage V _SH is additionally required for the output circuit of the.

With the above configuration, it has become possible to replace the gradation power supply, which conventionally requires only the number of gradations, with a gradation signal supply circuit for supplying a periodic signal having an oscillating waveform. Since this gradation signal supply circuit is a digital circuit, it is possible to integrate the control circuit and the gradation signal supply circuit 1 in the same integrated circuit as the control circuit, for example, and the drive circuit is revolutionarily simplified. It Further, conventionally, the gradation power supply supplies the charge / discharge current of the data line of the display body through the analog switch as the output of the driver, which requires a considerable current capacity, but instead of the conventional analog switch group. Since a logic circuit and an output circuit are provided and a periodic signal is selected in the logic circuit in accordance with image data and a necessary current capacity is secured in the output circuit, conventionally, the analog switch requires only the number of gradations. Only one output circuit is required,
Therefore, one gradation power source can display all gradations, and the scale of the control circuit can be reduced. As a result, the effects are extremely large, such as cost reduction, reliability improvement, and reduction in the size and weight of the module because the substrate is small.

FIG. 2 is a circuit diagram of a portion corresponding to one output of a 4-bit driver showing an example of the driver 3 of FIG. In FIG. 2, the difference from the prior art of FIG. 24 is that AND circuits AND _{0 to} A instead of the analog switches ASW _{0 to} ASW _15.
ND ₁₅ is present. The outputs S _{0 to} S ₁₅ of the output selection circuit DEC _i , which is a 4-bit decoder (decoder circuit), are one input of the corresponding AND circuits AND _{0 to} AND ₁₅ . From outside the circuit, 16 from T _{0 to} T ₁₅
The periodic signal of the book is input, and the AND circuit A
It is the other input of ND _{0 to} AND ₁₅ . The outputs of the AND circuits AND _{0 to} AND ₁₅ are input to the 16-input OR circuit OR, the output thereof is input to the buffer circuit OB, and the output thereof is the drive output. The power supply of this buffer circuit OB is the AND circuit AND
It is driven by power supplies V _SH and V _SL different from other logic circuits composed of _{0 to} AND ₁₅ and an OR circuit OR.

FIG. 3 is a waveform diagram of each periodic signal input to the 4-bit driver of FIG. In FIG. 3, the periodic signal T
_{1 to} T ₁₅ has a duty ratio of m during the on period and the off period.
(K): A periodic signal of n (k), which is a signal oscillating multiple times during one output period (the pulse interval of the output pulse OE is one output period in the figure). Where m
(K) + n (k) = const. So that m
When (k) and n (k) are determined, m (l)> m (2)
> M (3) ...> m (15), that is, a relationship in which the on period m (1) to the on period m (15) is shortened in order is established. Also, the signals T ₀ and T ₁₆
Is a high level or low level constant signal during one output period.

With the above structure, first, the data is k = 4.
Considering the case of, only the output S4 of the output selection circuit DEC _i becomes a high level, and only the periodic signal T ₄ passes through the logical product circuit AND ₄ and the logical sum circuit OR and the buffer circuit OB to be a gradation signal. Is output. Therefore,
Since the power supply voltages V _SH and V _SL are _supplied as the power supply of the buffer circuit OB, the waveform of the gradation signal is the same as that of the periodic signal T ₄ as shown in FIG. 4, and the power supply voltages V _SH and V _{SL are the same.} The voltage oscillates between the two values.

Similarly, one of the periodic signals T _{0 to} T ₁₅ corresponding to the data value k is selected by the AND circuit by the output signal from the output selection circuit DEC _i , and the drive output is obtained. Is determined. That is, the value of k is 0
When the value is 16, it becomes a constant voltage of the voltage V _SH , V _SL , respectively, and when the value of k is 1 to 15, the voltage VSH, VS respectively.
The voltage between L is oscillated by the periodic signal having the waveform of T1 to T15.

Next, 2 of such voltages VSH and VSL are used.
What voltage is applied to the picture element of the display when the voltage oscillating between the values is output will be described.

FIG. 5 shows a periodic function having a period of 2π. It is well known that such a periodic function is represented by the Fourier series given by the following equation if it is finite and integrable (for example, Sadaharu Takagi, Introduction to Analysis, Chapter 6).

[0037]

[Equation 1]

The first term on the right side of this equation represents the average value of one period of the periodic function, and when FIG. 5 shows the voltage waveform, it corresponds to the DC component of that voltage.

By the way, since it is clear that the actual voltage waveform is finite and can be integrated, all the voltages that change periodically are expressed by the above Fourier series.
That is, the periodic voltage is the DC component (average voltage of one period)
And the fundamental period voltage and its harmonics are added infinitely. Therefore, when the output of the driver outputs a periodic voltage, if the periodic component is sufficiently suppressed by some means, the pixel is given an average value which is its DC component.

By the way, various capacitance components and resistance components exist in the path from the output of the driver of the display body, especially the active liquid crystal display body to the picture element, and when viewed as the load of the driver, It has a characteristic as a low-frequency pass filter, and it is possible to sufficiently suppress the periodic component by appropriately setting the period, and the average value as a DC voltage is applied to the picture element.

By the way, as shown in FIG.
Between two values of H and VSL, for example, when k = 4, the average value A of the voltage of the periodic signal T ₄ oscillating with the duty ratio m (4): n (4) between the on period and the off period is

[0042]

[Equation 2]

It is clear that it is represented by
By appropriately setting the values of the on period m (4) and the off period n (4), it becomes possible to apply an arbitrary voltage between the two values of the voltages VSH and VSL to the picture element.

Similarly, by setting the duty ratios of the waveforms of the periodic voltages T _{1 to} T ₁₅ in FIG. 3 in advance,
A driver capable of applying an appropriate voltage to a pixel corresponding to a 4-bit data value k of 0 to 15, that is, 4-bit 1
A 6-gradation driver can be realized. Below, for simplicity,
Unless otherwise specified, the case of a 3-bit driver will be described. In FIG. 2, the case of the 4-bit driver as the driver 3 of FIG. 1 has been described, but as another example, the case of the 3-bit driver is shown in FIG. FIG. 7 is a waveform diagram of the periodic signals T _{0 to} T ₇ input to the 3-bit driver of FIG. As shown in FIGS. 6 and 7, the gradation signal supply circuit 21 includes
2 is a circuit that supplies a plurality of periodic signals T _{1 to} T ₇ that are vibration signals to the buffer circuit OB from the periodic signals T _{1 to} T _7.
It is assumed that the average value of the gradation signal obtained via the above-mentioned gradation value becomes smaller as the value k of the data corresponding to the gradation signal increases, that is, as the value k increases. Further, in the gradation signal supply circuit 21, all the periodic signals T ₀ corresponding to the maximum value of the average values of the gradation signals are at the high level.

In this embodiment, the average value of the grayscale signals has the opposite magnitude relation to the magnitude relation of the value k of the data corresponding to the grayscale signal, but the same magnitude relation, that is, The average value of the gradation signals may increase as the value k increases. In addition, in this embodiment,
All the periodic signals corresponding to the maximum value in the average value of the gradation signals are set to the high level, but one or both of the periodic signals corresponding to the maximum or minimum average value of the gradation signals are
The high level or the low level may be constant.

FIG. 8 is a circuit diagram showing an example of the gradation signal supply circuit 21 of FIG. 6, and shows only when the data is K = 2,5. In FIG. 8, the vibration signal generation circuit 3
The vibration signal T ₂ ′ of 1 is connected to one terminal of the exclusive OR circuit 32, and the vibration signal T ₅ ′ is connected to one terminal of the exclusive OR circuit 33. Flip flop 3
An output pulse OE, an inverted signal of the horizontal synchronizing signal Hsyn, or a signal synchronized with these is input to the clock terminal CK of No. 4. This output pulse OE is a signal given to the driver from the control circuit and is a signal inputted to the output holding storage means MH _i of FIG. The output inverting terminal Q bar of the flip-flop 34 is connected to the data input terminal D, and the output terminal Q is connected to the other terminals of the exclusive OR circuits 32 and 33. This exclusive OR circuit 32
The periodic signal T ₂ is output from the output terminal of the above, and the periodic signal T ₅ is output from the output terminal of the exclusive OR circuit 33. The grayscale signal supply circuit 35 is configured as described above, and the magnitude relationship of the average value between the grayscale signals is inverted in synchronization with one horizontal period or the like.

With the above configuration, since the output inverting terminal Q of the flip-flop 34 is connected to the data input terminal D, the output inverting terminal Q from the output terminal Q is input to the clock input terminal CK, for example, in synchronization with the output pulse OE. The output is inverted. In the exclusive OR circuits 32 and 33,
The outputs from the output terminals Q of the flip-flops 34 are input, and the vibration signals T ₂ ′ and T ₅ ′ are input. Therefore, as shown in FIG. 9, the periodic signals T ₂ and T output from the exclusive OR circuits 12 and 13 are generated.
₅ is a signal in which the vibration signals T ₂ 'and T ₅ ' are inverted in synchronization with the output pulse OE. That is, the magnitude relation of the average values of the gradation signals obtained from the periodic signals T ₂ and T ₅ is inverted in synchronization with the output pulse OE.

The gradation signal supply circuit 21 of FIG. 6 reverses this magnitude relationship in this embodiment, but this magnitude relationship may not be reversed and may remain the same.

FIG. 10 is a circuit diagram showing another example of the gradation signal supply circuit 21 of FIG. 6, and shows only when the data is K = 2,5. In FIG. 10, the vibration signal T ₂ ′ of the vibration signal generation circuit 41 is connected to one terminal of the exclusive OR circuit 42, and the vibration signal T ₅ ′ is connected to one terminal of the exclusive OR circuit 43. There is. The horizontal synchronization signal Hsy is applied to the clock terminal CK of the flip-flop 44.
The inverted signal of n is input. This horizontal synchronization signal Hsyn
The inverted signal of is a signal given to the driver from the control circuit. The output inverting terminal Q bar of the flip-flop 44 is connected to the data input terminal D and is also connected to one input terminal of the exclusive OR circuit 45. Further, the vertical synchronization signal Vsyn is input to the clock terminal CK of the flip-flop 46. This vertical synchronization signal Vsyn is
This is a signal given to the driver from the control circuit. The output inverting terminal Q bar of the flip-flop 46 is a data input terminal D
And the other input terminal of the exclusive OR circuit 45. The output terminal of the exclusive OR circuit 45 is connected to the other terminals of the exclusive OR circuits 42 and 43, respectively. The periodic signal T ₂ is output from the output terminal of the exclusive OR circuit 42, and the exclusive OR circuit 4
The periodic signal T ₅ is output from the output terminal of 3. The gradation signal supply circuit 47 is configured as described above, and one horizontal period and one horizontal period
In this structure, the magnitude relationship of the average values between the grayscale signals is reversed in synchronization with the vertical period.

FIG. 11 is a waveform diagram in each main part of the grayscale signal supply circuit 47 of FIG. 10 in the horizontal period at the same position in the adjacent vertical periods, and the magnitude relationship of the average values is reversed every horizontal period. Along with this, it is a diagram for explaining the operation in the case where the magnitude relationship of the horizontal periods corresponding to every one vertical period is reversed. As shown in FIG. 11, in the periodic signals T ₂ and T ₅ output from the exclusive OR circuits 42 and 43, the vibration signals T ₂ ′ and T ₅ ′ are inverted in synchronization with the horizontal synchronizing signal and the vertical synchronizing signal. It has become a signal. That is, the periodic signals T ₂ and T _{5 in} the horizontal period at the same position in the vertical periods adjacent to each other.
Are in the inverted state in each vertical period, and the average value of the grayscale signals in the corresponding horizontal period, that is, the average value of the grayscale signals obtained from the periodic signals T ₂ and T _{5 is} provided for each vertical period. The size relationship of is also reversed.

Here, one output period is between the output pulses OE. Further, in the present embodiment, the case where one output period is synchronized with the horizontal synchronization signal Hsyn in a one-to-one relationship has been described. In an actual application, for example, there may be two or more output periods in one horizontal period,
Here, the case of one-to-one correspondence will be described below as an example.

FIG. 12 is a waveform diagram for explaining a display driving operation which is realized by combining the gradation signal from the driver 3 and the common electrode driving signal from the common electrode driving means 5 in FIG. In FIG. 12, a grayscale signal O output from the driver 22 of FIG. 6 and applied to each picture element of the liquid crystal display 2 is displayed.
(I) shows a binary voltage V _SH , which has the same duty ratio as the periodic signal T ₂ shown in FIGS. 9 and 11 when the data value k is 2.
A vibration signal vibrating between V _SL , and the signal AO (i) is
The average value is shown. The common electrode signal Vcom is shown in FIG.
Output from the common electrode driving means 5 of the liquid crystal display 2
Is a potential of the common electrode in and is a signal which is inverted in synchronization with the output pulse OE. Further, the signal G (j) is j
It is the output of the second scan line (gate line or horizontal line) driver. Here, the amplitude does not correspond to the magnitude of the actual voltage, and in reality G (j) is a signal whose amplitude is generally 20 V or more, and the potential difference between the power supply voltages VSH and VSL is less than 5 V as described later. I often decide.

When the signal G (j) is at a high level, the TFT on the j-th scanning line is turned on and the picture element of the liquid crystal display 2 is charged by the voltage of the data line at that time, but as described above, When an oscillating voltage such as the gradation signal O (i) is applied to the input terminal of the data line, the picture element is charged with the average voltage shown by the signal AO (i). In the j-th time period of FIG. 12, the picture element on the j-th scanning line has a positive voltage Vp + as viewed from the common electrode, and in the j + 1-th time period, the picture element on the j + 1-th scanning line has a negative voltage Vp +.
− Therefore, it is possible to drive the liquid crystal display in which the positive and negative polarities are inverted for each scanning line. This is in the next vertical time period, i.e. in the next frame (or field)
This means that the driver is controlled so that the j-th waveform and the j + 1-th waveform in FIG. 12 are reversed, and the picture element on the j-th scanning line is at the positive voltage Vp + or the j + 1-th scanning line. The picture elements on the line will be charged to a negative voltage Vp-.

As a result, the polarity is inverted for each scanning line, and at the same time, each picture element has one frame (or one field).
The polarity is inverted every time to prevent flickering and deterioration of the liquid crystal. It is used for a display body (normally white mode liquid crystal display body) drive circuit manufactured so that the voltage applied to the picture element becomes higher as the data value becomes smaller.

FIG. 13 is a waveform diagram in each main part of the grayscale signal supply circuit 47 of FIG. 10 in the horizontal period at the same position in adjacent vertical periods. The grayscale signal and the common electrode drive signal are vertically synchronized. The case where the signal is inverted in synchronization with the signal is shown. In FIG. 13, the polarities of the picture elements are the same for each scanning line, and the effect of field inversion in which the polarities are inverted every one vertical period can be obtained. In this case, the flicker tends to be larger than in the case where the polarity inversion is performed for each scanning line, but the power consumption can be reduced.

FIG. 14 is a circuit diagram showing an example of a specific configuration in which the gradation signal supply circuit 47 of FIG. 10 and the common electrode driving means 5 of FIG. 1 are combined. In FIG. 14, the POL signal obtained from the output of the exclusive OR circuit 45 via the buffer 47A is input to the-input terminal of the operational amplifier 48, and the reference voltage is input to its + input terminal. The output of the operational amplifier 48 is connected to the input section of a complementary circuit 49 composed of transistors Q1 and Q2. As shown in FIG. 15, the common electrode signal Vcom of the voltage V _High or the voltage V _Low is alternately output from the output terminal of the complementary circuit 49 in accordance with the POL signal synchronized with the vertical synchronizing signal Vsyn and the horizontal synchronizing signal Hsyn. Is output. FIG. 16 is a circuit diagram showing another example of a specific configuration in which the gradation signal supply circuit 47 of FIG. 10 and the common electrode driving means 5 of FIG. 1 are combined. In FIG. 16, the output of the exclusive OR circuit 45 becomes a non-inverted signal and an inverted signal by passing through the buffer 50 and the inverter 51. Complementary circuit 52 composed of field effect transistors (FETs) of the same type
Of the common electrode signal Vco of the voltage V _High or the voltage V _Low according to the output of the exclusive OR circuit 45.
m is output alternately.

FIG. 17 is a waveform diagram showing each periodic signal input to the 4-bit driver, and FIG. 18 is a waveform diagram showing each periodic signal input to the 3-bit driver. In FIG. 17 and FIG. 18, what is indicated by a broken line is the γ characteristic of the gray scale voltage / luminance characteristic of the display body to be driven, and the horizontal axis represents the gray scale voltage and the vertical axis represents the luminance. There is. Periodic signal T
By changing the duty ratios of _{0 to} T ₁₅ , the average values of the gradation voltages obtained from the periodic signals T _{0 to} T ₁₅ are determined so as to follow the γ characteristic.

FIG. 19 is a circuit diagram of a portion corresponding to one output of a 3-bit driver showing still another example of the driver 3 of FIG.
In FIG. 19, among the periodic signals T _{0 to} T ₇ , the periodic signal T
_The duty ratios of ₀ and T ₇ , the periodic signals T ₁ and T ₆ , the periodic signals T ₂ and T ₅ , and the periodic signals T ₃ and T ₄ are inverted. Therefore, the periodic signals T _{4 to} T ₇ are
Through the inverter 53, the periodic signals T _{0 to} T ₃ can be replaced with inverted signals. Thus, a portion of the periodic signal by using their inverted signals, simply by inputting a periodic signal T ₀ through T ₃ from the driver outside, easily periodic signal T ₀ through T ₇ inside driver Obtainable.

FIG. 20 is a circuit diagram of the output pulse OE generator provided in the driver 22 of FIG. In FIG. 20, the periodic signal T ₀ output from the gradation signal supply circuit 21 is input to each input terminal of the exclusive OR circuit 61 via the delay circuit 62 and directly input. An output pulse OE is obtained from the output terminal of the exclusive OR circuit 61. The output pulse OE generating circuit 63 is configured as described above.

FIG. 21 is a timing waveform chart of each main part in the output pulse OE generating circuit 63 of FIG. 20, in which the periodic signal T ₀ for the data value k = 0 is synchronized with one output period and each gradation signal is obtained. It is a figure in the case of satisfy | filling the requirement which reverses the magnitude relationship of the average value between. Originally, the periodic signal T ₀
Since the time limit of change of the output signal is synchronized with the output pulse OE, it is possible to reproduce the output pulse OE from the time limit of change of the periodic signal T ₀ . That is, the output pulse OE is reproduced from the rising and falling times of the periodic signal T ₀ .

By preparing such an output pulse OE generator inside the driver 22, it becomes unnecessary to supply the output pulse OE to the driver 22 again. Therefore, the number of input terminals of the driver 22 and the number of signal lines from the control circuit to the driver 22 can be reduced, and the driving circuit system can be simplified. In fact, as a driving circuit of a liquid crystal display device that is required to be downsized, it is an advantageous condition to reduce the number of signals even by one such circuit.

[0062]

As described above, according to the present invention, since the gradation power supply, which has conventionally required the number of gradations, can be replaced with the gradation signal supply section for supplying the periodic signal, the same as the control circuit. It can be integrated in an integrated circuit to simplify the circuit. Further, a logic unit and an output unit are provided in place of the conventional analog switch group, a periodic signal can be selected in the logic unit according to image data, and a necessary current capacity can be secured in the output circuit. The analog switch, which required the current capacity of, was required for the number of gradations, but only one output circuit was required, and all gradations could be displayed with one gradation power source, and the circuit scale was also reduced. be able to.

Further, it is obtained from the periodic signal from the gradation signal supply section and the output from the common electrode drive section in synchronization with at least one of the one output period, the horizontal output period and the vertical output period of the image signal. Since the average value of the periodic signal of the gradation drive voltage is sequentially driven to be inverted, the polarity is inverted at least every one of the image signal output period, the horizontal output period, and the vertical output period to prevent flicker. It is possible to prevent deterioration of the liquid crystal.
Further, when the polarity is inverted every one vertical period, the flicker tends to be larger than when the polarity is inverted every one output period or each horizontal output period, but the power consumption can be reduced.

Further, since a part of the periodic signals can be obtained by using their inverted signals, the number of periodic signals from the gradation signal supply section can be reduced and the number of input terminals and signal lines can be reduced. Therefore, the circuit system can be simplified. In addition, if a control pulse generator that obtains a control signal in synchronization with an inversion time period of a signal that inverts a high level and a low level in each output period of the periodic signal supplied from the gradation signal supply unit is provided, It is not necessary to supply a control pulse again, the number of input terminals and signal lines can be reduced, and the circuit system can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram of a liquid crystal display device showing an embodiment of the present invention.

FIG. 2 is a circuit diagram of a portion corresponding to one output of a 4-bit driver showing an example of the driver 3 in FIG.

FIG. 3 is a waveform diagram showing each periodic signal input to the 4-bit driver of FIG.

4 is a waveform diagram when k = 4 among the periodic signals input to the 4-bit driver of FIG.

FIG. 5 is a periodic waveform chart showing a periodic function having a period of 2π.

6 is a circuit diagram showing a configuration of a portion corresponding to 1 output of a 3-bit driver in another example of the driver 3 of FIG.

7 is a waveform diagram of a periodic signal input to the 3-bit driver 22 of FIG.

8 is a circuit diagram showing an example of the gradation signal supply circuit 21 of FIG.

9 is a waveform diagram in each main part of the gradation signal supply circuit 35 of FIG.

10 is a circuit diagram showing another example of the gradation signal supply circuit 21 of FIG.

11 is a waveform diagram in each main part of the grayscale signal supply circuit 47 of FIG. 10 in a horizontal period at the same position in adjacent vertical periods, and the magnitude relationship of the average values is reversed every horizontal period, and The case where the magnitude relationship of the horizontal periods corresponding to every one vertical period is reversed is shown.

12 is a waveform diagram for explaining a display driving operation realized by combining a gray scale signal from the driver 3 of FIG. 1 and a common electrode driving signal of a common electrode driving unit 5. FIG.

13 is a waveform diagram in each main part of the grayscale signal supply circuit 47 of FIG. 10 in a horizontal period at the same position in adjacent vertical periods, in which the grayscale signal and the common electrode drive signal are synchronized with the vertical synchronization signal. Then, the case of reversing is shown.

14 is a circuit diagram showing an example of a specific configuration in which the gradation signal supply circuit 47 of FIG. 10 and the common electrode driving means 5 of FIG. 1 are combined.

15 is a waveform diagram in which operation waveforms of the common electrode driving unit of FIG. 14 are added to the waveform diagram of FIG. 11.

16 is a circuit diagram showing another example of a specific configuration in which the gradation signal supply circuit 47 of FIG. 10 and the common electrode driving means 5 of FIG. 1 are combined.

FIG. 17 is a waveform diagram showing each periodic signal input to the 4-bit driver.

FIG. 18 is a waveform diagram showing each periodic signal input to the 3-bit driver.

FIG. 19 is a circuit diagram of a portion corresponding to one output of a 3-bit driver showing still another example of the driver 3 of FIG.

20 is an output pulse O provided in the driver 22 of FIG. 6;
It is a circuit diagram which comprises an E generation part.

21 is a timing waveform chart of each main part in the output pulse OE generation circuit 63 of FIG.

FIG. 22 is a circuit diagram showing a configuration of a portion corresponding to one output in a conventional 3-bit digital driver.

FIG. 23 is a timing waveform chart in each main part of the digital driver in FIG. 22.

FIG. 24 is a circuit diagram showing a configuration of a portion corresponding to one output in a conventional 4-bit digital driver.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 control circuit and gradation signal supply circuit 3 driver 5 common electrode drive means 6 display driver 11,22 driver 21, 35, 47 gradation signal supply circuit 31, 41 vibration signal generation circuit 32, 33, 42, 43 , 45, 61 Exclusive OR circuit 34, 44, 46 Flip-flop 47A, 50 Buffer 48 Operational amplifier 49, 52 Complementary circuit 51, 53 Inverter 62 Delay circuit 63 Output pulse OE generation circuit DEC _i output selection circuit AND _{0 to} AND ₁₅ , AND _{0 to} AND ₇ AND circuit OR OR circuit OB buffer circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Junji Kawanishi 22-22 Nagaike-cho, Abeno-ku, Osaka City, Osaka Prefecture

Claims (16)

[Claims] 1. A gradation signal supply section that outputs a vibration signal that vibrates between binary voltages, and a selection control that selectively controls the vibration signal from the gradation signal supply section according to image data of a plurality of bits. A selection control unit that outputs a signal, a logic unit that outputs a vibration signal according to the selection control signal among a plurality of vibration signals from the gradation signal supply unit, and a level conversion of the vibration signal output from the logic unit And a display driving device provided with an output unit for outputting. 2. The vibration signal output from the gradation signal supply unit comprises a plurality of periodic signals (m (k), n (k) having a duty ratio of m (k): n (k)) of zero and positive. 2. The display driving device according to claim 1, wherein k is an integer of 0 or a positive integer equal to or less than the number of gradations. 3. The display driving device according to claim 1, wherein the output unit has a buffer structure. 4. The display drive device according to claim 1, wherein a drive power supply for the output section is common to at least one of the gradation signal supply section, the selection control section, and the logic section. 5. The display drive according to claim 1, wherein only one of a high level side and a low level side of a driving power supply for the output section is common to at least one of the gradation signal supply section, the selection control section and the logic section. apparatus. 6. The display drive device according to claim 1, wherein the drive power source for the output section is independently supplied to the gradation signal supply section, the selection control section, and the logic section. 7. The duty ratio between the on period and the off period is m.
(k): A plurality of n (k) periodic signals (m (k), n (k) are zero and positive integers, k is zero and positive integers less than the number of gradations) are output, and the A grayscale signal supply unit that reverses the duty ratio m (k): n (k) of the periodic signal in synchronization with at least one of one output period, horizontal output period, and vertical output period; A common electrode drive unit that alternately outputs a voltage between predetermined potentials in synchronization with the duty ratio inversion of the periodic signal from the supply unit, and outputs one output period, a horizontal output period, and a vertical output period of the image signal. A display drive device configured to sequentially invert and drive an average value of a periodic signal of a grayscale voltage obtained from a periodic signal from the grayscale signal supply unit and an output from the common electrode drive unit in synchronization with at least one of them. . 8. The duty ratio between the on period and the off period is m.
(k): A plurality of n (k) periodic signals (m (k), n (k) are zero and positive integers, k is zero and positive integers less than the number of gradations) are output, and the A grayscale signal supply unit that inverts a high level and a low level of the periodic signal in synchronization with at least one of one output period, a horizontal output period, and a vertical output period, and a period from the grayscale signal supply unit. A common electrode driving section that alternately outputs a voltage between predetermined potentials in synchronization with signal inversion, and in synchronization with at least one of one output period, horizontal output period, and vertical output period of the image signal. A display driving device configured to sequentially invert and drive the average value of the periodic signal of the gradation voltage obtained from the periodic signal from the gradation signal supply unit and the output from the common electrode driving unit. 9. The magnitude relation of the average value of the periodic signal from the gradation signal supply unit has the same magnitude relation as the magnitude relation of the value k of the image data corresponding to the periodic signal, or the opposite magnitude relation. 9. The display drive device according to claim 7, which has a relationship. 10. An average value of gray scale voltages obtained from the vibration signal or the periodic signal from the gray scale signal supply unit is adjusted so as to follow the gamma characteristic of the gray scale voltage / luminance characteristic of the display body to be driven. Claim 1 or 2 of the determined configuration,
7. The display drive device according to items 7 and 8. 11. The structure according to claim 2, wherein the duty ratios of the plurality of periodic signals of the gradation signal supply section are made different from each other to determine the magnitude relation of the average values of the gradation voltages obtained from the periodic signals. 7. The display drive device according to items 7 and 8. 12. One or both of a vibration signal or a periodic signal from the gradation signal supply unit, which corresponds to a maximum value or a minimum value of a data value k, is a high level or a low level constant voltage. The display drive device according to claim 1, 7, or 8. 13. The common electrode driving unit in the time period when the grayscale signal supply unit outputs the grayscale signal so that the magnitude relation of the average value of the grayscale signal is the magnitude relation opposite to the magnitude relation of the data value k. Outputs a potential on the low level side, and the gradation signal supply unit determines that the magnitude relationship between the average values of the gradation signals is the data value k.
9. The display drive device according to claim 7, wherein the common electrode drive section outputs a potential on the high level side in a time period in which the output is made to have the same magnitude relation as the magnitude relation. 14. The common electrode drive unit in a time period when the gradation signal supply unit outputs the gradation signal so that the relationship between the average values of the gradation signals is the same as the relationship between the data values k. Outputs a potential on the low level side, and the gradation signal supply unit determines that the magnitude relationship between the average values of the gradation signals is the data value k.
9. The display drive device according to claim 7, wherein the common electrode drive section outputs a high-level side potential in a time period in which the output is made to have a magnitude relation opposite to the magnitude relation. 15. A part of a plurality of necessary periodic signals is supplied from the gradation signal supply unit, and a part of the periodic signal supplied from the gradation signal supply unit is used as an inversion signal to output the periodic signal. 9. The display driving device according to claim 2, wherein the periodic signals are other than a part of the periodic signals. 16. A control pulse generator that obtains a control signal in synchronization with an inversion time period of a signal that inverts a high level and a low level for each output period of a periodic signal supplied from the gradation signal supply unit. Claims 2 or 7, 8 having
The display driving device described.