JPH071836B2 - Electronic information processing device - Google Patents
Electronic information processing deviceInfo
- Publication number
- JPH071836B2 JPH071836B2 JP62239353A JP23935387A JPH071836B2 JP H071836 B2 JPH071836 B2 JP H071836B2 JP 62239353 A JP62239353 A JP 62239353A JP 23935387 A JP23935387 A JP 23935387A JP H071836 B2 JPH071836 B2 JP H071836B2
- Authority
- JP
- Japan
- Prior art keywords
- boss portion
- information processing
- electronic information
- conductive film
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Mounting Of Printed Circuit Boards And The Like (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は電子情報処理装置の改良に係り，特にその電
波妨害の抑制手段に関するものである。Description: TECHNICAL FIELD The present invention relates to an improvement in an electronic information processing apparatus, and more particularly to a means for suppressing radio wave interference.
第２図および第３図は従来例を示すもので，図において
（１）は電磁波妨害の発生源であるIC等（５）が実装さ
れた基板，（４）はこの基板（１）を収納するプラスチ
ック製の筐体で，内底面には上記基板の取付け用の複数
のボス部が突設されており，これらの上に上記基板
（１）がねじ（３）で固定されている。（６）は上記ボ
ス部（２）を含めて筐体（４）の内面にメツキされた導
電膜である。2 and 3 show a conventional example, in which (1) is a board on which an IC or the like (5) that is a source of electromagnetic interference is mounted, and (4) stores this board (1). In this case, a plurality of bosses for mounting the above-mentioned substrate are projected on the inner bottom surface of the plastic casing, and the above-mentioned substrate (1) is fixed thereto by screws (3). (6) is a conductive film that is plated on the inner surface of the housing (4) including the boss (2).
第３図は上記ボス部（２）の拡大断面図であり，従来の
ボス部（２）の形状は円柱形または裁頭円錐台形になつ
ており，上記基板（１）の下面に接触する当該ボス部
（２）の頂面には導電膜（６）が形成され，基板（１）
の信号グランドに導電的に接続されていた。FIG. 3 is an enlarged cross-sectional view of the boss portion (2). The conventional boss portion (2) has a cylindrical shape or a truncated truncated cone shape, and is in contact with the lower surface of the substrate (1). A conductive film (6) is formed on the top surface of the boss (2), and the substrate (1)
Was conductively connected to the signal ground of.
従来のボス部（２）の形状は以上のように単純な円柱形
または裁頭円錐台形そのままであり，したがつてその周
面の表面積が比較的少なく，ボス部（２）の頂面と筐体
（４）の内底面に至る導電膜（６）の抵抗が比較的大き
いという問題点があつた。As described above, the shape of the conventional boss portion (2) remains the same as the simple cylindrical shape or truncated cone shape, and therefore the surface area of its peripheral surface is relatively small, and the top surface and the casing of the boss portion (2) are relatively small. There is a problem that the resistance of the conductive film (6) reaching the inner bottom surface of the body (4) is relatively large.
この発明は上記の問題点を解決するためになされたもの
で，円柱形または裁頭円錐台形のボス部の外周側面の表
面積をできるだけ広くし，被着される導電膜の量を多く
してその抵抗を少なくし，これによつて基板から発生す
る電磁波を上記導電膜により，より有効に抑制すること
を目的とする。The present invention has been made to solve the above-mentioned problems, and the surface area of the outer peripheral side surface of a cylindrical or frustoconical boss portion is made as large as possible to increase the amount of conductive film to be deposited. It is an object of the present invention to reduce the resistance and more effectively suppress the electromagnetic wave generated from the substrate by the conductive film.
この発明の場合は，プラスチック製の筐体（４）の内底
部に突設した円柱形または裁頭円錐形のボス部（２）の
外周側面に，例えば裾拡がりの複数の突出リブ（７）を
放射状に付加させてこれにより表面積を増大させ，また
は上記ボス部（２）の外周側面に，複数の凹溝を軸方向
に沿って付設することにより導電膜を厚くする等によ
り，ボス部（２）の頂面から筐体（４）の内底面に至る
電気抵抗をできるだけ小さくするようにしている。In the case of the present invention, a plurality of protruding ribs (7) having, for example, skirts are formed on the outer peripheral side surface of the cylindrical or frustoconical boss portion (2) projectingly provided on the inner bottom portion of the plastic housing (4). Are added radially to increase the surface area, or by forming a plurality of concave grooves along the axial direction on the outer peripheral side surface of the boss portion (2) to increase the thickness of the conductive film. The electric resistance from the top surface of 2) to the inner bottom surface of the housing (4) is made as small as possible.
この発明の場合は，ボス部の外周側面に付設された突出
リブまたは凹溝により，被着される導電膜の量が増大し
てその分抵抗が小さくなり，これにより基板の下面に接
触するボス部の外周側面のグランドパターンの電気抵抗
が減少し，筐体外部に放射する電磁波が有効に抑制され
る。In the case of the present invention, the protruding ribs or concave grooves provided on the outer peripheral side surface of the boss portion increase the amount of the conductive film to be deposited and reduce the resistance accordingly, so that the boss contacting the lower surface of the substrate is obtained. The electric resistance of the ground pattern on the outer peripheral side surface of the part is reduced, and electromagnetic waves radiated to the outside of the housing are effectively suppressed.
以下この発明の一実施例について説明する。すなち電子
情報処理装置としては第２図の従来のものと同一構成に
なつているので，その重複説明は省略することにする
が，第１図の（２）はこの発明のボス部であり，従来の
ように裁頭円錐台形になつているが，その周面には裾拡
がりの複数の突出リブ（７）および複数の凹溝（８）が
放射状に付設されて当該ボス部の外周側面の表面積が広
げられている点に特徴を有するものである。An embodiment of the present invention will be described below. That is, since the electronic information processing apparatus has the same configuration as that of the conventional one shown in FIG. 2, its duplicate description will be omitted, but (2) in FIG. 1 is the boss portion of the present invention. Although it has a truncated cone shape like the conventional one, a plurality of projecting ribs (7) and a plurality of recessed grooves (8) with flared skirts are radially attached to the outer peripheral surface of the boss portion. The feature is that the surface area of the side surface is widened.
したがつてこのボス部の頂面（９）から上記の筐体
（４）の内底面に被着される導電膜の量もその分多くな
り，これによりボス部（２）の頂面より筐体（４）の内
底面に至る電気抵抗を小さくすることができ，基板
（１）から発生する電磁波をより有効に抑制できること
になるものである。Therefore, the amount of the conductive film deposited on the inner bottom surface of the housing (4) from the top surface (9) of the boss portion also increases by that amount, which causes the housing to be larger than the top surface of the boss portion (2). The electric resistance reaching the inner bottom surface of the body (4) can be reduced, and the electromagnetic waves generated from the substrate (1) can be suppressed more effectively.
なお上記の実施例では裁頭円錐台形のボス部を示した
が，円柱形のボス部であつてもよく，かつ被着される導
電膜はメツキまたは塗装で行つてもよい。また実施例で
は突出リブと凹溝の双方を付設した場合について説明し
たが，そのいずれか一方のみの付設でもよく，さらにこ
の突出リブおよび凹溝の本数は当該ボス部の成形可能な
範囲で多くした方がよい。その他図中の（10）は基板
（１）の取付けねじ（３）が螺合されるねじ穴である。Although the truncated cone-shaped boss portion is shown in the above embodiment, it may be a cylindrical boss portion, and the conductive film to be deposited may be plated or painted. Further, in the embodiment, the case where both the protruding rib and the recessed groove are provided has been described, but only one of them may be provided, and the number of the protruding ribs and the recessed groove is large within a range in which the boss portion can be formed. You should do it. In addition, (10) in the drawing is a screw hole into which the mounting screw (3) of the substrate (1) is screwed.
この発明の電子情報処理装置では以上のようにして，基
板取付け用ボス部の外周側面のインピーダンスを低下さ
せているので，電磁波障害の抑制をきわめて簡単な手段
で達成できるという効果を有するものである。In the electronic information processing apparatus of the present invention, the impedance of the outer peripheral side surface of the board mounting boss portion is reduced as described above, so that it is possible to suppress electromagnetic interference by an extremely simple means. .
第１図はこの発明の電子情報処理装置における基板取付
け用ボス部の一実施例を示す斜視図，第２図は従来の電
子情報処理装置の要部を示す垂直断面図，第３図は第２
図の鎖線で囲まれた部分の拡大断面図である。 なお図において（１）は基板，（２）はボス部，（４）
は筐体，（５）はIC,（６）は導電膜，（７）は突出リ
ブ，（８）は凹溝である。 その他図中同一符号は同一部分を示すものとする。FIG. 1 is a perspective view showing an embodiment of a board mounting boss portion in an electronic information processing apparatus according to the present invention, FIG. 2 is a vertical sectional view showing a main portion of a conventional electronic information processing apparatus, and FIG. Two
It is an expanded sectional view of the portion enclosed with the chain line of a figure. In the figure, (1) is the substrate, (2) is the boss, (4)
Is a case, (5) is an IC, (6) is a conductive film, (7) is a protruding rib, and (8) is a concave groove. In other figures, the same reference numerals indicate the same parts.
Claims (1)
導電膜を施してグランドパターンを形成するボス部を内
底面に突設したプラスチック製の筐体を備えたものにお
いて，上記ボス部の外周側面に，その表面が上記導電膜
で覆われた複数の突出リブまたは複数の凹溝を，放射状
にまたは軸方向に沿って付設したことを特徴とする電子
情報処理装置。1. A plastic housing having a substrate on which an IC or the like is mounted, and a boss portion for forming a ground pattern by applying a conductive film on the surface of the substrate, which projects from an inner bottom surface. An electronic information processing device, comprising: a plurality of protruding ribs or a plurality of concave grooves, the surface of which is covered with the conductive film, provided radially or along the axial direction on the outer peripheral side surface of the boss portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62239353A JPH071836B2 (en) | 1987-09-24 | 1987-09-24 | Electronic information processing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62239353A JPH071836B2 (en) | 1987-09-24 | 1987-09-24 | Electronic information processing device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6481399A JPS6481399A (en) | 1989-03-27 |
| JPH071836B2 true JPH071836B2 (en) | 1995-01-11 |
Family
ID=17043488
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62239353A Expired - Lifetime JPH071836B2 (en) | 1987-09-24 | 1987-09-24 | Electronic information processing device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH071836B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0536560B1 (en) * | 1991-10-11 | 1996-06-12 | Asea Brown Boveri Ag | In- and/or output device for process data |
| JP2639280B2 (en) * | 1992-06-10 | 1997-08-06 | 松下電器産業株式会社 | Method for manufacturing high-density circuit module |
| JP3073162B2 (en) * | 1996-07-31 | 2000-08-07 | 株式会社ピーエフユー | Electronic equipment housing |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5895092U (en) * | 1981-12-20 | 1983-06-28 | 株式会社富士通ゼネラル | boss |
| JPS5934701A (en) * | 1982-08-23 | 1984-02-25 | Tdk Corp | Radio wave absorber |
| JPS61205200U (en) * | 1985-06-13 | 1986-12-24 |
-
1987
- 1987-09-24 JP JP62239353A patent/JPH071836B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6481399A (en) | 1989-03-27 |
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