JPH07183742A - Voltage-current conversion circuit - Google Patents

Abstract

PURPOSE:To improve the linearity of the output current of an input voltage by connecting the output terminal and the inverted input terminal of a differential amplifier having a high gain to the gate terminal and the source terminal of a differential MOS transistor TR respectively so that negative feedback takes place. CONSTITUTION:The output terminal and the inverted input terminal of a first differential amplifier G1 having a high gain are connected to the gate terminal and the source terminal of a MOS TR N1 respectively, and the amplifier G1 is subjected to negative feedback. As the result, the terminal voltage of an input terminal V1 and the source terminal voltage of the TR N1 are equalized. The output terminal and the inverted input terminal of a second differential amplifier G2 having a high gain are connected to the gate terminal and the source terminal of a MOS TR N2 respectively, and the amplifier G2 is subjected to negative feedback. As the result, the terminal voltage of an input terminal V2 and the source terminal voltage of the TR N2 are equalized. Thus, a voltage DELTAV1=V1=V2 is applied to both ends of a resistance 2R0, and a current DELTAV1/2R0 flows, and the differential input voltage is within the range of -R0.I 00<=DELTAV1<=R0.I00, and the differential current is DELTAI1=DELTAV1/R0 as shown by a formula I.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage-current conversion circuit, and more particularly to a MOS with reduced variation using field effect MOS transistors formed on a semiconductor integrated circuit chip.
The present invention relates to a differential voltage / current conversion circuit.

[0002]

2. Description of the Related Art The structure and operation of a conventional MOS differential voltage-current conversion circuit will be described with reference to the drawings.

FIG. 5 shows an example of a circuit configuration of a first conventional example. In FIG. 5, N _{1 and} N ₂ are the first and second differential N, respectively.
In the MOS transistors, V ₁ and V ₂ represent the first and second input terminals, respectively. 2I _{0 is} a source resistance that sets the current amplification factor _{of the} differential voltage-current conversion circuit,
I ₀₁ and I ₀₂ represent the first and second constant current sources, respectively, and the constant current I ₀₀ and the differential output current ΔI ₃ are defined as in equation (1).

The input / output characteristics of this circuit configuration are shown in FIG.
6A, the differential input voltage becomes 0 in FIG. 6A, and the current amplification factor gm is the maximum value gmmax.
The tangent line at the point of taking the value
Shown (defined) in (b) and equation (4).

[0005]

[0006]

The numerical values shown in 6 (a) and (b) above are I ₀₀ = 1 (mA), β = 1 × 10 ^-3 (A / V ² ), R ₀
= 1 (kΩ).

From FIGS. 6A and 6B, as the differential input voltage ΔV ₃ increases and the drain current difference ΔI ₃ between the first and second MOS transistors N ₁ and N ₂ increases, It can be seen that the absolute value of linearity is also increasing. In the MOS I _D -V _GS characteristic, this is the drain current I _D for the gate-source voltage V _GS of the MOS transistor.
Is not proportional to each other, the voltage across the current amplification factor setting resistor, that is, the differential output currents I ₃ = I ₁ −I of the first and second MOS transistors N ₁ and N ₂ is expressed by the equation (2). _This is a phenomenon that occurs because ₂ is not proportional to the differential input voltage ΔV ₃ = V ₁ −V ₂ .

FIG. 7 is a circuit diagram of the second conventional example. N ₁ and N _{2 in} FIG. 7 are the first and second differential N, respectively.
In the MOS transistors, V ₁ and V ₂ represent the first and second input terminals, respectively. Further, R ₀₁ and R ₀₂ are the first and the first, respectively, which set the current amplification factor of the differential voltage-current conversion circuit.
In the second source resistance, I ₀ represents a constant current source, and the source resistance R ₀₀ differential output current ΔI ₄ is defined as in Expression (5).

The input / output characteristics of this circuit configuration are shown in FIG.
8 (a) and equation (6), and in FIG. 8 (a), the non-linearity E is defined as in the first conventional example described above.
It shows in (b) and Formula (8).

[0011]

[0012]

Numerical values shown in FIGS. 8A and 8B are I ₀ = 1 (mA), β = 1 × 10 ^-3 (A / V ₂ ), R
_This is the case where ₀₀ = 1 (kΩ).

From FIGS. 8A and 8B, the differential input voltage ΔV ₄ increases and the first and second MOS transistors N ₁ ,
It can be seen that as the drain current difference ΔI _{4 of} N ₂ increases, the non-linear insulation value also increases. This is the first
MO in the MOS of the I _D -V _GS characteristics as in the conventional example
Since the change in the drain current I _D is not proportional to the gate-source sense voltage V _{GS of the} S-transistor, the voltage across the current amplification factor setting resistor, that is, the first and the second, is given by the equation (5).
Differential output current of the MOS transistor ΔI ₁ = I ₁ −I
_This is a phenomenon that occurs because ₂ is not proportional to the differential input voltage ΔV ₄ = V ₁ −V ₂ .

FIG. 9 shows an example of the circuit configuration of the third conventional example. This is also described in JP-A-57-46161. In this circuit, it is possible to reduce the non-linearity of the differential amplifier circuit by combining the differential amplifier circuit D and the bipolar current mirror circuits C ₁ and C ₂ having two outputs. Moreover, if the current mirror circuit and the constant current source are idealized, the input / output characteristics thereof are shown in FIG.
(A) and equation (11) are given, and the nonlinearity is shown in FIG.
(B) and equation (12) are obtained.

However, in order to take out the current to the outside, it is necessary to add a new circuit such as adding another output side transistor of the bipolar current mirror circuit. Moreover, since the non-linearity changes when a signal is input and the flowing current changes, the formula (1
It increases from the value obtained in 2), and the effect of improving linearity is weakened. Further, as shown in FIGS. 10A and 10B, the range of the differential current that can reduce the non-linearity is a range of 1/3 of the constant current I _0. In order to obtain an output equivalent to that of the example, it is necessary to triple the value of the constant current I ₀ .

Further, since the currents flowing through the transistors of the bipolar current mirror circuit and the differential MOS transistors have a mutual relationship, it is difficult to design the size of the transistors independently.

[0018]

[0019]

In the above-described first and second conventional MOS differential voltage / current conversion circuits, the differential input voltage increases and the differential output currents of the first and second MOS transistors increase. There was a problem that the linearity of the input / output characteristics deteriorated and the dynamic range decreased as the
Further, various characteristics of the MOS transistor (non-linearity of I _d -V _gs characteristics, variation of mutual conductance β, fluctuation of threshold voltage VT due to back gate effect, I _d -V in MOS saturation region due to short channel effect, etc. There was also the problem of increased nonlinearity due to the influence of _ds characteristic fluctuation).

Further, in the third conventional example, it is possible to reduce the non-linearity of the differential amplifier circuit by combining the differential amplifier circuit and the current mirror circuit using a bipolar process having two outputs. However, in order to take out the current to the outside, it is necessary to add a new circuit, which weakens the effect of improving the linearity. Further, even if the amplitude of the differential current output is the maximum, 1 / of the current value I ₀ of the constant current source
Since it is possible to obtain only three, it is necessary to triple the value of the constant current I _{0 in} order to obtain an output equivalent to that of the first and second conventional examples, and it is difficult to suppress the current consumption. Further, there is a problem that it is difficult to reduce the cost because the bipolar process and the MOS process are used.

Therefore, an object of the present invention is to provide a voltage-current conversion circuit that further improves the linearity of the output current with respect to the input voltage.

[0022]

A voltage-current conversion circuit according to the present invention is a voltage-current conversion circuit having first and second input terminals and first and second output terminals, the source of which is connected via a resistance section. First and second transistors connected to each other, collectors of which are connected to the first and second output terminals, respectively, and a current source section connected to the resistance section. And a first differential amplifier having an inverting input terminal, a non-inverting input terminal and an output terminal, wherein the non-inverting input terminal is connected to the first input terminal and the inverting input terminal is the first transistor. A first differential amplifier connected to the source and having the input end connected to the gate of the first transistor, and a second differential amplifier having an inverting input end, a non-inverting input end, and an output end. , The inverting input terminal is A second differential amplifier connected to a second input terminal, the inverting input terminal connected to the source of the second transistor, and the output terminal connected to the gate of the second transistor. Characterize.

Preferably, the current source section includes a first current source connected to one end of the resistance section and the source of the first transistor, the other end of the resistance section, and the second section.
A second current source connected to the source of the transistor.

Preferably, the resistance section includes first and second resistances connected in series, and the current source section includes the first resistance section.
Is connected to a connection point between the second resistance and the second resistance.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit configuration diagram of a differential current-voltage conversion circuit of a first embodiment according to the present invention. In this embodiment,
The first and second constant current sources I ₀₁ and I ₀₂ are connected to the source terminals of the first and second NMOS differential transistors N ₁ and N ₂ , respectively, and the first and second NMOS differential transistors are connected. This is an example in which one source resistor R ₀ is connected between the source terminals of. In FIG. 1, V ₁ and V ₂ are _first and _second , respectively.
, And I ₁ and I ₂ represent differential output currents.

Here, the high gain differential amplifiers G1 and G2 are M
In the first embodiment, an active load type MOS differential amplifier configured by an OS and using a differential circuit and a current mirror circuit is used.

The input / output characteristics of this circuit configuration are shown in FIG.
2 (a) and equation (13), and in FIG. 2 (a), the non-linearity E is defined as in the first and second conventional examples.
It shows in (b) and Formula (15).

[0029]

From FIGS. 2A and 2B, even if the differential input voltage increases and the drain current difference between the first and second MOS transistors increases, the non-linearity E does not increase and the differential E Current I1
E = 0 until −I ₂ becomes the constant current I ₀₀ .

In this embodiment, a high gain _first gate terminal and a source terminal of the first MOS transistor N ₁ are provided.
The output terminal and the inverting input terminal of the differential amplifier G1 are connected to each other, and the negative feedback is applied to the first differential amplifier G1, so that the first input terminal V ₁ and the source terminal of the _first MOS transistor N ₁ are connected. The output and the inverting input terminal of the high gain second differential amplifier G2 are respectively connected to the gate terminal and the source terminal of the second MOS transistor N ₂ with the same voltage, and the second differential amplifier G2 is connected to the second differential amplifier G2. By applying negative feedback, the second input terminal V ₂ and the source terminal voltage of the _second MOS transistor N ₂ are made equal. With such a configuration, Δ is provided at both ends of the resistor 2R _0.
Since a voltage of V ₁ = V ₁ −V ₂ is applied and a current represented by ΔV ₁ / 2R ₀ flows, that is, the differential input voltage is −
In the range of R ₀ · I ₀₀ ≦ ΔV ₁ ≦ R ₀ · I ₀₀ , the differential current is ΔI ₁ = ΔV ₁ / R ₀ as shown in the equation (13).

This first embodiment can be considered in exactly the same way when the NMOS transistor is replaced by a PMOS transistor and the PMOS transistor is replaced by an NMOS transistor.

FIG. 3 is a circuit configuration diagram of a differential current-voltage conversion circuit of the second embodiment according to the present invention. In this embodiment, one terminal of each of the first and second source resistors R ₀₁ and R ₀₂ is connected to the source terminal of each of the first and second NMOS differential transistors N ₁ and N ₂ , and the first , The other terminal of the second source resistor is commonly connected, and one constant current source I ₀ is connected to the commonly connected terminal. V in Fig. 3
₁ and V ₂ respectively represent the first and second input terminals,
I ₁ and I ₂ represent differential output currents.

Here, the high gain amplifiers G1 and G2 are M
It is composed of an OS (or a bipolar process). In the second embodiment, an active load type MOS differential amplifier using a differential circuit and a current mirror circuit is used.

The input / output terminals in this circuit configuration are shown in FIG.
4 (a) and the equation (16), and FIG. 4 (b) and the equation (16) are defined in the same manner as in the first and second conventional examples and the first embodiment in FIG. 4 (a). It is shown in (18).

[0036]

4A and 4B, even if the differential input voltage increases and the drain current difference between the first and second MOS transistors increases, the indirectness E does not increase and the differential current I _1- I
E = 0 until ₂ becomes the constant current I ₀ .

In this embodiment, the high gain _first gate is provided at the gate terminal and the source terminal of the first MOS transistor N 1.
The output terminal and the inverting input terminal of the differential amplifier G1 are connected to each other, and the negative feedback is applied to the first differential amplifier G1, so that the first input terminal V ₁ and the source terminal of the _first MOS transistor N ₁ are connected. equal voltage, and a second MOS transistor N ₂ of the gate terminal and the output terminal and the inverting input terminal of the high gain second differential amplifier G2 to the source terminal respectively connected to the second differential amplifier G2
By applying negative feedback to the second input terminal V ₂ and the source terminal voltage of the _second MOS transistor N ₂ are made equal to each other. Thus, at both ends of the resistor 2R ₀ △ V ₂ =
Since a voltage of V ₁ -V ₂ is applied and a current represented by ΔV ₁ / 2R ₀₀ flows, that is, the differential input voltage is -R ₀₀
In the range of I ₀ ≦ ΔV ₂ ≦ R ₀₀ · I ₀ , the differential current is expressed by the formula (1
As shown in 6), ΔI ₂ = ΔV ₂ / R ₀₀ .

The second embodiment can be considered in exactly the same way when the NMOS transistor is replaced with a PMOS transistor and the PMOS transistor is replaced with an NMOS transistor.

As described above, the two embodiments relating to the present invention are expressed by the formula (19) if I ₀ , I ₀₁ and I ₀₂ are regarded as ideal constant current sources.
It can be seen that an equivalent characteristic can be obtained for linearity by assuming

I ₀ = 2I ₀₁ = 2I ₀₂ , R ₀ = R ₀₁ = R _02- (19) According to the above-described embodiment of the present invention, the current amplification factor of the voltage-current conversion circuit is set only by the value of the source resistance. Even if the drain current difference between the first and second MOS transistors N ₁ and N ₂ increases as the differential input voltage increases, the non-linearity E is determined by the differential input voltage ΔV being -R. ₀ · I ₀₀ ≤ △ V ₁ ≤R
_A current of ΔV ₁ / R ₀ or ΔV ₂ / R ₀₀ within the range of ₀ · I ₀₀ or −R ₀₀ · I ₀ ≦ ΔV ₂ ≦ R ₀₀ · I ₀ as shown in formulas (13) and (16). Flows and the nonlinearity does not increase E =
It is 0. Therefore, the differential current ΔI = I ₁ −I ₂ can be realized in the output current range until the constant current ≦ I ₀ or ≦ ₂ I ₀₁ = ≦ ₂ I ₀₂ , and the output current range is wider than that of the third conventional example. Can be obtained.

Further, in this voltage-current conversion circuit, the various characteristics (I _d
It is possible to prevent the nonlinearity from increasing due to the nonlinearity of the −V _gs characteristic, the variation of the mutual conductance β, and the influence of the fluctuation of the threshold voltage VT due to the backgate effect. These characteristic variation factors are extremely large as compared with the bipolar or are peculiar to the MOS transistor and cannot be avoided by the conventional MOS transistor circuit, and the practical effect according to the present invention is extremely high.

Further, since the front circuit can be constructed by MOS, the cost can be reduced by simplifying the process.

[0044]

As described above, according to the present invention,
The sources of the first and second transistors are connected to each other via a resistance section, the current source section is connected to the resistance section, and the inverting input terminal of the first differential amplifier is connected to the source of the first transistor. The output terminal is connected to the gate of the first transistor, the inverting input terminal of the second differential amplifier is connected to the source of the second transistor, and the output terminal is connected to the gate of the second transistor. Therefore, the input voltages to the first and second input terminals are equal to the source terminal voltages of the first and second transistors, respectively, and the output currents from the first and second output terminals are equal to the first and second output terminals. The resistance value of the resistance part connecting the sources of the transistors can be determined. Therefore, the linearity of the output current with respect to the input voltage can be further improved.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a first embodiment of the present invention.

FIG. 2 is a graph showing input / output characteristics and non-linearity characteristics of the first embodiment of the present invention.

FIG. 3 is a circuit configuration diagram of a second embodiment of the present invention.

FIG. 4 is a graph showing input / output characteristics and non-linearity characteristics of the second embodiment of the present invention.

FIG. 5 is a circuit configuration diagram of a first conventional example.

FIG. 6 is a graph showing an input / output characteristic and a non-linear characteristic of the first conventional example.

FIG. 7 is a circuit configuration diagram of a second conventional example.

FIG. 8 is a graph showing an input / output characteristic and a non-linear characteristic of the second conventional example.

FIG. 9 is a circuit configuration diagram of a third conventional example.

FIG. 10 is a graph showing input / output characteristics and non-linearity characteristics of a third conventional example.

[Explanation of symbols]

N _{1 to} N ₆ N channel MOS transistor P _{3 to} P ₆ P channel MOS transistor Q _{1 to} Q ₄ PNP type bipolar transistor R ₀ , R ₀₁ , R ₀₂ Source resistance and resistance value R _{1 to} R ₄ Emitter resistance for current mirror L ₁ , L ₂ level shift circuit C ₁ , C ₂ current mirror circuit D differential circuit G 1, G 2 high gain amplifier I ₀ , I _{01 to} I ₀₄ constant current source and current value I ₁ , I ₂ output current V ₁ , V ₂ input terminal and voltage V _DD , V _SS high-potential power supply, low-potential power supply V _{B1 to} V _B6 back gate terminal and voltage a1 to a5 input / output characteristic curve b1 to b5 tangential line at input voltage 0 V c1 to c5 indirect Sex curve

Claims (3)

[Claims] 1. First and second input terminals, first and second
In the voltage-current conversion circuit having the output terminal of, the sources are first and second transistors connected to each other via a resistance part, and collectors are respectively connected to the first and second output terminals. First and second transistors, a current source section connected to the resistance section, an inverting input terminal,
A first differential amplifier having a non-inverting input terminal and an output terminal, wherein the non-inverting input terminal is connected to the first input terminal and the inverting input terminal is connected to the source of the first transistor. A first differential amplifier having the input terminal connected to the gate of the first transistor, and a second differential amplifier having an inverting input terminal, a non-inverting input terminal and an output terminal, A second differential amplifier having an end connected to the second input terminal, the inverting input end connected to the source of the second transistor, and the output end connected to the gate of the second transistor. A voltage-current conversion circuit having. 2. The first current source section is connected to one end of the resistance section and the source of the first transistor.
2. The voltage-current conversion circuit according to claim 1, further comprising a second current source connected to the current source and the other end of the resistance section and the source of the second transistor. 3. The resistance section includes first and second resistances connected in series, and the current source section is connected to a connection point between the first resistance and the second resistance. The voltage / current conversion circuit according to claim 1.