JPH07191099A - IC inspection device - Google Patents

Abstract

(57) [Abstract] [Purpose] An object of the present invention is to provide an IC inspection apparatus in which the capacity of a memory for storing an address conversion table is reduced and the address conversion conditions can be switched in a short time. A pattern generating section, a memory for storing a plurality of address conversion tables, an address register for storing data of an address signal for accessing the memory, and a receiving pattern generating section for receiving the data of the address register as first data. Received the second data as the first data
, A selector for selecting a predetermined bit of the data and a predetermined bit of the second data according to a control signal to generate an address signal of the memory and transmitting the signal to the memory, and a selector for storing the control signal and transmitting the control signal to the selector And a control data register.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC inspection device for inspecting an IC such as a memory, and more specifically, conversion of an address signal generated by a pattern generator from a logical address to a physical address (address / address). The present invention relates to an address conversion circuit for performing scrambling.

[0002]

2. Description of the Related Art An address conversion method in a conventional IC inspection apparatus is provided with an address conversion table (generally placed in a random access memory), and the address signal output from a pattern generator is used as address information to read the address conversion table. By performing the above, the address signal after the address conversion is obtained. Further, the address conversion table is generally rewritable by the central processing unit (CPU) of the IC inspection device.

FIG. 2 shows an application filed by the applicant of the present application.
This is the address conversion method shown in No. 3-166100. In the figure, 1 is a pattern generation unit of the IC inspection apparatus. The pattern generation unit 1 is generally an algorithmic pattern generation circuit, and a central processing unit (CPU) 2 of an IC inspection device.
An address signal A, a data pattern, and other control signals are generated in accordance with the program loaded from. A random access memory 3 stores a plurality of address conversion tables 41 to 4n. This random access memory 3 can be accessed by the central processing unit 2, and address translation information of different translation conditions is written in each address translation table 4 prior to the inspection.

S is a table selection signal for selectively enabling the address conversion table 4, which is set in the register 5 from the central processing unit 2. Naturally, this table selection signal S can be controlled by the central processing unit 2. The address signal A and the table selection signal S are input to the random access memory 3 as address information signals.

In such a structure, the random access memory 3 is accessed by using the address signal A and the table selection signal S output from the pattern generator 1 as address information signals. As a result, the table selection signal S
Of one address translation table 4 enabled by
Information on an address determined by the address signal A is read out and output from the random access memory 3 as an address signal B after address conversion.

When the address conversion conditions need to be switched, the central processing unit 2 resets the table selection signal S for validating the necessary address conversion table 4 in the register 5, thereby The address conversion of the address signal A is performed under the conversion condition corresponding to the address conversion table 4. Since such a setting operation of the table selection signal S can be performed in a short time, the interruption time of the inspection for switching the address conversion condition can be made extremely short. Therefore, it is possible to perform the inspection while dynamically changing the address conversion condition in real time.

[0007]

However, the data stored in the register is one for selecting one of several fixed address conversion tables, and the width of the address conversion table is set in the register 5. It is fixed by the number of bits stored. On the other hand, there are various bit widths of addresses and data of IC devices to be tested. As a result, it is necessary to individually prepare the address conversion tables according to the maximum bit width, and there is a disadvantage that the storage capacity of the RAM to be stored increases as the number of conversion tables increases. The present invention provides an IC inspection apparatus that solves the above-mentioned conventional problems, reduces the capacity of a memory that stores an address conversion table, and enables switching of address conversion conditions in a short time. It is in.

[0008]

In order to achieve this object, the features of the IC inspection apparatus of the present invention are: a pattern generating section; a memory for storing a plurality of address conversion tables;
An address register for storing data of an address signal for accessing the memory, a data of the address register as first data, data of the receiving pattern generating section as second data, and a predetermined bit of the first data. A selector provided with a selector for selecting a predetermined bit of the second data according to a control signal to generate an address signal of the memory and sending it to the memory, and a control data register for storing the control signal and sending it to the selector. Is.

[0009]

As described above, the access address of the memory storing the address conversion table is generated by combining the data from the pattern generator and the data stored in the register, so that the width of the stored address conversion table is increased. Can be set freely. Moreover, if the data on the pattern generator side is selected as the upper address side and the address register side is set as the lower address side, the address conversion table can be accessed at fixed addresses, enabling dynamic address conversion at high speed. Become. As a result, address conversion can be performed by selectively using a plurality of address conversion tables whose widths are not fixed, the memory capacity for storing the address conversion tables can be small, and different conversion conditions can be set in advance for each address conversion table. If registered in the table, conversion conditions can be switched in a short time.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a schematic block diagram showing an embodiment centering on an address conversion portion of an IC inspection device according to the present invention. The same components as those in FIG. 2 are designated by the same reference numerals. 2 is different from FIG. 2 in that an address register 5a is provided instead of the register 5, and the pattern generator 1
That is, the selector 7 receives the signal (address data) of the address register 5a and the address signal of the RAM 3 is added from the selector 7. The selector 7 is a part of the data n + m bits of the pattern generator 1,
Upon receiving the bit data of the lower m bits, the bit at the designated digit position is selected from the m bits, and further, the bit at the designated digit position of the data m bits of the address register 5a is selected and selected. The bits are combined to generate data of the address signal m + m bits. The accessed address of the RAM 3 has a width of n + 2m bits.

In order to select each digit position, the control data register 6a for storing selection control data for selecting the digit position of the data of the pattern generator 1 and the output of each digit bit of this output are digitized. An inverter circuit 6b is provided which correspondingly inverts and generates selection control data for selecting the digit position of the data in the digit address register 5a.

The RAM 3 stores a plurality of address conversion tables 4a-4x having different storage area widths. This RAM 3 can be accessed by the central processing unit 2, and address conversion information of different conversion conditions is written in each address conversion table prior to the inspection. The control data register 6a stores m-bit data, the valid digit position data of the m-bit data of the pattern generation unit 1 is set to "1", and the invalid digit position is " It is set to 0 ″ and masked by the selector 7. Inverter circuit 6b
Is to invert the bit pattern of "1" and "0", and conversely, in the address register 5a, the signal of the valid digit in the m-bit data of the pattern generating section 1 becomes invalid. , The signal of the invalid digit becomes valid.
The m-bit address signal selected by this is the signal m at each valid digit position obtained by combining the data of the pattern generator 1 and the data of the address register 5a.
Become a bit.

As a result, if it is desired to validate the upper 3 digits of the data of the pattern generating section 1 and combine it with the lower digits of the data of the address register 5a, "111000" is used.
The data m bits of "..." may be set in the control data register 6a from the central processing unit 2. Conversely, the pattern generating unit 1
Address register 5 by enabling the lower 3 digits of the data
If you want to combine with the upper digit of the data of a, enter "0".
The data m bits of 00 ... 111 "may be set in the control data register 6a from the central processing unit 2.

The number of upper digits, in other words, the bit width thereof becomes the width of the address conversion table. The upper n bits are
Since it is provided from the pattern generation unit 2, it can be dynamically changed. Therefore, the address conversion tables 4a to 4x.
The width of can be changed dynamically. When the upper digit is fixed, the data of the address register 5a may be fixed to n bits provided from the pattern generating section 2 as the upper digit. When it is desired to access the address of a certain address conversion table at every y address, it is possible to select the lower digit position of the data of the address register 5a corresponding to the y address by validating the corresponding width.

In the above configuration, the upper n bits of the pattern generating section 2 may be eliminated, the number of generated bits of the pattern generating section 2 may be set to m bits, and all the bits may be sent to the selector 7. Conversely, as shown by the dotted line,
The number of bits of the address register 5a may be m + k bits, and the k-bit data of the upper or lower digit may be directly used as the address access data of the RAM 3 and the table selection signal S without being sent to the selector 7. When such a table selection signal S is generated, the inverter circuit 6a is not an inverter, but a register for independently setting and storing control data from the central processing unit 2 is used, and the selector 7 corresponding to the table selection signal S is used. It is assumed that the data for masking the bit at the specific digit position of is added to the selector 7.

Further, as shown by the dotted line, the upper n bits of data of the pattern generator 2 are transferred to the control data register 6a.
Alternatively, the digit position may be dynamically selected by the selector for the next address signal. Next, the operation when the address size required for the device test is smaller than the size of each address conversion table 4 inside the RAM 3 and the table can be divided into t parts for use will be described. It is assumed that the number of bits of the address register 5a is m + k bits and the upper k-bit data is sent to the selector 7 as a table selection signal S. In this case, the inverter circuit 6a is not an inverter but a register for storing control data for masking the digit position of the table selection signal S.

The data of the address signal A'input to the RAM 3 is controlled so that the lower bits are the address pattern signal from the pattern generator 1 and the upper bits are the switching information of different patterns from the address register 5a. Data is set in the register 6a. At this time, the selector 7 can freely switch p bits of information from the upper bits of the lower bits of the address signal A and output q bits (where p + q = m) of the address register 5a by setting the control data register 6a. Therefore, the output of the address / address register 5a is switched so that it is sent to the selector 7 by the number of bits to be divided by t. Further, the table selection signal S sets the upper bits of the address address register 5a so as to indicate one target address conversion table.

In this setting, the address signal A output from the pattern generator 1 accesses a specific area divided into t in one address conversion table, and is output from the RAM 3 as an address signal B after address conversion. It When it becomes necessary to switch the address conversion conditions, the central processing unit 2 side resets the lower q bits of the address register 5a in order to validate the table in the necessary area, so that the address conversion area is reset. The address conversion of the address signal A is performed under the conversion condition corresponding to.

If the conversion table required under the above conditions does not fit in the RAM 3, the upper bit of the address register 5a is operated and the table selection signal S is operated to prepare it in another table in advance. It is also possible to read the stored next address conversion information. Since the setting operation of the table selection signal S can be performed in a short time, it is possible to perform the inspection while dynamically changing the address conversion condition in real time.

[0020]

As is apparent from the above description, according to the present invention, the access address of the memory storing the address conversion table is generated by combining the data from the pattern generator and the data stored in the register. By doing so, the width of the stored address conversion table can be freely set. Moreover, if the data on the pattern generator side is selected as the upper address side and the address register side is set as the lower address side, the address conversion table can be accessed at fixed addresses, enabling dynamic address conversion at high speed. Become. As a result, address conversion can be performed by selectively using a plurality of address conversion tables whose widths are not fixed, and the memory capacity for storing the address conversion tables can be small.
If different conversion conditions are registered in advance in the respective address conversion tables, the conversion conditions can be switched in a short time. Therefore, the efficiency of the inspection process can be improved, and if the central processing unit of the inspection device directly sets and controls the data in the control data register, the inspection can be performed while dynamically changing the address conversion conditions in real time. It is possible. Further, since it is possible to rewrite another address conversion table during the inspection using a certain address conversion table, the inspection will not be interrupted due to the change of the address conversion condition.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing an embodiment centering on an address conversion portion of an IC inspection apparatus according to the present invention.

FIG. 2 is a block diagram of an address conversion method in a conventional IC inspection device.

[Explanation of symbols]

1 ... Pattern generation unit, 2 ... Central processing unit, 3 ... RAM, 4
a to 4x ... Address conversion table, 5 ... Register, 5a
... address register, 6 ... control data register, 7 ... selector, A ... pre-conversion address signal, B ... post-conversion address signal, S ... table selection signal.

Claims (2)

[Claims] 1. A pattern generator, a memory for storing a plurality of address conversion tables, and an address register for storing data of an address signal for accessing the memory.
The data of the address register is received as first data, the data of the pattern generating section is received as second data, and a predetermined bit of the first data and a predetermined bit of the second data are respectively received according to a control signal. An IC inspecting apparatus comprising: a selector which selects and generates an address signal of the memory and sends the address signal to the memory; and a control data register which stores the control signal and sends the control signal to the selector. 2. A processor having a processor, wherein the control data register stores data for selecting a digit to be output as the address signal by the selector from the first data, and the data of the register. And an inverter circuit that generates data for selecting a digit to be output by the selector as the address signal, the processor sends data to the register, and outputs data of the address signal to the address register. The IC inspection device according to claim 1, wherein