JPH071920B2 - Vertical deflection circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a vertical deflection circuit of a TV (television) receiver, and particularly to a TV receiver for displaying characters on a TV screen when there is no signal. The present invention relates to a vertical deflection circuit suitable for use in.

(B) Prior Art A countdown vertical deflection circuit for generating a vertical drive pulse in response to a vertical synchronization signal from a synchronization separation circuit is disclosed in Japanese Utility Model Laid-Open No. 60-98971.

According to the vertical deflection circuit described in the above publication, when the vertical synchronizing signal arrives, the counter can generate a vertical drive pulse having a constant cycle in synchronization with it. Further, when the vertical synchronizing signal does not arrive, the counter is in a self-reset operation and it is possible to generate a vertical driving pulse having a period longer than the fixed period. The period of the vertical drive pulse during the self-reset operation is normally set to be several tens H (H is one period of the horizontal synchronizing signal) longer than the fixed period, which is longer than the normal period. This is to enable synchronization when a synchronization signal arrives.

(C) Problems to be Solved by the Invention By the way, recently, a TV receiver having a function of displaying character information (channel display or video input display) on a part of a TV screen has appeared. In the above, the read operation start time of the memory in which the character information is stored is controlled according to the vertical drive pulse generated from the counter. By doing so, the character information can be displayed at a predetermined position in the vertical direction. The memory is configured to generate character information a predetermined time after the input trigger (vertical drive pulse) is applied. Therefore, when a vertical drive pulse having a regular cycle is applied, a desired position can be set on the screen. However, in the case of no signal (for example, when receiving an empty channel), the above-mentioned counter generates a vertical drive pulse having a long period, and when the memory is driven accordingly, the position of the character information on the screen is increased. Has a problem that it is generated in the upper part as compared with the normal case and is unsightly, and in an extreme case, it is shifted out of the screen.

(D) Means for Solving the Problems The present invention has been made in view of the above points, and includes a counter which is reset in response to an external vertical synchronizing signal and which generates a vertical drive pulse in response to the reset. , A no-signal detection circuit for detecting the absence of the vertical synchronization signal.

(E) Operation According to the present invention, when the absence of the vertical synchronizing signal coming from the outside is detected, the counter for generating the vertical drive pulse is reset in a predetermined vertical cycle in accordance with the detection. Character information can be displayed at a predetermined position even when there is no signal.

(F) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention, in which (1) is a sync for separating a vertical sync signal and a horizontal sync signal from a composite sync signal applied to an input terminal (2). Separation circuit, (3)
Is a horizontal AFC circuit to which the horizontal sync signal from the sync separation circuit (1) is applied, and (4) is a clock signal of a frequency 2f _H (f _H is a horizontal sync signal frequency) from the horizontal AFC circuit (3). Counts and outputs the first to fourth frequency division output signals (φ _{1 to} φ ₄ )
A gate circuit for passing a vertical synchronizing signal in accordance with the _first frequency-divided output signal φ ₁ from the counter (4), and (6) a vertical synchronizing signal from the gate circuit (5). An OR gate for passing the signal and the second divided output signal φ ₂ from the counter (4), and (7) an output signal of the OR gate (6) and a third divided output signal φ ₃ from the counter (4). A switch for switching output of (8), a non-signal detection circuit for detecting the absence of an incoming vertical synchronizing signal and switching the switch (7) according to the detected output.
(9) is a character display memory for generating an image signal having character information according to a vertical drive pulse from the counter (4), and (10) is an image signal from the character display memory (9) and a terminal (11). (12) subtracts the luminance signal from the adding circuit (10) and each color difference signal to generate R, G, B primary color signals. The circuit and (13) are cathode ray tubes.

The first frequency division output signal φ ₁ generated from the counter (4)
Between 224H and 297H, the second divided output signal φ ₂ is generated after 297H, the third divided output signal φ ₃ is generated after 262.5H, and the fourth divided output signal φ ₄ is generated after 1.5H. . H indicates one cycle of the horizontal synchronizing signal.

Generally, the period of the vertical synchronization signal of the NTSC system is 262.5H. Now, a vertical sync signal with such a regular cycle is
If it is generated from the sync separation circuit (1), the vertical sync signal is applied to the gate circuit (5) and also to the no-signal detection circuit (8). Then, the no-signal detection circuit (8) detects the presence of the vertical synchronization signal, and the "H"
Generates a level switching control signal. Then, the switch (7) is switched to the contact a side according to the switching control signal. Since the gate period of the gate circuit (5) is between 224H and 297H, the vertical synchronizing signal arriving at the 262.5H cycle passes through the gate circuit (5) as it is, and the OR gate (6) and the switch (7). Is applied to the reset terminal R of the counter (4) via. Therefore, the counter (4) is once reset in response to the vertical synchronizing signal and starts counting again. Then, the same operation is repeated according to the vertical synchronizing signals that sequentially arrive.

The counter (4) generates a vertical drive pulse having a predetermined width at the output terminal (14) after reset. The vertical drive pulse is amplified by an amplifier (15) and then supplied as a deflection current to a vertical deflection coil (16) of a cathode ray tube (13).

On the other hand, the vertical drive pulse is applied to the character display memory (9) as a trigger signal that determines the operation start time. Then, the character display memory (9) starts its operation accordingly, and starts the read operation based on the clock signal supplied from the horizontal AFC circuit (3).
An image signal having text information is generated. Then, the image signal is added to the luminance signal applied to the terminal (11) in the addition circuit (10), and the luminance signal after the addition is subtracted in the subtraction circuit (12).
Applied to. Then, the luminance signal and the terminal (17),
(18) and (19) each color difference signal (RY, GY, B-
Y) and the primary color signals (R, G, B) are applied to the cathode ray tube (13). Therefore, according to the circuit of FIG. 1, character information can be generated on the TV screen.

The character information in the embodiment of FIG. 1 is represented in black and white.

Next, a case will be described in which character information is generated when a vertical synchronization signal does not exist, such as when receiving a station with an empty channel. In this case, since no vertical sync signal is generated from the sync separation circuit (1), no signal is applied to the gate circuit (5) and the no-signal detection circuit (8). Then, the counter (4) advances the counting, and when it reaches 297H, the second
The divided output signal φ ₂ is generated. The second frequency division output signal φ
₂ is applied to the reset terminal R of the counter (4) via the OR gate (6) and the switch (7) and is also applied to the no-signal detection circuit (8). Then, in response to the _second frequency-divided output signal φ ₂ , the no-signal detection circuit (8) generates a "L" level switching control signal indicating that there is no signal, and switches the switch (7) to the contact b. Switch to the side. The counter (4) is reset in response to the second frequency-divided output signal φ ₂ and then counts up again. When the counter reaches 262.5H, a third frequency-divided output signal φ ₃ is generated. The third frequency division output signal φ ₃ is
Since it is applied to the reset terminal R of the counter (4) via the switch (7), the counter (4) is in a self-reset operation and generates a vertical drive pulse of a constant cycle (262.5H) at the output terminal (14).

Therefore, even in the state of no signal, the vertical drive pulse having the normal vertical cycle can be applied to the character display memory (9) as a trigger, and the generation of the image signal can be made equal to that in the above case.

FIG. 2 is a circuit diagram showing a specific circuit example of the no-signal detection circuit (8) of FIG. 1, in which the vertical sync signal from the sync separation circuit (1) applied to the terminal (20) is It is applied to the set inputs of the second flip-flops (21) and (22).
The output signal of the switch (7) is applied to the terminal (24) of the AND gate (23) controlled by the Q output of the first flip-flop (21), and the output signal of the AND gate (23) is the second signal. Applied to the reset input of the flip-flop (22). Therefore, the Q output terminal (26) of the second flip-flop (22) is at “H” level when there is a signal and “L” when there is no signal.
The discriminant output of the level is obtained.

The reset input of the first flip-flop (21) is applied with the fourth output signal φ ₄ from the terminal (25), which returns the first flip-flop (21) to the initial state. Anything may be used as long as it occurs within a fixed period after the reset in (4).

(G) Effect of the Invention As described above, according to the present invention, when the absence of the vertical synchronizing signal is detected, the counter is self-reset in a predetermined vertical cycle according to the detection. Also
Character information can be displayed at a predetermined position on the TV screen. In particular, if the vertical cycle is set equal to the normal vertical cycle, the character information can be displayed at the same position as in the case of a signal.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a concrete circuit example of the no-signal detection circuit (8) of FIG. (4) ... Counter, (6) ... OR gate, (7) ...
… Switch, (8) …… No signal detection circuit, (9) …… Memory for character display.

Claims (2)

[Claims] 1. A first frequency-divided output signal having a predetermined vertical cycle, a second frequency-divided output signal which is generated when asynchronous and has a cycle longer than the cycle of the first frequency-divided output signal, and which is generated in response to a reset To generate a vertical drive pulse, an OR gate to which an external vertical synchronizing signal and the second frequency division output signal are applied, and a first frequency division output signal and an output signal of the OR gate. A switch for outputting and applying as a reset pulse to the counter, an output signal of the switch and a vertical synchronizing signal from the outside are applied to detect the absence of the vertical synchronizing signal from the outside, and depending on the detected output. And a signalless detection circuit for switching the switch. 2. The vertical deflection circuit according to claim 1, wherein the operation start time of the character display memory is controlled according to a vertical drive pulse generated from the counter.