JPH07200111A - Computer system - Google Patents

Abstract

(57) [Abstract] [Purpose] To realize a CPU sleep function that is not affected by the OS environment. [Structure] Various hardware interrupt request signals IRQ0 to IRQ15, NMI in the system are monitored, and all other interrupt request signals except timer interrupt (IRQ0) are 4
Global standby SMI is C when not generated for seconds
It is supplied to the PU 11. This global standby SM
The global standby SMI routine executed by I sets the CPU 11 in the stop grant state. As a result, the CPU 11 shifts to the sleep mode. By performing sleep control using such a global standby SMI, the same sleep mode function can be always provided regardless of the OS environment, and the number of triggers for shifting the CPU 11 to the sleep mode is increased. be able to.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laptop type or notebook type portable personal computer system, and more particularly to a computer system having a function of controlling the operating speed of a CPU in order to reduce power consumption.

[0002]

2. Description of the Related Art In recent years, various laptop or notebook type personal portable computers which are easy to carry and can be operated by a battery have been developed. This type of portable computer is provided with a so-called CPU sleep mode function of automatically stopping the CPU under predetermined conditions in order to reduce unnecessary power consumption.

The conventional CPU sleep mode function is executed on condition that the keyboard operation by the operator is not executed for a predetermined time or longer.

That is, when the application program waits for a key input, the BIOS (Basic I / O)
System) INT16H is called, and the keyboard control routine is executed. This BIOS keyboard control routine is an HA for stopping the program execution by the CPU if there is no keyboard input within a fixed time.
Execute the LT instruction. When this HALT cycle of the CPU is detected by the system hardware, the system hardware puts the CPU into the sleep mode by reducing the clock frequency or completely stopping the clock in order to reduce the power consumption of the CPU. . When the CPU is in the sleep mode, no program execution is performed by the CPU, whether the clock frequency is reduced or the clock is completely stopped.

However, the CPU idle state that can be detected by the conventional sleep mode function is only the CPU idle state when the application program waits for keyboard input. Therefore, when the application program has completed the operation of the I / O device other than the keyboard, the CPU cannot be put into the sleep mode even when the CPU is in the idle state.

In this case, the CPU power is wasted for the time required to complete the operation of the I / O device. In particular, if the application program is waiting for an operation completion notification from an I / O device with a slow operation speed or an operation completion notification from an I / O device with high intelligence such as a bus master, the CPU Is in idle state for a relatively long time, the CPU cannot enter sleep mode. For this reason, the power consumed by the CPU is wasted.

As described above, the conventional sleep mode function has a drawback that sufficient power saving cannot be realized because there are few triggers that trigger the CPU to shift to the sleep mode.

The BIOS can control the system hardware only under a specific operating system (OS) environment corresponding to the BIOS. Therefore, whether the sleep mode function operates normally depends on the OS.
Depending on the environment, the sleep mode function may not work depending on the OS environment.

Further, in the conventional sleep mode function,
There is a problem that it takes time to return the CPU from the sleep mode.

That is, when some kind of system event occurs while the CPU is in the sleep mode, the system hardware restarts the clock supply to the CPU or raises the clock frequency. However, even if the clock is switched to the normal state, the CPU operation cannot be started immediately. Especially, the recent PLL (Phase Loc)
Ked Loop) built-in high performance microprocessor,
For example, in an Intel486 series microprocessor developed and manufactured and sold by Intel Corporation of the US, a certain period (for example, 1
(about ms), the operation of the CPU is delayed. this is,
For the following reasons.

That is, this type of microprocessor has an internal oscillator including a PLL, generates a high-speed clock synchronized with an externally supplied clock by the PLL, and uses it to realize a high-speed operation. . Therefore, in order for this microprocessor to operate normally, the phase of the clock supplied from the outside must be stable. Otherwise, the PLL synchronous operation will be abnormal. Therefore, in a system using a high-performance microprocessor with a built-in PLL as a CPU, if the conventional sleep mode function for switching the CPU clock is applied, it takes a long time to recover from the sleep mode and the system performance is deteriorated. There is a drawback.

[0012]

In the conventional sleep mode function, the CPU is set in the sleep mode only in the following manner.
Only when the BIOS keyboard control routine detects that there is no keyboard input for a certain period of time. For this reason,
There were few triggers for shifting the CPU to the sleep mode, and it was often impossible to shift the CPU to the sleep mode even when the CPU was in the idle state. Also, B
Since the IOS can control the hardware only in the OS environment corresponding to the BIOS, C can be controlled by the OS environment.
There was a drawback that the PU could not be put into sleep mode. Further, since the CPU clock is lowered or stopped in the sleep mode, it takes a long time to return from the sleep mode to the normal mode.

The present invention has been made in view of the above circumstances, and provides a computer system capable of always realizing the same sleep mode regardless of the OS environment and sufficiently reducing the power consumption of the CPU. The purpose is to provide.

The present invention also provides a high-performance C with a built-in PLL.
An object of the present invention is to provide a computer system capable of returning a PU from a sleep mode at high speed.

[0015]

A computer system according to the present invention stores a main memory in which various programs to be executed are stored and an instruction for calling a system management program, and stores the address space in the main memory. It has an overlay memory mapped to a part, a program execution mode for executing a program of the main memory, and a system management mode for executing an instruction of the overlay memory, and has an interrupt signal supplied to a predetermined interrupt input terminal. CP in response to switch from the program execution mode to the system management mode
U, CPU sleep means for executing a sleep control routine included in the system management program called by the CPU, and switching the operating state of the CPU from a first state to a second state in which power consumption is lower than that of the first state; System idle detection that monitors various hardware interrupt request signals to the CPU generated in the computer system and detects a system idle when all the hardware interrupt request signals are not generated for a preset first timeout time Means for supplying the interrupt signal indicating the system idle to the interrupt input terminal of the CPU in response to the detection of the system idle by the system idle detecting means, and the CPU sleep means executes the switching processing of the operating state of the CPU. And means A first feature in that.

In this computer system, various hardware interrupt request signals in the system are monitored, and when all the hardware interrupt request signals are not generated for a predetermined time, system idle is detected, whereby the CPU shifts to the sleep mode. To be done. Therefore, the number of triggers for shifting the CPU to the sleep mode is increased, and not only the CPU idle when the application program waits for keyboard input but also the application program has the operation completion of the I / O device other than the keyboard. Even in such a case, the CPU can be shifted to the sleep mode. Therefore, C
It is possible to prevent the situation where the CPU is kept in the operating state even though the PU is idle, and it is possible to sufficiently reduce the power consumption of the CPU.

A hardware interrupt request signal is used to detect the system idle. This hardware interrupt request signal is a physical signal generated from various I / O devices in the system, and is detected by B
No IOS is used. Further, the processing of the CPU sleep means can be activated only by supplying the interrupt signal to the CPU, and the OS and the BIOS have no concern with the activation processing of the CPU sleep means. Therefore, it is possible to detect the system idle and control the CPU sleep at the hardware level, and always realize the same sleep mode function regardless of the OS environment.

Further, the computer system according to the present invention generates the internal clock in accordance with the external clock.
A normal state in which LL is built in and instructions are executed,
It includes a clock stop state in which instruction execution and the external clock are stopped, and a clock stop enable state which is located between the normal state and the clock stop state and in which instruction execution is stopped and the external clock can be stopped. Has an operating state, transitions from the normal state to the clock stop permission state in response to the generation of a clock stop signal indicating clock stop permission, and changes from the clock stop permission state in response to the stop of generation of the clock stop signal C returned to normal state
Using the PU, the CPU sleep means for the CPU
Is set to a clock stop permission state.

In this computer system, C
The CPU clock stop permission state is used for PU sleep. In this state, execution of all instructions is stopped, so without stopping the external clock,
The power consumption of the CPU can be reduced. For this reason,
Since the CPU can wake up from sleep mode without dynamically switching the external clock, high-performance C with a built-in PLL
It is possible to wake up the PU from the sleep mode at high speed.

Further, the computer system according to the present invention has a built-in PLL for generating an internal clock in response to an external clock, and has a normal state in which an instruction is executed and a clock stop state in which the instruction execution and the external clock are stopped. A clock stop signal indicating a clock stop permission, which has an operation state located between the normal state and the clock stop state and including a clock stop permission state in which instruction execution is stopped and the external clock can be stopped. In response to the generation of the clock stop permission state, and in response to the stop of the generation of the clock stop signal from the clock stop permission state to the normal state, the CPU and the clock stop signal. Generating means for generating clock stop signal A main memory that stores various programs executed by the CPU, and an overlay memory that stores an instruction for calling a system management program and is mapped to a part of an address space of the main memory. An overlay memory for executing the instruction by the CPU when an interrupt signal is supplied to an interrupt input terminal;
CPU sleep means for executing a sleep control routine included in the system management program called by U and instructing the clock stop signal generation means to generate a clock stop signal, and various CPU sleep means generated in the computer system. A system idle detection means for monitoring a hardware interrupt request signal and detecting a system idle when all the hardware interrupt request signals are not generated for a preset time, and a system idle detection means for responding to the detection of the system idle by the system idle detection means. Supply an interrupt signal indicating system idle to the interrupt input terminal of the CPU to cause the CPU sleep means to execute the process of issuing a clock stop signal generation instruction, and monitor the various hardware interrupt request signals, Wear interrupt required System event detection means for detecting the occurrence of a system event when one of the signals is generated, and the clock stop signal generation means for generating the clock stop signal in response to the detection of the system event occurrence by the system event detection means. To stop the C
Means for returning the PU from the clock stop permission state to the normal state, and the CPU sleep means is the CPU during the period from the generation of the interrupt signal indicating the system idle to the detection of the occurrence of the system event by the system event detection means. The third feature is that the clock stop signal generating means includes means for intermittently generating the clock stop signal so that the clock stop enable state and the normal state are alternately repeated.

In this computer system, C
In the sleep mode, the PU alternately repeats the clock stop enable state and the normal state at certain time intervals. In the clock stop permission state, all CPU instruction execution is stopped, but in the normal state, instruction execution can be restarted. Therefore, during the sleep mode, that is, during the period from the detection of the system idle to the detection of the occurrence of the system event, CP
Program execution by U is not completely stopped, CPU
Is able to execute programs intermittently. Therefore, as in a memory benchmark test, I
A program that does arithmetic processing without using / O
Even if the CPU accidentally shifts to the sleep mode due to the false detection of the idle state while the PU is executing, it is possible to prevent the occurrence of a situation in which no processing progresses after the program execution is suddenly stopped. Further, since the average operation speed of the CPU can be slowed down in the sleep mode, the power consumption of the CPU can be sufficiently reduced in the average sense even in this sleep control method.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a computer system according to an embodiment of the present invention. This computer system is a laptop or notebook type personal computer system,
CPU 11, system controller 12, main memory 13, BIOS ROM 14, and bus conversion circuit 15
Is equipped with.

The CPU 11 and the main memory 13 have three
It is connected to the CPU bus 100 including a 2-bit wide data bus. The CPU bus 100 is connected via a bus conversion circuit 15 to an ISA specification system bus 200 including a 16-bit wide data bus.

The system is further provided with an interrupt controller 16, a keyboard controller 17, a system timer 18, and various other I / O devices 19, which are connected to the system bus 200.

The CPU 11 is, for example, a microprocessor SL manufactured and sold by Intel Corporation of the United States.
An Enhanced Intel 486 is used. S
The LEnhanced Intel 486 is roughly classified into four types of clock models, 1x clock model, 1 / 2x clock model, 1 / 3x clock model, and 2x clock model. The 1 × clock model, the 1/2 × clock model, and the 1/3 × clock model are models with a built-in PLL, and the 2 × clock model is a model without a PLL. In this system, a high-performance processor with a built-in PLL, 1 × clock model, 1/2 × clock model, or 1/3 × clock model SL Enhan
ced Intel 486 is used.

Hereinafter, 1 × clock model SL Enh
A case where the advanced Intel 486 is used as the CPU 11 will be described as an example.

That is, the CPU 11 has the PLL circuit 111.
This PLL circuit 111 generates an internal clock CLK2 that is the same as or faster than the external clock CLK based on the external clock CLK. As shown in FIG. 2, the CPU 11 has three operating states with different power consumption, namely, a normal state (Normal State), a stop grant state (Stop Grant State), and a stop clock state (STOP Clock State).
Tate).

The normal state is a normal operation state of the CPU 11, and the instruction is executed in this normal state. This normal state has the highest power consumption, and its current consumption is about 700 mA.

The stop clock state consumes the least power, and the current consumption is about 50 μA. In this stop clock state, not only execution of instructions is stopped, but also external clock CLK and internal clock CLK2 are stopped.

The stop grant state is an operation state intermediate between the normal state and the stop clock state, and its current consumption is relatively small at about 20 to 50 mA. No instructions are executed in the stop grant state. Further, although both the external clock CLK and the internal clock CLK2 are in the running state, the CPU
The supply of the internal clock CLK2 to the internal logic is stopped. This stop grant state is external clock C
LK is a stoppable state, and when the external clock CLK is stopped in this stop grant state,
The CPU 11 shifts from the stop grant state to the stop clock state.

The transition between the normal state and the stop grant state can be performed at high speed by the stop clock (STPCLK) signal.

That is, in the normal state, CP
When the STPCLK signal supplied to U11 is enabled, that is, set to the active state, the CPU 11
After the instruction currently being executed is completed, the internal pipeline is completely emptied without executing the next instruction, and then the stop grant cycle is executed to shift from the normal state to the stop grant state. On the other hand, when the STPCLK signal is set to the disable state, that is, the inactive state in the stop grant state, C
The PU 11 shifts from the stop grant state to the normal state and restarts execution of the next instruction.

The transition from the stop grant state to the stop clock state is performed by the external clock CLK.
Instantly done by stopping. External clock CL to the CPU 11 in the stop clock state
When the supply of K is restarted, the CPU 11 shifts to the stop grant state after 1 ms. As described above, there is a problem that it takes time to recover from the stop clock state.

As described above, the stop grant state has much lower power than the normal state,
In addition, it has a feature that it can quickly return to the normal state, that is, the instruction execution state by the STPCLK signal. Therefore, in this system, the stop grant state is used as the CPU sleep mode instead of the stop clock state.

Further, the CPU 11 of FIG. 1 has the following system management function.

That is, the CPU 11 has a system management mode (SMM; System Ma) in addition to a real mode, a protect mode, a virtual 86 mode for executing an application program and a program such as an OS.
It has an operation mode for executing a system management program dedicated to system management or power management called a “management mode”.

The real mode is a mode in which a maximum 1 Mbyte memory space can be accessed, and the physical address is determined by the offset value from the base address represented by the segment register. The protect mode is a mode in which a maximum of 4 Gbytes of memory space can be accessed per task, and a linear address is determined using an address mapping table called a descriptor table. This linear addressless is finally converted into a physical address by paging. The virtual 86 mode is a mode for operating a program configured to operate in the real mode in the protect mode, and the program in the real mode is treated as one task in the protect mode.

The system management mode (SMM) is a pseudo-real mode, in which the descriptor table is not referenced and paging is not executed. System Management Interrupt (SMI)
rupt) is issued to the CPU 11, the operation mode of the CPU 11 is switched from the real mode, the protect mode or the virtual 86 mode to the SMM. In the SMM, a system management program dedicated to system management or power save control is executed.

The SMI is a kind of the non-maskable interrupt NMI, but it is the highest priority interrupt having a higher priority than the normal NMI and the maskable interrupt INTR. This SM
By issuing I, various SMI service routines prepared as a system management program can be started without depending on the application program being executed or the OS environment. In this computer system, in order to always realize the same sleep mode function without depending on the OS environment, CP is used by using this SMI.
U-sleep is controlled.

The system controller 12 is a gate array for controlling the memory and I / O in this system. Here, the SMI signal to the CPU 11 and the STP signal are provided.
Hardware is included to control the generation of the CLK signal.

The main memory 13 stores an operating system, an application program to be processed, user data created by the application program, and the like. SMRAM (System M
management RAM) 50 is the main memory 1
3 is an overlay that is mapped in the address space from 30000H to 3FFFFH.
It becomes accessible only when a signal is input to the CPU 11. Here, the address range to which the SMRAM is mapped is not fixed, and can be changed to any place in the 4 Gbyte space by a register called SMBASE. The SMBASE register can only be accessed during SMM. The initial value of the SMBASE register is
The address is 3000H.

When the CPU 11 shifts to SMM, C
PU status, that is, CPU when SMI is generated
11 registers and the like are saved in the SMRAM 50 in a stack format. In this SMRAM50, BIOSRO
The instruction for calling the system management program of M14 is stored. This instruction is an instruction that is first executed when the CPU 11 enters the SMM, and control is transferred to the system management program by executing this instruction.

The BIOS ROM 14 is a BIOS (Bas
ic I / O System) for storing
It is composed of a flash memory so that the program can be rewritten. The BIOS is configured to operate in real mode. This BIOS has an IRT routine executed at system boot and various I / O routines.
A device driver for controlling the O device and a system management program are included. The system management program is a program executed in SMM, and includes an SMI program including a global stanbus SMI routine and a software SMI routine,
It includes an SMI handler for determining the SMI routine to be executed.

Each of the global standby SMI routine and the software SMI routine includes a CPU.
A sleep control routine for setting 11 to sleep mode is included. In addition, global standby S
The MI routine also includes an auto power off routine that powers off the system after saving the system status.

The SMI handler is a program in the BIOS that is first called by the CPU 11 when an SMI occurs, whereby the cause of the SMI is checked and the SMI routine corresponding to the cause is executed. .

The bus conversion circuit 15 performs bus width conversion between the 32-bit data bus of the CPU bus 100 and the 16-bit data bus of the system bus 200.

The interrupt controller 16 includes interrupt request signals IRQ0 to IRQ from the keyboard controller 17, system timer 18, and other I / O devices 19.
The RQ 15 is received, and the generation of the interrupt signal INTR to the CPU 11 is controlled according to the priority of the interrupt request signal. In this case, the status information indicating the generated interrupt request signal is held in the register in the interrupt controller 16. The interrupt signal INTR is generated when any one of the hardware interrupt request signals (IRQ0 to IRQ15) is generated.

Here, IRQ0 is a timer interrupt request signal generated from the system timer 18 in a unit of 55 msec, for example. The generation interval of IRQ0 can be set programmable, and depending on the OS environment, it may be set to a value shorter than 55 ms for fast task switching. IRQ1 is a keyboard interrupt signal generated from the keyboard controller 17 at the time of key input. The interrupt signal from the keyboard controller 17 also includes an interrupt signal IRQ12 generated when the mouse is operated. IRQ2 to IRQ11, IRQ13 to IRQ15
Is an interrupt request signal from various other I / O devices 19 in the system (eg, floppy disk controller, hard disk controller, serial port, SCSI port, etc.).

Next, a hardware configuration provided in the system controller 12 for controlling generation of SMI and STPCLK will be described.

As shown in the figure, the system controller 12 includes an I / O register group 121, a global standby timer 122, a software SMI timer 123, a system event detection circuit 124, and a global standby SM.
I generation circuit 125, software SMI generation circuit 12
6. SMI generation circuit 127 and OR circuit 12 for other factors
8, 130, and a stop clock control circuit 129,
And an NMI generating circuit 131.

The I / O register group 121 is a group of registers readable / writable by the CPU 11, in which SMI status information indicating the cause of SMI is set by the hardware in the controller 12 and global The CPU 11 sets a standby timeout value, a software SMI warning timeout count value, and the like. The global standby timeout value is sent to the global standby timer 122, and the software SMI warning timeout count value is sent to the software SMI timer 123. Further, a stop clock command for causing the stop clock control circuit 129 to generate STPCLK is set in the I / O register group 121 by the CPU 11. This stop clock command is sent to the stop clock control circuit 129.

The global standby timer 122 is an up-counter which counts in units of 4 seconds, for example, and the count operation is started by setting the global standby timeout value in the register group 121. When the system event detection circuit 124 generates a system event detection signal, the count value of the global standby timer 122 is reset, and the count operation is restarted from the count value "0". When the count value and the global standby timeout value match, the global standby timeout signal is generated from the global standby timer 122. This global standby timeout signal indicates that no system event has occurred during the time specified by the global standby timeout value. This global standby time-out signal is a global standby SMI.
Generation circuit 125 is caused to generate a global standby SMI.

The software SMI timer 123 is, for example, an up counter that counts in units of 1 msec, and the count operation is started by setting the software SMI warning time-out value in the register group 121. When the system event detection signal is generated from the system event detection circuit 124, the count value of the software SMI timer 123 is reset, and the count operation is restarted from the count value "0". When the count value and the software SMI warning time-out value match, the software SMI warning time-out signal is generated from the software SMI timer 123. The software SMI warning time-out signal causes the software SMI generation circuit 126 to generate a software SMI.

The system event detection circuit 124 monitors the hardware interrupt signal and NMI and detects the occurrence of a system event. When the occurrence of a system event is detected, the system event detection circuit 124 generates a system event detection signal.

Here, the system event is a hardware interrupt request signal excluding a timer interrupt (IRQ0),
That is, IRQ1 to IRQ15 and NMI.

The system event detection circuit 124 uses an IR signal to reduce the number of input pins of the system controller 12.
Q1 to IRQ15 are not actually monitored and instead I
Monitor NTR and IRQ0. In this case, the system event detection circuit 124, if IRQ0 is not in the active state when INTR occurs, IRQ1 to IRQ1.
It is determined that any one of 5 has occurred (system event). In this case, in reality, even if IRQ0 is in the active state, it is considered that a system event has occurred when INTR occurs twice within the period of the single active state.

That is, as shown in FIG. 3A, when two INTRs are generated within the period in which IRQ0 is maintained active (H), the first INT is generated.
When a TR occurs, it is not considered as a system event occurrence, but when a second INTR occurs, it is considered as a system event occurrence. On the other hand, as shown in FIG. 3 (B), when IRQ0 returns to inactive (L) in the middle, even if both IRQ0 are active (H) during two consecutive INTR occurrences, the system Not considered an event occurrence.

Since IRQ0 to 15 are edge trigger signals, only the edge when the inactive state is changed to the active state is effective, and the period during which it is maintained in the active state. Because has no meaning.

That is, as shown in FIG. 3 (C), once IRQ0 is generated, it remains for a fixed period (27 ms).
To some degree) Active (H) is maintained. Therefore, IR
Q0 does not return to inactive (L) immediately after the timer processing ends, but is maintained in the active state (H). Therefore, IRQ0 is in active state (H)
The first IN generated during the period maintained at
TR is due to IRQ0, but INTR generated for the second time is due to factors other than IRQ0 such as IRQ1.

For the above reason, the system event detection circuit 124 detects the system event as follows.
There are the following two cases. 21) When IRQ0 is not in the active state when INTR occurs.

2) Even if IRQ0 is in the active state, INT is set within the period of one active state.
When R occurs twice.

Global standby SMI generation circuit 12
5 is a global standby SM indicating a system idle when no system event is generated for the time specified by the global standby timeout value, that is, when the global standby timeout signal is generated from the global standby timer 122.
Generate I. The global standby SMI is supplied to the CPU 11 via the OR circuit 128. When the global standby time-out signal is generated, SMI status information indicating the occurrence of global standby SMI is set in the register group 12.

The software SMI generating circuit 126 receives the software SM from the software SMI timer 123.
A software SMI is generated in response to the I warning time-out signal. This software SMI is OR
It is supplied to the CPU 11 via the circuit 128. When the software SMI warning time-out signal is generated, SMI status information indicating the generation of the software SMI is set in the register group 121.

The SMI generating circuit 127 for other factors is responsible for the global standby time-out and the software SM.
An SMI (external input SMI, SMI due to I / O trap function, SMI due to local standby timeout, SMI due to suspend / resume button signal from the power supply) is generated due to factors other than the I warning timeout.

The stop clock control circuit 129 uses the CP
When a stop clock generation command is set in the register group 121 by the U11, a stop clock signal (STPCLK) for shifting the CPU 11 to the stop grant state is generated. This STPCLK is O
When the stop break signal is supplied from the R circuit 130, its generation is stopped. The stop break signal is C
It is generated to return PU11 from the stop grant state to the normal state. The cause of the stop break signal is all SMI and IRQ0.
~ INTR generated by IRQ15 and NMI.

The NMI generating circuit 131 generates an NMI in response to an NMI generating factor such as an I / O channel check. This NMI is supplied to the CPU 11, the system event detection circuit 124, and the OR circuit 130.

In the system controller 12, the system event detection circuit 124 monitors various hardware interrupt request signals in the system, and when all the hardware interrupt request signals other than the timer interrupt are not generated for a predetermined time, the system idle is performed. Is detected, which causes a global standby SMI for shifting the CPU 11 to the sleep mode.

When the stop clock command is issued from the CPU 11, the stop clock control circuit 129 causes the S
TPCLK is generated and the CPU 11 is set to the stop grant state. When a stop break factor such as a hardware interrupt occurs in this state, the stop clock control circuit 129 causes the CPU 11 to execute STPCLK in order to execute the process corresponding to the hardware interrupt.
Is stopped and the CPU 11 is returned to the normal state.

In the system controller 12, the stop break software SM is arranged so that the stop grant state and the normal state are alternately repeated at a certain time interval in the sleep mode.
Alternately, I and the software SMI for resleep are generated. This sets a time-out time for stop break in the software SMI timer 123 before generating the STPCLK signal, and sets a time-out time for re-sleep when the stop break is generated by the software SMI for the stop break. It is realized by setting the timer 123.

In this case, if another stop break factor due to a hardware interrupt request signal such as a keyboard interrupt occurs before the software SMI as a stop break factor is generated, that stop break factor is not waited and A stop break is triggered first by the hardware interrupt request signal. This allows
The keyboard controller 17 or other I / O device 19 requesting the service can be quickly provided with the service.

If the cause of the stop break is a timer interrupt, re-sleep processing for returning the CPU 11 to the stop grant state again is executed.

The operation procedure of CPU sleep control using SMI and STPCLK will be described below.

First, referring to FIGS. 4 and 5, the CPU
The operation of the CPU 11 when the SMI is issued to 11 will be described.

When the SMI is input to the CPU 11, the CP
The U11 first maps the SMRAM 50 into the address space from the address 30000H to 3FFFFH of the main memory 13 (step S1). This allows
Address 30000H to 3FFF of main memory 13
The FH becomes inaccessible and the SMRAM 50 becomes accessible instead.

The SMRAM 50 is provided with a CPU state storage area and an SMI handler work area,
Also, a jump code that specifies the SMI handler of the BIOS ROM 14 as an interrupt destination is set.

Next, the CPU 11 saves the contents (CPU status) of various registers of the CPU 11 when the SMI is input to the CPU state storage area of the SMRAM 50 in a stack format (step S2). And
CPU11 is SMM start address 38000H
Code, that is, address 38000 of SMRAM50
The jump code set in H is fetched, and the SMI handler of the BIOS ROM 14 designated by the jump code is executed (step S3). The processes of steps S1 to S3 up to this point are executed by the microprogram of the CPU 11.

The SMI handler called by the execution of the jump code checks the SMI occurrence factor to determine what causes the SMI occurrence (step S4). In this processing, the SMI set in the register group 121 of the system controller 12 is set.
Status information is referenced. For example, in the case of SMI due to global standby timeout, the SMI handler requests execution of the BIOS SMI service routine corresponding to the SMI, that is, the global standby SMI routine (step S5). In addition, SMI due to software SMI warning timeout
If so, the SMI handler requests execution of the software SMI routine (step S5). Global Standby SMI Routine and Software SM
Each I routine includes a CPU sleep control routine.

As described above, the CPU sleep control routine causes the CPU 11 to execute the SM without any intervention of the OS and the BIOS.
It can be activated by simply supplying the I signal.

Next, referring to FIGS. 6 and 7, the CPU sleep control operation when the CPU 11 is maintained in the stop grant state during the sleep mode will be described.

When the system is booting, the detection time for detecting the system idle is set in the global standby timer 122 as the global standby timeout value. This global standby time-out value is set immediately by the CPU 11 when the system is idle.
Is set to a relatively short time, preferably any one of 4 seconds, 8 seconds, ... The initial setting of this timer is
It is executed by the IRT routine.

After the system is started, if no hardware interrupt request signal other than the timer interrupt is generated for 4 seconds, the global standby timer 122 generates a global standby timeout signal (step S11). In response to the global standby time-out signal, the global standby SMI generating circuit 125 generates the global standby SMI signal (step S12). At this time, the register group 121 has
SMI status information indicating that an SMI due to global standby timeout has occurred is set.

The CPU 11 responds to the SMI signal by the SM
M is entered and a global standby SMI routine is executed (step S13). Global standby SMI
The routine resets the global standby timeout value to the time for auto power off, for example, 30 minutes (or 1 hour) (step S14), and then STP.
A stop clock command instructing the generation of CLK is set in the register group 121.

The stop clock control circuit 129 generates STPCLK in response to the stop clock command (step S15). In response to this, the CPU 11 is set to the sleep mode, that is, the stop grant state. As a result, the instruction execution of the CPU 11 is stopped, and its execution is stopped in the middle of the global standby SMI routine.

When a stop break factor is generated in the sleep mode (step S16), it is used as a stop break signal by the stop clock control circuit 129.
Sent to. In response to this stop break factor signal, the stop clock control circuit 129 causes the STPCLK
Is stopped (step S17). As a result, the CPU1
1 shifts from stop grant state to normal state and exits sleep mode. Then, the global standby SMI routine is started from the next instruction.

The global standby SMI routine is
First, the cause of the stop break is checked to see if the cause of the stop break is a system event (a hardware interrupt request signal other than a timer interrupt) or a timer interrupt (step S18). This factor check can be performed by referring to the interrupt status register of the interrupt controller 16.

If the cause of the stop break is the occurrence of a system event, the global standby SMI
The routine sets the global standby timeout value to 4
Return to seconds (step S19), then resume (RS
M) The instruction is executed (step S20). This allows
Returning to the OS or application program interrupted by the SMI, the CPU 11 returns from the sleep mode to the normal operation mode. And there,
The service for the interrupt that caused the system event is executed.

During SMM, an interrupt (I
(Including RQ0) is masked by CLI. The NMI is also masked.

On the other hand, when the cause of the stop break is the timer interrupt (IRQ0), the global standby SMI routine executes the re-sleep software SMI.
Software SMI to generate
The time T2 is set in the timer 123 (step S2
1) After that, a resume (RSM) instruction is executed (step S20). As a result, the OS or application program interrupted by the SMI is once returned and the timer interrupt by the IRQ0 is processed therein, but immediately thereafter, the CPU 11 shifts to the sleep mode again by the re-sleep software SMI.

FIG. 7 shows the procedure of the resleep processing when the timer interrupt occurs as a break factor.

As shown in FIG. 7, step S2
When the time T2 set in the software SMI timer 123 by 1 has elapsed, a software SMI warning time-out signal is generated from the software SMI timer 123 (step S22). In response to the software SMI warning time-out signal, the software SMI generation circuit 126 generates a software SMI signal for resleep (step S2).
3). At this time, the software S is stored in the register group 121.
SMI status information indicating that SMI due to MI warning timeout has occurred is set.

The CPU 11 responds to the SMI signal by the SM
M is entered and the software SMI routine is executed (step S24). When the software SMI routine confirms that the software SMI is for resleep, it sets a stop clock command instructing the generation of STPCLK in the register group 121. The stop clock control circuit 129 generates STPCLK in response to the stop clock command (step S2).
5). In response to this, the CPU 11 is reset to the sleep mode, that is, the stop grant state.

FIG. 8 shows a timing chart from the time when the CPU 11 shifts to the sleep mode due to the SMI caused by the global standby timeout to the time when the CPU 11 returns from the sleep mode to the normal operation mode due to a system event such as a keyboard interrupt.

In FIG. 8, t1 indicates the timing of occurrence of the global standby timeout, which occurs when the CPU 11 does not generate a system event for 4 seconds during the normal operation mode. This timing t
1, the CPU 11 enters the SMM, and the program that is being executed at that time receives the global standby S
Control is transferred to the MI routine. t2 is the generation timing of the STPCLK signal, and at this timing t2, C
PU11 enters the stop grant state. t3 is
Indicates the timing of occurrence of a system event such as a keyboard interrupt. At this timing t3, the CPU 11
Returns from the stop grant state to the normal state. t4 is the execution timing of the RSM instruction,
By executing this RSM instruction, the global standby S
Control returns from the MI routine to the interrupt source program. Interrupt processing such as keyboard interruption is performed there.

FIG. 9 shows a timing chart in the case where the resleep processing is executed due to the occurrence of the stop break due to the timer interrupt.

In FIG. 9, t1 indicates the timing of occurrence of global standby timeout, which occurs when the system event does not occur for 4 seconds in the CPU 11 in the normal operation mode. This timing t
1, the CPU 11 enters the SMM, and the program that is being executed at that time receives the global standby S
Control is transferred to the MI routine. t2 is the generation timing of the STPCLK signal, and at this timing t2, C
PU11 enters the stop grant state. t3 is
Indicates the timing of timer interrupt generation. At this timing t3, the CPU 11 is temporarily stopped and returns from the stop grant state to the normal state. t4 shows the execution timing of the preparation process for generating the software SMI for resleep after a fixed time. t5 is the execution timing of the RSM instruction, and the control once returns from the global standby SMI routine to the interrupt source program by the execution of this RSM instruction. Timer interrupt processing is performed here.
t6 indicates the timing of generation of the software SMI for resleep. At this timing t6, the CPU1
1 enters SMM again and executes the software SMI routine. t7 is the generation timing of the STPCLK signal, and at this timing t7, the CPU 11 enters the stop grant state. t8 indicates the timing of occurrence of a system event such as a keyboard interrupt. At this timing t8, the CPU 11 returns from the stop grant state to the normal state. This time,
Re-sleep is not set. At t9, the execution timing of the RSM instruction, the execution of this RSM instruction returns control from the software SMI routine to the interrupt source program, and the CPU 11 returns from the sleep mode to the normal operation mode. Keyboard interrupt processing is performed here.

As described above, in this sleep control system, the CPU 11 is immediately returned from the sleep mode when the cause of the stop break is a system event, but in the case of a timer interrupt, the sleep mode is changed by the resleep processing. Continued.

In addition to the above-mentioned system event and timer interrupt, an SMI caused by a global standby timeout for auto power off may be generated as a cause of a stop break.

That is, when the sleep mode of the CPU 11 is continuously maintained for 30 minutes, the SMI due to the global standby timeout is generated as a stop break factor.

In this case, the CPU 11 executes the global standby SMI routine corresponding to the global standby SMI signal after exiting the sleep mode by the processing of steps 19 and 20 in FIG. When the global standby SMI routine confirms that the global standby timeout value set in the regirator group 121 is 30 minutes, it calls the auto power off routine. The auto power-off routine saves the system status necessary to restore the system to the state just before the system was powered off at the time of power-on in the main memory 13, and then almost everything else in the system except the main memory 13. Power off the unit.

As described above, in sleep control in this computer system, various hardware interrupt request signals IRQ0 to IRQ1 in the system are used.
5, NMI is monitored and system idle is detected when all other interrupt request signals except timer interrupt (IRQ0) are not generated for a predetermined time.
11 is shifted to the sleep mode. Therefore, the CPU
The number of triggers for switching 11 to sleep mode has increased,
The CPU 11 can be shifted to the sleep mode not only when the application program waits for keyboard input but also when the application program has completed the operation of an I / O device other than the keyboard. . Therefore, the CPU
It is possible to prevent the situation where the CPU 11 is maintained in the operating state even though the CPU 11 is idle.
The power consumption of 1 can be sufficiently reduced.

A hardware interrupt request signal is used to detect the system idle. The hardware interrupt request signals RQ0 to IRQ15 are physical signals generated from various I / O devices in the system, and the BIOS is not used for detecting them. Furthermore, the SMI routine including the sleep sequence is executed by the CPU.
It can be activated only by supplying the SMI signal to 11.
The OS and the BIOS have no relation to the startup process of the SMI routine.

Therefore, system idle detection and sleep control can be realized at the hardware level, and the same sleep mode function can always be provided regardless of the OS environment. Further, even when the application program for directly controlling the hardware is executed without going through the BIOS, it is possible to detect the system idle and control the CPU sleep.

Further, in the sleep mode, the CPU
11 is maintained in the stop grant state. In this stop grant state, the execution of all instructions is stopped, so the CP does not stop without stopping the external clock.
The power consumption of U can be reduced. Therefore, the CPU can be returned from the sleep mode without dynamically switching the external clock, and the high-performance CPU with the built-in PLL can be returned from the sleep mode at high speed.

The operation when the stop grant state and the normal state are alternately repeated at a certain time interval in the sleep mode will be described below. In this sleep mode control method, the CPU
This is a method in which the operation speed is slowed down instead of completely stopping 11. The reason for adopting this method is as follows.

That is, in this system, the CPU responds to the global standby timeout of 4 seconds.
11 is set to the sleep mode, and the sleep mode is released when a system event occurs. Therefore, for example, I
A program that does arithmetic processing without using / O
There is a possibility that the CPU 11 is set to the sleep mode by mistake when the PU 11 is executing. In this case, if the operation of the CPU 11 is completely stopped, the program to be executed may be suddenly stopped and the process may not proceed after that even though it is not waiting for the event. If the user cancels the sleep mode by performing a key input or the like, the user can get out of the state, but without the key input, the user cannot get out of the state at all.

Therefore, in order to prevent the occurrence of such a situation, it is preferable to operate the CPU 11 at a low speed rather than completely stopping the CPU 11 in the sleep mode.

In this system, as will be described below, the C in the sleep mode is controlled by the duty control of the stop grant state and the normal state.
The operation speed of the PU 11 is reduced.

That is, as shown in FIG.
If no hardware interrupt request signal other than a timer interrupt is generated for 4 seconds after the system is started, the global standby timer 122 generates a global standby timeout signal (step S).
31). In response to the global standby time-out signal, the global standby SMI generating circuit 125
Generates a global standby SMI signal (step S32). At this time, SMI status information indicating that an SMI has occurred due to the global standby timeout is set in the register group 121.

The CPU 11 responds to the SMI signal by the SM
M is entered and the global standby SMI routine is executed (step S33). Global standby SMI
The routine resets the global standby timeout value to a time for auto power-off, for example, 30 minutes (step S34), and then causes the software SMI timer 123 to generate the stop break software SMI after a predetermined time T1. (For example, 2m
Seconds) is set (step S35). After that, the global standby SMI routine sends a stop clock command instructing the generation of STPCLK to the register group 12
Set to 1.

The stop clock control circuit 129 generates STPCLK in response to the stop clock command (step S36). In response to this, the CPU 11 is set to the sleep mode, that is, the stop grant state. As a result, the instruction execution of the CPU 11 is stopped, and its execution is stopped in the middle of the global standby SMI routine.

When the time T1 elapses after shifting to the sleep mode, a software SMI warning time-out signal for stop break is generated from the software SMI timer 123 (step S37). In response to this software SMI warning timeout signal,
The software SMI generation circuit 126 generates a software SMI for stop break (step S3).
8). The software SMI is sent as a stop break signal to the stop clock control circuit 129 and the CPU 11.

The stop clock control circuit 129 uses the ST
PCLK is stopped (step S39). This allows
The CPU 11 shifts from the stop grant state to the normal state, and execution of the global standby SMI routine starts from the next instruction.

The global standby SMI routine is
First, in order to generate the re-sleep software SMI after a predetermined time, the software SMI timer 123 is set to time T2 (for example, 1 msec) (step S4).
0), after which a resume (RSM) instruction is executed (step S41). This returns to the OS or application program interrupted by the SMI.

After that, the CPU 11 enters the SMM in order to perform the processing corresponding to the software SMI generated in step S38, and executes the software SMI routine (step S42). However, since the software SMI generated in step S38 is the dummy SMI generated for the stop break, the software SMI routine called by this executes the RSM instruction without performing any processing, and immediately the dummy SMI is executed. The process returns to the OS or application program interrupted by the SMI (step S43).

When the time T2 elapses after the CPU 11 shifts to the normal state, the software SMI warning time-out signal is generated from the software SMI timer 123 (step S44). In response to the software SMI warning time-out signal, the software SMI generation circuit 126 generates a software SMI signal for resleep (step S4).
5). At this time, the software S is stored in the register group 121.
SMI status information indicating that SMI due to MI warning timeout has occurred is set.

The CPU 11 receives the SM signal in response to the SMI signal.
M is entered and the software SMI routine is executed (step S46). When the software SMI routine confirms that the software SMI is for re-sleep, the software SMI timer 123 is set to time T1 in order to generate the stop break software SMI again after a fixed time (step S47).
After this, the software SMI routine returns STPCLK.
A stop clock command for instructing the generation of is set in the register group 121.

The stop clock control circuit 129 generates STPCLK in response to the stop clock command (step S48). In response to this, the CPU 11 is set to the sleep mode, that is, the stop grant state. As a result, the instruction execution of the CPU 11 is stopped, and the execution is stopped in the middle of the software SMI routine.

In this way, the stop grant state and the normal state are alternately repeated in the sleep mode.

Then, for example, when a stop break occurs due to a factor other than the software SMI in the stop grant state, the following processing is performed.

That is, when a stop break occurs due to a factor other than the software SMI (step S4
9), which is sent to the stop clock control circuit 129 as a stop break signal. In response to this stop break factor signal, the stop clock control circuit 129
Stops STPCLK (step S50). As a result, the CPU 11 shifts from the stop grant state to the normal state. And software SM
The I routine is started from the next instruction.

The software SMI routine first checks the cause of the stop break and determines whether the cause of the stop break is a system event (a hardware interrupt request signal other than a timer interrupt) or a timer interrupt (step S51). This factor check can be performed by referring to the interrupt status register of the interrupt controller 16.

When the cause of the stop break is the occurrence of a system event, the software SMI routine returns the global standby timeout value to 4 seconds (step S52), and then executes the resume (RSM) instruction (step S53). . This returns to the OS or application program interrupted by the SMI, and the CPU 11 returns from the sleep mode to the normal operation mode. Then, the service for the interrupt that caused the system event is executed there.

On the other hand, when the cause of the stop break is the timer interrupt (IRQ0), the software SMI
The routine uses the software SMI timer 1 to generate the software SMI for resleep after a certain time.
The time T2 is set to 23 (step S54), and then the resume (RSM) instruction is executed. This allows S
Although the OS or application program interrupted by MI is once returned, the CPU 11 immediately shifts to the stop grant state by the resleep software SMI. As a result, the sleep mode is continued.

FIG. 11 shows the timing when the CPU 11 shifts to the sleep mode in which the stop grant and the normal state sleep mode are alternately repeated and then returns from the sleep mode to the normal operation mode due to a system event such as a keyboard interrupt. A chart is shown.

In FIG. 11, t1 indicates the timing of global standby time-out which occurs when the CPU 11 does not generate a system event for 4 seconds during the normal operation mode. At this timing t1, the CPU 11 enters the SMM, and control is transferred from the program that is being executed at that time to the global standby SMI routine. t2 represents the execution timing of the preparation process for generating the stop break software SMI after a certain period of time. t3 is STP
This is the generation timing of the CLK signal, and this timing t
At 3, the CPU 11 enters the stop grant state. t4 is software SMI for stop break
The occurrence timing of is shown. The software SMI generated at the timing t4 causes a stop break and C
PU11 returns from the stop grant state to the normal state. t5 shows the execution timing of the preparation process for generating the software SMI for resleep after a fixed time. t6 is the execution timing of the RSM instruction, and the execution of this RSM instruction returns control from the global standby SMI routine to the interrupt source program.

At t7, the transition timing to the SMM processing corresponding to the stop break software SMI (dummy SMI) generated at the timing t4 is given. t8
Is the RSM in the SMM process corresponding to the dummy SMI.
This is the execution timing of the instruction, and at this timing t8, the control returns to the interrupt source program. t9 indicates the generation timing of the software SMI for resleep. At this timing t6, the CPU 11 executes S again.
Enter the MM and execute the software SMI routine.

TA indicates the timing at which the timer interrupt is generated. At this timing tA, the CPU 11 is temporarily stopped and returns from the stop grant state to the normal state. tB indicates the timing of occurrence of a system event such as a keyboard interrupt. At this timing tB, the CPU 11 returns from the stop grant state to the normal state. tc
Is the execution timing of the RSM instruction, the execution of this RSM instruction returns control from the software SMI routine to the interrupt source program, and the CPU 11 returns from the sleep mode to the normal operation mode.

As described above, in this sleep control system, the CPU 11 alternately repeats the stop grant state and the normal state at a certain time interval in the sleep mode. In the stop grant state, all instruction execution of the CPU 11 is stopped, but in the normal state, instruction execution can be restarted. Therefore, during the sleep mode, that is, during the period from the detection of the system idle to the detection of the occurrence of the system event, the program execution by the CPU 11 is not completely stopped and the CPU 11 intermittently executes the program. Is possible. Therefore, it is possible to prevent a situation in which a program such as a Benmark test that does not wait for I / O is suddenly stopped even if the CPU 11 is erroneously shifted to the sleep mode due to a false detection of system idle. Further, also in this method, the average operation speed of the CPU 11 can be slowed in the sleep mode, so that the power consumption of the CPU 11 can be sufficiently reduced in the average sense.

Further, if another stop break factor due to a hardware interrupt request signal such as a keyboard interrupt occurs before the software SMI as a stop break factor occurs, the stop break due to the hardware interrupt request signal is generated. Is triggered first. As a result, the keyboard controller 17 or the other I / O device 19 requesting the service can be quickly provided with the service.

Next, referring to FIGS. 12 to 14, the global standby SMI routine and the software SMI will be described.
The processing procedure of each routine will be described by taking a specific case as an example.

FIG. 12 shows a flowchart of each of the global standby SMI routine and the software SMI routine when the stop grant state and the normal state are alternately repeated at a certain time interval in the sleep mode.

When no hardware interrupt request signal is generated except the timer interrupt for the time of 4 seconds, the global standby SMI signal is generated and the global standby SMI routine is executed. The global standby SMI routine first sets the global standby timeout value to the time for auto power off, eg 3
It is reset to 0 minutes (step S61), and thereafter, in order to generate the software SMI for stop break after a predetermined time, the software SMI timer 123 is set to the time T.
1 is set (step S62). After that, the global standby SMI routine instructs the system controller 12 to generate STPCLK (step S6).
3).

As a result, the STPCLK is generated, and the CPU 11 is set to the stop grant state until the time T1 elapses thereafter. The execution of the global standby SMI routine is stopped when step S63 is completed.

When time T1 elapses after shifting to the sleep mode, a stop break software SMI signal is generated. As a result, the CPU 11 shifts from the stop grant state to the normal state, and the global standby SMI routine is started from the next instruction.

The global standby SMI routine is
First, in order to generate the re-sleep software SMI after a fixed time, the time T2 is set in the software SMI timer 123 (step S64), and then the resume (RSM) instruction is executed (step S65). This returns to the OS or application program interrupted by the SMI.

After that, the CPU 11 executes the SM to execute the processing corresponding to the stop break software SMI.
Enter M and execute the software SMI routine.

In the software SMI routine, the software SMI generated in the sleep mode is used as the dummy SMI.
If it is confirmed that it is MI, R is executed without any processing.
The SM command is executed and immediately returns to the OS or application program interrupted by the dummy SMI (steps S71, 75).

When the time T2 elapses after the CPU 11 shifts to the normal state, the software SMI signal for resleep is generated, and the CPU 11 executes the software SMI routine. When the software SMI routine confirms that the software SMI is for resleep (step S71), the software SMI timer 123 is set to the time T1 to generate the stop break software SMI again after a certain time (step S71). S72). After this, the software SMI routine sends STP to the system controller 12.
The generation of CLK is instructed (step S73).

As a result, the STPCLK is generated and the CPU 11 is set to the stop grant state during the period until the time T1 elapses. Software SM
The execution of the I routine is stopped when step S73 is completed.

When time T1 elapses after shifting to the sleep mode, a stop break software SMI signal is generated. As a result, the CPU 11 shifts from the stop grant state to the normal state, and the software SMI routine is started from the next instruction.

First, the software SMI routine causes the software SMI timer 123 to set the time T2 in order to generate the re-sleep software SMI after a predetermined time.
(Step S74), and then resume (R
SM) command is executed (step S75). This returns to the OS or application program interrupted by the SMI.

After that, the CPU 11 executes the SM to execute the processing corresponding to the stop break software SMI.
Enter M and execute the software SMI routine.

In the software SMI routine, the software SMI generated in the sleep mode is used as the dummy SMI.
When it is confirmed that it is MI, RS is executed without any processing.
The M instruction is executed and immediately returns to the OS or application program interrupted by the dummy SMI (steps S71 and 75).

In this way, the sleep mode is continued by repeatedly executing the software SMI routine.

FIG. 13 shows a software SMI routine in the case where a system event such as a keyboard interrupt occurs before the software SMI for resleep is generated while the CPU 11 is set to the normal state in the sleep mode. Processing is shown.

If a keyboard interrupt occurs before the time T2 elapses after the CPU 11 returns to the normal state, the count value of the software SMI timer 123 is temporarily reset by the system event detection signal. Therefore, in this case, the software SMI is generated when the time (T2 + α), which is the sum of the time α and the time T2 from when the CPU 11 returns to the normal state to when the keyboard interrupt occurs.

The software SMI routine takes time T2
After confirming that it is a software SMI caused by a system event from the fact that a software SMI is generated after a longer time, the software SMI timer for resleep is not set and the global standby timeout value is set to 4 seconds. Return (step S8
1) After that, a resume (RSM) instruction is executed (step S82).

FIG. 14 shows the processing of the global standby SMI routine when a system event such as a keyboard interrupt occurs before the time T1 elapses after the CPU 11 shifts to the stop grant state due to the global standby timeout. ing.

As described above, if no hardware interrupt request signal other than the timer interrupt is generated for the time of 4 seconds, the global standby SMI signal is generated and the global standby SMI routine is executed.
The global standby SMI routine first resets the global standby timeout value to the time for auto power off, for example, 30 minutes (step S9).
1), then stop break software SMI
Software SMI to generate
The time T1 is set in the timer 123 (step S9)
2). After that, the global standby SMI routine instructs the system controller 12 to generate STPCLK (step S93).

As a result, the STPCLK is generated, and the CPU 11 is set to the stop grant state during the period until the time T1 elapses from that. The execution of the global standby SMI routine is stopped when step S93 is completed.

In this state, if a keyboard interrupt occurs before the time T1 elapses (here, T1-β) after shifting to the sleep mode, it causes a stop break, and the CPU 11 shifts from the stop grant state to the normal state. Transition to state. Then, the global standby SMI routine is started from the next instruction.

The global standby SMI routine is
If it is confirmed that the cause of the stop break is a system event based on the fact that the stop break occurs before the time T1 has elapsed after the sleep mode, the global standby timeout value is returned to 4 seconds (step S94), After that, a resume (RSM) instruction is executed (step S95).

Next, referring to FIG. 15, an actual flowchart of the sleep control routine provided in the global standby SMI routine will be described.

The global standby SMI routine is
When the execution of the routine is requested, it is first checked whether the global standby timeout value set in the register group 121 is a sleep value (4 seconds) or an auto-off value (30 minutes) (step S101). If the value for auto-off (30 minutes) is set, the global standby SMI routine calls the auto-off routine to power off the system.

On the other hand, when the sleep value (4 seconds) is set, the global standby SMI routine first changes the global standby timeout value, and the global standby timer 122 sets the auto-off value (30). Minute) is set (step S102).
After that, the global standby SMI routine reads the time (t1) at that time designated by the counter built in the system timer 18, and then causes the software SMI timer 123 to generate the stop break software SMI after a predetermined time. Is set (step S103). Thereafter, the global standby SMI routine sets a stop clock command instructing the generation of STPCLK in the register group 121 (step S104).

Next, the global standby SMI routine reads the time (t2) at that time designated by the counter incorporated in the system timer 18, detects whether t2-t1 <T1 is established, and responds to the detection result. Stop break factor is software for stop break S
It is determined whether it is other than MI (step S10).
5).

When the expression {t2-t1 <T1} is not satisfied, it means that the stop break has not occurred before the time T1 has passed, that is, the cause of the stop break is the stop break software SMI. On the other hand, the expression {t2-t1 <T1} is satisfied when the stop break occurs within the time T1, that is, the cause of the stop break is the software SMI for stop break.
It means that it is due to factors other than.

If the stop break factor is caused by a factor other than the stop break software SMI, the global standby SMI routine checks whether or not the factor is a timer interrupt (step S1).
06). This factor check process can be realized by referring to the register of the interrupt controller 16, for example.

When the cause of the stop break is not the timer interrupt, the global standby SMI routine determines that a system event, that is, IRQ1 to 15 or NMI has occurred, and returns the global standby timeout value to 4 seconds (step S108). ), And then the resume (RSM) instruction is executed (step S1).
09).

On the other hand, if the cause of the stop break is the stop break software SMI or the timer interrupt, the global standby SMI routine
After reading the time (t1 ') specified by the counter built into the system timer 18 and setting it in a predetermined register, the re-sleep software SMI is set.
To generate the timer after a certain time, the time T2 is set in the software SMI timer 123 (step S10).
7) After that, a resume (RSM) instruction is executed (step S109). In step S107, a process of setting a flag indicating that the stop break software SMI (dummy SMI) is generated in the SMI routine in the memory 13 or the register in the system controller 12 is also performed.

Next, referring to FIG. 16, software S
An actual flowchart of the sleep control routine provided in the MI routine will be described.

When the software SMI signal is requested to be executed by the software SMI signal being supplied to the CPU 11, the software SMI routine determines whether or not the SMI signal is generated in the SMI routine. It is determined whether the signal is a dummy SMI signal (step S201). This determination can be realized by referring to the flag set in the memory 13 or the register in the system controller 12 in step S201.

After this, the software SMI routine
The time (t2 ') at that time designated by the counter incorporated in the system timer 18 is read, and it is detected whether or not t2'-t1'<T2 is established, and the generated SMI signal is detected according to the detection result. It is determined whether the software SMI is caused by the occurrence of a system event (step S
202).

The expression {t2'-t1 '<T2} is satisfied as follows.
It means that the generated SMI signal is due to the occurrence of a system event. On the other hand, the expression {t2'-t1 '
The failure of <T2} means that the generated SMI signal is the re-sleep software SMI.

If the generated SMI signal is due to the occurrence of a system event, the software SMI
The routine sets the global standby timeout value to 4
Return to seconds (step S208), then resume (R
The SM) command is executed (step S209).

On the other hand, if the generated SMI signal is due to the re-sleep software SMI, the software SMI routine first sets the system timer 1
8 The current time (t
After reading 1), software SMI for generating a stop break software SMI after a certain time is generated.
The time T1 is set in the MI timer 123 (step S
203). After this, the software SMI routine returns S
A stop clock command instructing the generation of TPCLK is set in the register group 121 (step S20).
4).

Then, the software SMI routine
The time (t2) at that time specified by the counter built in the system timer 18 is read, and it is detected whether or not t2-t1 <T1 is satisfied, and the stop break factor is the stop break software S according to the detection result.
It is determined whether it is other than MI (step S20).
5).

The failure of the expression {t2-t1 <T1} means that a stop break has not occurred before the time T1 has passed, that is, the cause of the stop break is the stop break software SMI. On the other hand, the expression {t2-t1 <T1} is satisfied when the stop break occurs within the time T1, that is, the cause of the stop break is the software SMI for stop break.
It means that it is due to factors other than.

If the cause of the stop break is due to a factor other than the software SMI for stop break, the software SMI routine checks whether or not the factor is a timer interrupt (step S206).
This factor check process can be realized by referring to, for example, the register of the interrupt controller 16.

If the cause of the stop break is not a timer interrupt, the software SMI routine executes a system event, that is, IRQ1-15 or NMI.
Is determined to have occurred, the global standby timeout value is returned to 4 seconds (step S208), and then the resume (RSM) instruction is executed (step S209).

On the other hand, when the cause of the stop break is the software SMI for stop break or the timer interrupt, the software SMI routine reads the time (t1 ') at that time designated by the counter built in the system timer 18 and Is set in a predetermined register, and a software SMI timer 12 is generated in order to generate a software SMI for resleep after a predetermined time.
The time T2 is set to 3 (step S207), and then the resume (RSM) instruction is executed (step S20).
9). In step S207, the dummy SM
The above-mentioned flag setting process indicating that the flag is I is also executed.

As described above, in this embodiment, the stop grant state and the normal state are alternately repeated in the sleep mode so that the CPU 11 is set to the sleep mode by mistake while the memory benchmark test is being executed. Even if it happens, it is possible to prevent the situation in which the processing does not proceed further while the execution of the program is suddenly stopped.

In this embodiment, the cause of the system event or the stop break event is checked by measuring the time of the system timer 18. However, for example, a dedicated timer is provided in the system controller 12, or a system event If the system controller 12 is configured so that the information indicating the occurrence can be held in the register or the like, it is possible to check those factors without using the system timer 18.

Also, in this embodiment, the SMI handler,
BI system management program including software SMI routine and global standby SMI routine
Stored in OSROM14, address 3 of SMRAM50
BIOS ROM by jump code of 8000H
Although the SMI handler 14 is called, in the present invention, it is important that the system management program is called by the code at the address 38000H that the CPU 11 fetches first.
SMI in the area starting from address 38000H in
Stores the handler, and the SMI handler stores the BIO
It can also be configured to call the SROM 14 software SMI routines and global standby SMI routines. Further, it goes without saying that the entire system management program including the software SMI routine and the global standby SMI routine may be stored in the SMRAM 50.

Further, it is possible to change the address 38000H to another value by using the above-mentioned SMBASE register.

[0177]

As described in detail above, according to the present invention, the same sleep mode can always be realized regardless of the OS environment, and the power consumption of the CPU can be sufficiently reduced. Even when a high-performance CPU with a built-in PLL is used, the CPU can be quickly returned from the sleep mode.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a computer system according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining three operation states of a CPU provided in the system of the embodiment.

FIG. 3 is a diagram for explaining the operation principle of a system event detection circuit provided in the system of the embodiment.

FIG. 4 is a block diagram showing an example of a SM provided in a CPU provided in the system of the embodiment.
The figure for demonstrating the memory map when I is issued.

FIG. 5 is a block diagram showing a CPU provided in the system of the embodiment in which SM is provided.
The figure for demonstrating operation | movement of CPU when I is issued.

FIG. 6 is a diagram for explaining a first CPU sleep control operation when the CPU is maintained in the stop grant state during the sleep mode in the system of the embodiment.

FIG. 7 is a diagram for explaining re-sleep processing when a stop break occurs due to a timer interrupt in the CPU sleep control operation of FIG.

8 is a CPU in the CPU sleep control operation of FIG.
3 is a timing chart for explaining the operation from when the device shifts to the sleep mode until it returns to the normal operation mode.

9 is a timing chart illustrating a re-sleep process executed in response to the occurrence of a stop break event due to a timer interrupt in the CPU sleep control operation of FIG.

FIG. 10 is a diagram for explaining a second CPU sleep control operation for alternately switching the CPU between the stop grant state and the normal state during the sleep mode in the system of the embodiment.

FIG. 11 is a block diagram showing C in the CPU sleep control operation of FIG.
7 is a timing chart illustrating the operation of the PU from returning to the sleep mode to returning to the normal operation mode.

12 is a flowchart showing a processing procedure of each of a global standby SMI routine and a software SMI routine necessary for realizing the CPU sleep control operation of FIG.

13 is a flowchart showing a processing procedure when a system event occurs, which is executed by the software SMI routine of FIG.

14 is a flowchart showing a processing procedure when a system event occurs, which is executed by the global standby SMI routine of FIG.

15 is a flowchart showing a detailed procedure of a global standby SMI routine for realizing the CPU sleep control operation of FIG.

16 is a flowchart showing a detailed procedure of a software SMI routine for realizing the CPU sleep control operation of FIG.

[Explanation of symbols]

11 ... CPU, 12 ... System controller, 13 ... Main memory, 14 ... BIOS ROM, 16 ... Interrupt controller, 17 ... Keyboard controller, 18 ... System timer, 19 ... Other I / O device, 121 ... Register group, 122 ... Global standby SMI timer, 123 ... Software SMI timer, 124 ... System event detection circuit, 125 ... Global standby SMI generation circuit, 126 ... Software SMI generation circuit, 129 ... Stop break control circuit.

Claims (9)

[Claims] 1. A main memory in which various programs to be executed are stored, an overlay memory in which an instruction for calling a system management program is stored, and which is mapped in a part of an address space of the main memory, and the main memory. Of the program execution mode for executing the program and a system management mode for executing the instruction of the overlay memory, and in response to an interrupt signal supplied to a predetermined interrupt input terminal, the program execution mode is changed to the system management mode. CPU for switching, and CPU sleep means for executing a sleep control routine included in the system management program called by the CPU to switch the operating state of the CPU from a first state to a second state with less power consumption. And the computer System idle detecting means for monitoring various hardware interrupt request signals to the CPU, which are generated in the system, and for detecting a system idle when a preset first timeout time is not generated for all the hardware interrupt request signals. Means for supplying an interrupt signal indicating a system idle to the interrupt input terminal of the CPU in response to the detection of the system idle by the system idle detecting means, and for causing the CPU sleep means to execute the switching processing of the operating state of the CPU A computer system comprising: 2. The CPU includes a PLL that generates an internal clock according to an external clock, and has a normal state in which an instruction is executed, a clock stop state in which instruction execution and the external clock are stopped, and the normal state. State and an intermediate state between the clock stop state and an operation state including a clock stop enable state in which instruction execution is stopped and the external clock can be stopped. A CPU that responds to the transition from the normal state to the clock stop permitting state and returns to the normal state from the clock stop permitting state in response to the stop of the generation of the clock stop signal, wherein the CPU sleep means comprises: By supplying the clock stop signal to the CPU, the CPU Computer system according to claim 1, characterized in that it comprises means for switching the operation state from the normal state to the clock stop permission state. 3. The CPU sleep means, in response to the interrupt signal generated by the timeout of the first timeout time, sets the timeout time of the system idle detecting means to a second time longer than the first timeout time. Means for changing the time-out time of the second CPU in the second state in the state of the second state.
And a means for powering off the system by executing an auto power-off routine included in the system management program called by the CPU when an interrupt signal indicating a system idle is supplied to the CPU due to the timeout of the timeout time. The computer system of claim 1, comprising: 4. A PLL for generating an internal clock according to an external clock is built-in, a normal state in which an instruction is executed, a clock stop state in which instruction execution and the external clock are stopped, a normal state and the clock. It has an operation state located in the middle of the stop state and including a clock stop permission state in which instruction execution is stopped and the external clock can be stopped, and in response to generation of a clock stop signal indicating clock stop permission, A CPU that shifts from the normal state to the clock stop enable state and returns from the clock stop enable state to the normal state in response to the stop of the generation of the clock stop signal, and a clock stop signal generation unit that generates the clock stop signal. And various programs executed by the CPU An overlay memory that stores a main memory to be stored and an instruction to call a system management program and is mapped to a part of an address space of the main memory, and an interrupt signal is supplied to a predetermined interrupt input terminal of the CPU. When the above CP
An overlay memory in which the instruction is executed by U, and a CPU sleep means for executing a sleep control routine included in the system management program called by the CPU and instructing the clock stop signal generating means to generate a clock stop signal. System idle detecting means for monitoring various hardware interrupt request signals generated in the computer system to the CPU, and detecting a system idle when all the hardware interrupt request signals are not generated for a preset time, In response to the detection of the system idle by the system idle detecting means, an interrupt signal indicating the system idle is supplied to the interrupt input terminal of the CPU to cause the CPU sleep means to execute a process of issuing a clock stop signal generation instruction. Prepare Computer system characterized in that. 5. A stop break signal for monitoring the various hardware interrupt request signals, and causing the clock stop signal generation means to stop the generation of the clock stop signal when one of the hardware interrupt request signals is generated. 5. The computer system according to claim 4, further comprising a stop break means for generating the CPU and returning the CPU from the clock stop permission state to the normal state. 6. The CPU sleep means is the CPU.
In response to the return to the normal state of, the means for determining whether or not the cause of the stop break signal is a timer interrupt from a system timer that generates a hardware interrupt request signal at fixed time intervals, and the timer interrupt. And further comprising means for instructing the clock stop signal generation means to generate a clock stop signal when the cause of the stop break signal is determined, and for causing the CPU to shift to the clock stop enable state again. The computer system of claim 5, wherein the computer system is a computer system. 7. A stop break signal indicating the end of the clock stop enable state of the CPU is generated when the time-out period has elapsed after the time-out period was set, and the CPU is returned from the clock stop enable state to the normal state. Stop break means, and the stop break means in response to the interrupt signal indicating the system idle so that the first interrupt signal is generated when a predetermined time has elapsed after the CPU has entered the clock stop enable state. 5. The computer system according to claim 4, further comprising means for setting a predetermined time-out time in the. 8. An interrupt signal indicating the end of the normal state of the CPU is supplied to the interrupt input terminal of the CPU when the time-out period has elapsed after the time-out period has been set, and a clock stop signal is sent to the CPU sleep means. Interrupt signal generating means for executing generation instruction issuing processing; and an interrupt signal indicating the end of the normal state when a predetermined time has elapsed after the CPU was returned to the normal state by the generation of the stop break signal. 8. The computer system according to claim 7, further comprising means for setting a predetermined timeout time in the interrupt signal generating means in response to the generation of the stop break signal. 9. A PLL for generating an internal clock according to an external clock is built in, a normal state in which an instruction is executed, a clock stop state in which instruction execution and the external clock are stopped, the normal state and the clock. It has an operation state located in the middle of the stop state and including a clock stop permission state in which instruction execution is stopped and the external clock can be stopped, and in response to generation of a clock stop signal indicating clock stop permission, A CPU that shifts from the normal state to the clock stop enable state and returns from the clock stop enable state to the normal state in response to the stop of the generation of the clock stop signal, and a clock stop signal generation unit that generates the clock stop signal. And various programs executed by the CPU An overlay memory that stores a main memory to be stored and an instruction to call a system management program and is mapped to a part of an address space of the main memory, and an interrupt signal is supplied to a predetermined interrupt input terminal of the CPU. When the above CP
An overlay memory in which the instruction is executed by U, and a CPU sleep means for executing a sleep control routine included in the system management program called by the CPU and instructing the clock stop signal generating means to generate a clock stop signal. System idle detecting means for monitoring various hardware interrupt request signals generated in the computer system to the CPU, and detecting a system idle when all the hardware interrupt request signals are not generated for a preset time, A means for supplying an interrupt signal indicating system idle to the interrupt input terminal of the CPU in response to the detection of the system idle by the system idle detecting means, and causing the CPU sleep means to execute a process of issuing a clock stop signal generation instruction; Each of the above And a system event detecting means for monitoring the generation of a system event when one of the hardware interrupt request signals is generated, and a system event detecting means for responding to the detection of the occurrence of the system event by the system event detecting means. To stop the clock stop signal generation means from generating the clock stop signal,
To a normal state from the clock stop permission state, the CPU sleep means is configured such that the CPU sleeps during a period from generation of an interrupt signal indicating the system idle to detection of occurrence of a system event by the system event detection means. A computer system comprising: means for causing the clock stop signal generating means to intermittently generate the clock stop signal so as to alternately repeat the clock stop enable state and the normal state.