JPH07201633A - Multilayer ceramic capacitor and manufacturing method thereof - Google Patents

Multilayer ceramic capacitor and manufacturing method thereof

Info

Publication number
JPH07201633A
JPH07201633A JP5336126A JP33612693A JPH07201633A JP H07201633 A JPH07201633 A JP H07201633A JP 5336126 A JP5336126 A JP 5336126A JP 33612693 A JP33612693 A JP 33612693A JP H07201633 A JPH07201633 A JP H07201633A
Authority
JP
Japan
Prior art keywords
dielectric ceramic
internal electrodes
layer
ceramic capacitor
printed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5336126A
Other languages
Japanese (ja)
Other versions
JP2998538B2 (en
Inventor
Hisanao Nakakura
久直 中蔵
Iwao Ishikawa
巌夫 石川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP5336126A priority Critical patent/JP2998538B2/en
Publication of JPH07201633A publication Critical patent/JPH07201633A/en
Application granted granted Critical
Publication of JP2998538B2 publication Critical patent/JP2998538B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

(57)【要約】 【目的】 セラミック表面での沿面放電を防止し、また
内部電極と接続していない外部電極との間での放電を防
止することにより、絶縁抵抗不良を減少した積層セラミ
ックコンデンサを作成することを目的とする。 【構成】 対向する内部電極2間は誘電体セラミック層
1からなり、対向する内部電極2間以外の絶縁体部分は
前記誘電体セラミック層1よりも高耐圧である絶縁物の
ガラス層3にすることにより、耐湿負荷試験において絶
縁抵抗不良を防止することができ、かつ切断マージンお
よび無効層厚みを小さくできることにより小型で高容量
の積層セラミックコンデンサを作製することができる。
(57) [Abstract] [Purpose] A multilayer ceramic capacitor with reduced insulation resistance defects by preventing creeping discharge on the ceramic surface and preventing discharge between internal electrodes and external electrodes not connected. The purpose is to create. A dielectric ceramic layer 1 is formed between opposed internal electrodes 2, and an insulator portion other than the opposed internal electrodes 2 is a glass layer 3 of an insulator having a higher breakdown voltage than the dielectric ceramic layer 1. As a result, insulation resistance failure can be prevented in the moisture resistance load test, and the cutting margin and the ineffective layer thickness can be reduced, so that a small-sized high-capacity multilayer ceramic capacitor can be manufactured.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は積層セラミックコンデン
サおよびその製造方法に関するものであり、特に中高圧
用積層セラミックコンデンサに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monolithic ceramic capacitor and a method of manufacturing the same, and more particularly to a monolithic ceramic capacitor for medium and high voltage.

【0002】[0002]

【従来の技術】一般に積層セラミックコンデンサはセラ
ミックグリーンシートならびにセラミックグリーンシー
ト上に内部電極ペーストを印刷したシートを積み重ねた
後、加圧させて積層体とし、次に焼成し焼結体の両端部
に内部電極と接続される外部電極を設けた構造である。
2. Description of the Related Art Generally, a laminated ceramic capacitor is formed by stacking a ceramic green sheet and a sheet on which an internal electrode paste is printed on the ceramic green sheet, pressurizing it to form a laminated body, and then firing it to both ends of the sintered body. This is a structure in which an external electrode connected to the internal electrode is provided.

【0003】中高圧積層セラミックコンデンサ(1KV
級以上)では、誘電体セラミック表面の沿面放電が起こ
りやすくなるため、誘電体セラミックの寸法を長くする
ことにより電極間距離を大きくし沿面放電を防止してい
た。
Medium and high voltage monolithic ceramic capacitors (1 KV
Since the creeping discharge is likely to occur on the surface of the dielectric ceramic, the distance between the electrodes is increased by increasing the dimension of the dielectric ceramic to prevent the creeping discharge.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、上記の
従来の構成では高電圧で使用する場合、誘電体セラミッ
ク表面での沿面放電を防止するために電極間距離を長く
しなければならず、そのために形状が大きくなり、コス
トが高くなるという問題点を有していた。また内部電極
と接続していない外部電極との間で放電しやすく絶縁抵
抗不良を起こしやすいという問題点を有していた。
However, in the above conventional structure, when used at a high voltage, the distance between the electrodes must be increased in order to prevent creeping discharge on the surface of the dielectric ceramic. There is a problem that the shape becomes large and the cost becomes high. In addition, there is a problem that discharge is likely to occur between the internal electrode and the external electrode that is not connected, and defective insulation resistance is likely to occur.

【0005】本発明は上記従来の問題点を解決するもの
で、誘電体セラミック層の表面での沿面放電を防止し、
また内部電極と接続していない外部電極との間での放電
を防止することにより、絶縁抵抗不良を減少した積層セ
ラミックコンデンサを作成することを目的とする。
The present invention solves the above-mentioned conventional problems by preventing creeping discharge on the surface of the dielectric ceramic layer,
It is another object of the present invention to produce a monolithic ceramic capacitor in which defective insulation resistance is reduced by preventing discharge between the internal electrode and an external electrode which is not connected.

【0006】[0006]

【課題を解決するための手段】この目的を達成するため
に本発明は、積層された内部電極が一層おきに所定の外
部電極と接続し、対向する内部電極の間の部分は誘電体
セラミック層からなり、対向する内部電極の間以外の絶
縁体部分は前記誘電体セラミック層よりも高耐圧である
絶縁物で構成している。
In order to achieve this object, according to the present invention, laminated internal electrodes are connected to predetermined external electrodes every other layer, and a portion between the opposed internal electrodes is a dielectric ceramic layer. Insulators other than between the opposing internal electrodes are made of an insulator having a higher breakdown voltage than the dielectric ceramic layer.

【0007】[0007]

【作用】したがって本発明の構成によれば、誘電体セラ
ミック層表面で沿面放電が起こりにくく、また内部電極
と接続していない外部電極との間で放電が起こりにくく
なり、積層セラミックコンデンサの絶縁抵抗不良が減少
する。
According to the structure of the present invention, therefore, creeping discharge is unlikely to occur on the surface of the dielectric ceramic layer, and discharge is unlikely to occur between the internal electrode and the external electrode which is not connected. Defects are reduced.

【0008】[0008]

【実施例】【Example】

(実施例1)図1,図2には本発明の一実施例の積層セ
ラミックコンデンサの断面図が示されている。図1,図
2において、1は誘電体セラミック層、2は内部電極、
3は誘電体セラミック層1より高耐圧である絶縁物から
なるガラス層、4は外部電極を示し、積層された内部電
極2が一層おきに所定の外部電極4に接続され、対向す
る内部電極2間には誘電体セラミック層1が形成され、
対向する内部電極2間以外はガラス層3で構成されてい
る。また、両外表面にもガラス層3が形成されている。
(Embodiment 1) FIGS. 1 and 2 are sectional views of a monolithic ceramic capacitor according to an embodiment of the present invention. 1 and 2, 1 is a dielectric ceramic layer, 2 is an internal electrode,
Reference numeral 3 denotes a glass layer made of an insulating material having a higher breakdown voltage than the dielectric ceramic layer 1, 4 denotes external electrodes, and the stacked internal electrodes 2 are connected to predetermined external electrodes 4 every other layer, and the internal electrodes 2 facing each other are provided. A dielectric ceramic layer 1 is formed between them,
The glass layer 3 is formed except between the opposing internal electrodes 2. The glass layer 3 is also formed on both outer surfaces.

【0009】このように内部電極2の対向する部分以外
は誘電体セラミック層1より高耐圧のガラス層3で形成
しているため、耐湿負荷試験においても絶縁抵抗不良が
低減でき、誘電体セラミック層1の表面で沿面放電が発
生しにくくなる。
Since the glass layer 3 having a higher breakdown voltage than the dielectric ceramic layer 1 is formed except for the opposing portions of the internal electrodes 2 as described above, defective insulation resistance can be reduced even in a humidity resistance load test, and the dielectric ceramic layer can be reduced. No creeping discharge is likely to occur on the surface of No. 1.

【0010】次に、この積層セラミックコンデンサの製
造方法について説明する。まず、キャリアフィルム上に
誘電体セラミックペースト9をスクリーン印刷により長
方形状に連続的にパターニングしたスクリーンにより印
刷乾燥し、次に、誘電体セラミックペースト9を印刷し
なかった部分にガラスペースト3を印刷乾燥し、図3に
示すようなグリーンシート5を構成した。次に図3のグ
リーンシート5上に内部電極ペースト2をスクリーン印
刷により印刷乾燥し図4に示すように内部電極2を有す
るグリーンシート5を構成した。次に図5に示すような
位置関係を持って複数の内部電極2を有するグリーンシ
ート5を積層した。このように積層したグリーンシート
5の上側および下側に必要に応じて内部電極2が形成さ
れていないガラスペーストのみで作製したグリーンシー
トを所定枚数積層した。積層したグリーンシートはプレ
スしてお互いに圧着し積層体を構成した。次に切断し、
バインダアウト、焼成を行い、その後外部電極4を塗
布、焼き付けしNiメッキ、Sn−Pbメッキを行い、
積層セラミックコンデンサとした。
Next, a method of manufacturing the monolithic ceramic capacitor will be described. First, the dielectric ceramic paste 9 is printed and dried on a carrier film by a screen which is continuously patterned in a rectangular shape by screen printing, and then the glass paste 3 is printed and dried on a portion where the dielectric ceramic paste 9 is not printed. Then, the green sheet 5 as shown in FIG. 3 was formed. Next, the internal electrode paste 2 was printed and dried on the green sheet 5 of FIG. 3 by screen printing to form a green sheet 5 having the internal electrodes 2 as shown in FIG. Next, the green sheets 5 having a plurality of internal electrodes 2 were laminated in a positional relationship as shown in FIG. A predetermined number of green sheets prepared only from the glass paste on which the internal electrodes 2 were not formed were laminated on the upper and lower sides of the thus laminated green sheets 5. The laminated green sheets were pressed and pressed together to form a laminated body. Then disconnect
Binder out and firing are performed, and then the external electrode 4 is applied and baked, and Ni plating and Sn-Pb plating are performed,
A monolithic ceramic capacitor was used.

【0011】得られた積層セラミックコンデンサは静電
容量10000pF、Tanδ1.0%、絶縁抵抗1×
1011Ωであった。
The obtained monolithic ceramic capacitor has an electrostatic capacity of 10000 pF, Tan δ 1.0% and an insulation resistance of 1 ×.
It was 10 11 Ω.

【0012】この積層セラミックコンデンサを用いて6
0℃95%の環境下で500Vの電圧を印加する耐湿負
荷試験を行った結果を(表1)に示す。なお、5×10
8Ω以下を絶縁抵抗不良とした。
Using this monolithic ceramic capacitor,
The results of a moisture resistance load test in which a voltage of 500 V is applied in an environment of 0 ° C. and 95% are shown in (Table 1). 5 × 10
Insulation resistance was considered to be 8 Ω or less.

【0013】(比較例1)キャリアフィルム上に誘電体
ペーストをリバースロールコータにより塗布、印刷しセ
ラミックグリーンシートを作製した。次にキャリアフィ
ルムから剥離したセラミックグリーンシート上に内部電
極ペーストをスクリーン印刷により印刷、乾燥し、その
上にセラミックグリーンシートを積層した。その後、内
部電極ペーストの印刷、乾燥と、セラミックグリーンシ
ートの積層を繰り返し、プレスしてお互いに圧着し積層
体とした。以降は実施例1と同様である。
(Comparative Example 1) A dielectric paste was applied on a carrier film by a reverse roll coater and printed to prepare a ceramic green sheet. Next, the internal electrode paste was printed by screen printing on the ceramic green sheet peeled from the carrier film and dried, and the ceramic green sheet was laminated thereon. After that, printing and drying of the internal electrode paste and lamination of the ceramic green sheets were repeated, pressed and pressed together to form a laminate. The subsequent steps are the same as in the first embodiment.

【0014】得られた積層セラミックコンデンサを用い
て実施例1と同様に耐湿負荷試験を行った結果を(表
1)に示す。
The results of a moisture resistance load test carried out in the same manner as in Example 1 using the obtained monolithic ceramic capacitor are shown in (Table 1).

【0015】[0015]

【表1】 [Table 1]

【0016】この(表1)から明らかなように、本発明
の積層セラミックコンデンサは耐湿負荷試験における絶
縁抵抗不良を防止することができた。
As is clear from this (Table 1), the laminated ceramic capacitor of the present invention was able to prevent defective insulation resistance in the moisture resistance load test.

【0017】[0017]

【発明の効果】以上のように本発明は対向する内部電極
間以外の絶縁体部分を誘電体セラミック層よりも高耐圧
である絶縁物にすることにより、耐湿負荷試験において
絶縁抵抗不良を防止することができ、かつ切断マージン
および無効層厚みを小さくできることにより小型で高容
量の積層セラミックコンデンサを作製することができ
る。
As described above, according to the present invention, the insulating portion other than between the opposing internal electrodes is made of an insulating material having a higher withstand voltage than the dielectric ceramic layer, thereby preventing insulation resistance failure in the moisture resistance load test. Since the cutting margin and the ineffective layer thickness can be reduced, a small-sized and high-capacity monolithic ceramic capacitor can be manufactured.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例における積層セラミックコン
デンサの縦断面図
FIG. 1 is a vertical sectional view of a monolithic ceramic capacitor according to an embodiment of the present invention.

【図2】同積層セラミックコンデンサの横断面図FIG. 2 is a cross-sectional view of the same monolithic ceramic capacitor.

【図3】同積層セラミックコンデンサを作るためにグリ
ーンシートを作成した状態の平面図
FIG. 3 is a plan view of a state in which a green sheet is created to make the monolithic ceramic capacitor.

【図4】同積層セラミックコンデンサを作るためにグリ
ーンシート上に内部電極を形成した状態の平面図
FIG. 4 is a plan view showing a state in which internal electrodes are formed on a green sheet to make the same multilayer ceramic capacitor.

【図5】同積層セラミックコンデンサを作るための積層
状態を示す説明図
FIG. 5 is an explanatory view showing a laminated state for making the same laminated ceramic capacitor.

【符号の説明】[Explanation of symbols]

1 誘電体セラミック層 2 内部電極 3 ガラス層 4 外部電極 1 Dielectric ceramic layer 2 Internal electrode 3 Glass layer 4 External electrode

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 積層された内部電極が一層おきに所定の
外部電極と接続され、対向する内部電極間は誘電体セラ
ミック層からなり、対向する内部電極間以外の絶縁体部
分は前記誘電体セラミック層よりも高耐圧である絶縁物
からなる積層セラミックコンデンサ。
1. A laminated internal electrode is connected to a predetermined external electrode every other layer, a dielectric ceramic layer is formed between opposed internal electrodes, and an insulator portion other than the opposed internal electrodes is formed of the dielectric ceramic layer. Multilayer ceramic capacitor made of an insulator that has a higher breakdown voltage than the layers.
【請求項2】 長方形状に連続的にパターニングしたス
クリーンにより誘電体セラミックペーストを印刷し、次
に前記誘電体セラミックペーストを印刷しなかった部分
に前記誘電体セラミックよりも高耐圧である絶縁体ペー
ストを印刷、乾燥してグリーンシートを作成する工程
と、前記グリーンシート中の誘電体セラミック層上と、
誘電体セラミック層の長手方向の間隙上を一つおきに内
部電極ペーストを印刷、乾燥し、その内部電極を印刷し
たグリーンシートならびに絶縁物シートを積み重ねた後
加圧させて積層体として焼成し、その焼結体の両端部に
内部電極と接続される外部電極を塗布する工程からなる
積層セラミックコンデンサの製造方法。
2. An insulating paste having a higher breakdown voltage than the dielectric ceramic is printed on a portion where the dielectric ceramic paste is not printed, by printing the dielectric ceramic paste on a screen which is continuously patterned in a rectangular shape. Printing and drying to produce a green sheet, and on the dielectric ceramic layer in the green sheet,
The internal electrode paste is printed on every other space in the longitudinal direction of the dielectric ceramic layer, dried, and the green sheets and the insulating sheets on which the internal electrodes are printed are stacked and then pressed to be fired as a laminate, A method for manufacturing a monolithic ceramic capacitor, which comprises a step of applying external electrodes connected to internal electrodes to both ends of the sintered body.
JP5336126A 1993-12-28 1993-12-28 Multilayer ceramic capacitor and method of manufacturing the same Expired - Fee Related JP2998538B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5336126A JP2998538B2 (en) 1993-12-28 1993-12-28 Multilayer ceramic capacitor and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5336126A JP2998538B2 (en) 1993-12-28 1993-12-28 Multilayer ceramic capacitor and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH07201633A true JPH07201633A (en) 1995-08-04
JP2998538B2 JP2998538B2 (en) 2000-01-11

Family

ID=18295968

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5336126A Expired - Fee Related JP2998538B2 (en) 1993-12-28 1993-12-28 Multilayer ceramic capacitor and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP2998538B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0818792A1 (en) * 1996-05-09 1998-01-14 Murata Manufacturing Co., Ltd. Multilayer capacitor
JP2010147169A (en) * 2008-12-17 2010-07-01 Tdk Corp Multilayer ceramic electronic component
WO2016152990A1 (en) * 2015-03-25 2016-09-29 京セラ株式会社 Electronic component

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102163418B1 (en) 2018-11-02 2020-10-08 삼성전기주식회사 Multi-layered ceramic capacitor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0818792A1 (en) * 1996-05-09 1998-01-14 Murata Manufacturing Co., Ltd. Multilayer capacitor
US5812363A (en) * 1996-05-09 1998-09-22 Murata Manufacturing Co., Ltd. Multilayer capacitor including a dielectric breakdown prevention layer
JP2010147169A (en) * 2008-12-17 2010-07-01 Tdk Corp Multilayer ceramic electronic component
WO2016152990A1 (en) * 2015-03-25 2016-09-29 京セラ株式会社 Electronic component
JPWO2016152990A1 (en) * 2015-03-25 2017-12-07 京セラ株式会社 Electronic components

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