JPH07202968A - Demodulator - Google Patents

Abstract

(57) [Abstract] [Purpose] In a multiplex communication system, when the base station side limits the dynamic range when combining channel signals, the basic performance is not compromised in order to reduce errors that occur, and it is extremely simple. By adding a simple circuit,
The signal information originally needed is reproduced. [Structure] In the receiving system, an I signal data complement circuit 3
2 and Q signal data complementing circuit 33 is provided at the subsequent stage of I and Q signal analog-digital converters 24 and 25. This I, Q
The signal data complementation circuits 32 and 33 output the output data obtained by squaring the input data, which is advantageous when limiting the dynamic range.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator used in a communication network having a base station for a plurality of terminal stations, for example, a mobile telephone installed in a public wireless telephone, an automobile, or a communication network by optical communication. Is.

[0002]

2. Description of the Related Art In a base station communication device, for example, which needs to combine and send out a plurality of communication channels using the same frequency band, conventionally, as shown in FIG. 5, a method of adding individual voltage signals is generally used. It was target.

FIG. 5 shows a system configuration diagram of a transmission system and a reception system in a conventional base station communication device.

The example of the system configuration shown in FIG. 5 shows the case where QPSK, that is, four-phase modulation is used for code transmission. QPSK is a serial baseband signal in the base band converted into two series of orthogonal signals and is composed of parallel 2-bit signals. By making them parallel, the transmission speed can be halved without changing the base frequency bandwidth, and it is easy to detect the influence of external noise that interferes almost at the same time, and it is easy to eliminate the influence of external noise. It has many advantages.

In FIG. 5, in the transmission system (I), signals of a plurality of channels, that is, baseband signal 1 (1), baseband signal 2 (2), ..., Baseband signal n (3), Corresponding channel recognition encoders 4, 5, ...
6 and is added with a channel identification code.

Each output to which the channel recognition code has been added is divided into I and Q of quadrature components by a quadrature modulation I and Q divider 7 and an I signal digital-analog converter (D / A) 8 is provided.
Added to the Q signal digital-to-analog converter (D / A) 9,
It becomes an analog signal of the multiplexed I and Q signals. Each synthesized signal is a reference carrier signal 10 for quadrature modulation.
Is multiplied by. That is, the I signal side is Q in the I signal quadrature modulation multiplier 11, and the Q signal side is the phase shifter 12 which gives a phase difference of 90 degrees to the quadrature modulation reference carrier signal 10.
The signal is multiplied in the quadrature modulation multiplier 13.

These multiplication outputs are added to the quadrature modulation adder 14
Is added to the transmission output amplifier 16 through the band pass filter (BPF) 15 and the output is sent to the receiving system side. The transmitted signal reaches the reception system (II) through the propagation path 17 in the air or a cable, and is multiplied by the orthogonal demodulation reference carrier signal 18 for orthogonal demodulation. On the I signal side, the I signal orthogonal demodulation multiplier 19
On the Q signal side, the phase shifter 20 gives a phase difference of 90 degrees to the Q signal quadrature demodulation multiplier 21.

Thus, the demodulated signals that have undergone the quadrature demodulation pass through the low-pass filters (LPF) 22 and 23, respectively, and the I signal, Q signal analog and digital converter (D / A) 2
The signals I and Q of the desired channel j are extracted by the channel signal detection circuits 26 and 27, respectively, which are digitized by 4 and 25, and the baseband signal j (29 ) Is played.

FIG. 6 is a view of the outputs of the quadrature modulation I / Q signal digital-analog converters (D / A) 8 and 9 shown in FIG. 5 on an IQ plane, where I is the I signal axis and Q. Is the Q signal axis.

[0010]

Problems to be Solved by the Invention As shown in FIG.
A lattice formed on the IQ plane of SK multiplexing, that is, since this is a QPSK signal, in the case of only one channel,
Only the central circle with stitches is present, and the signal exists at four points at 45 degrees diagonal. Next, when one channel is added, all four points, which are the centers of the new circles, become points at all 45 degrees diagonally of the four circles. At this point, the number of points is nine. When a new signal of one channel is further added, nine new circles centering on the above nine points are formed, which results in Q
The grid points of PSK are 16.

As the number of channels increases, the radius to the outermost shell increases in proportion to the number of channels. As a result, the dynamic range that increases with channel combination increases dramatically in proportion to the square of the channel increase. This inherently presents the very big problem that the power dynamic range of a modulator, which would otherwise be as power-consuming as the channel multiplexing of a single channel of power, would require that squared excess dynamic range. Was there.

[0012] As described above, the multiplexing by the voltage signal increases squarely in terms of electric power, and the larger the number of channels, the larger the load on the transmitter including the modulator.

The present invention solves the above problems and, in a multiplex communication system, has a basic performance in order to reduce an error that occurs when a base station side limits a dynamic range when combining channel signals. Without any damage
It is an object of the present invention to provide a demodulation device in a reception system that accurately reproduces originally required signal information only by adding an extremely simple circuit.

[0014]

In order to solve the above-mentioned problems and achieve the object, the present invention provides a means for receiving a multiplexed communication signal and a data after digital conversion of the communication signal. It is characterized by having means for squaring and means for decoding the output.

A second means is a means for receiving the multiplexed communication signal, a means for estimating the upper bits truncated from the adjacent data sequence of the communication signal based on the characteristics of the Gray code, and the estimation thereof. It is characterized in that it has means for converting the converted Gray code output into a binary signal.

[0016]

According to the present invention, in channel combination in the demodulator for base station reception, there is provided means for receiving and squaring the transmission information limited to the lattice range corresponding to the square root of the number of channels on the I and Q voltage axes. As a result, the square operation is performed from the received signal with the limited I and Q voltage axes, and the electric power having a value that is twice the number of channels of the information to be originally transmitted can be reproduced.
Therefore, it is possible to solve the problem that excessive dynamic range and excessive power of the I and Q combined signals are generated in the receiving side demodulator.

Further, by having a means for utilizing the characteristics of the Gray code for estimating the upper bits to be originally transmitted and for reproducing and restoring, the demodulation of the dynamic range close to the value of the number of channels to be originally transmitted is provided. The signal is regenerated. This makes it possible to limit the range of the I, Q voltage axis of the base station demodulator, and reduce the occurrence of excessive dynamic range and excessive power in the I, Q combined signal in the demodulator of the multi-channel set. it can.

[0018]

1 is a system configuration diagram of a transmission system and a reception system of a base station communication device according to a first embodiment of the present invention. The reference numerals indicating the respective constituent elements in FIG. 1 are I signal synthesizing / data converting section 30, Q signal synthesizing / data converting section 31,
Except for the I-signal data complementing circuit 32 and the Q-signal data complementing circuit 33, the components are the same as those of the conventional example indicated by the numbers in FIG.

The configuration and operation of the first embodiment will be described below with reference to FIG. In the transmission system (I), as in the conventional example, each channel signal which has passed through the channel recognition encoders 4, 5, ... Is supplied to the I signal synthesis / data conversion section 30 and the Q signal synthesis / data conversion section 31 of QPSK. I signal synthesis / data conversion unit 30 and Q signal synthesis /
The output of the data converter 31 will be hereafter similar to the conventional example, the I signal digital-analog converter (D / A) 8 and the Q signal digital analog converter (D / A) 9, the I signal quadrature modulation multiplier 1
1. After being supplied to the quadrature modulation multiplier 12 for the Q signal, the same processing as in the conventional example is performed, the signal is output to the propagation path 17, and enters the receiving system (II).

Here, the I signal digital-analog converter (D / A) 8 and the Q signal digital-analog converter (D
/ A) 9 outputs the output as a square root corresponding to a linear digital input.

In the reception system (II), the I and Q signals are subjected to quadrature demodulation by the I and Q signal quadrature demodulation multipliers 19 and 21.
Each demodulated signal passes through a low pass filter (LPF) 22, 23, and then an I, Q signal analog-digital converter (D / A) 24,
Added to 25. Analog-to-digital converter for I signal
(D / A) 24 and analog / digital converter for Q signal (D
The output of the / A) 25 is supplied to the I signal data complement circuit 32 and the Q signal data complement circuit 33. In the I signal data complement circuit 32 and the Q signal data complement circuit 33,
The output data obtained by squaring the input data is output. That is, "1" is converted into "1", "2" is converted into "4", "3" is converted into "9", and so on. From the outputs of the I-signal data complementing circuit 32 and the Q-signal data complementing circuit 33, the I and Q signals of the desired channel j are extracted by the channel signal detecting circuits 26 and 27, and thereafter, these two outputs are output as in the conventional example. The received decoder 28 receives the baseband signal j (2
9) is played.

In this embodiment having the above-mentioned structure, the input / output of the transmission output amplifier 16 is as follows from the above operation.
For each multiplexed channel signal, the voltage amplitude is given in the state where its square root is calculated, that is, in the form of power proportional to the number of channels. Therefore, the transmission output amplifier 16 need only have a dynamic range of power equal to the number of channels.

FIG. 2 is a data complementing circuit for I signal shown in FIG.
32 is a circuit configuration diagram of a specific example of a Q signal data complementation circuit 33. FIG. In the receiving system, the upper 2 bits of the demodulated data are used as the input first bit 34 and the input second bit 35. These two inputs are supplied to the first gate 37 and the second gate 38 for converting the Gray code to the binary number together with the virtual signal path of the most significant bit 36 to be originally transmitted. The respective outputs 39 and 40 of the conversion first gate 37 and the second gate 38 are supplied to the reverse conversion first gate 41 and the second conversion gate 42 together with the virtual signal path of the most significant bit 36. Inverting first gate 41 and second
The respective outputs 43 and 44 of the gate 42 are supplied to the most significant bit reproduction comparison circuit 45. High-order bit reproduction comparison circuit
The upper 2 bits of the data demodulated by the receiving system are also supplied to 45 as input first bit 34 and input second bit 35. From the most significant bit reproducing comparison circuit 45, an output 46 in which the most significant bit to be originally transmitted is reproduced is sent out.

In operation, the I-signal data complementing circuit 32 and the Q-signal data complementing circuit 33 receive the input first bit 34 and the input second bit 35 of the data demodulated in the receiving system, The most significant bit originally transmitted from the comparison circuit 45 for reproducing the most significant bit is supplied to the first gate 37 and the second gate 38 for converting the Gray code into the binary number together with the output 46 reproduced. Conversion first gate 37 and second
Since the gate 38 is composed of an exclusive OR circuit,
For conversion with the input first bit 34 and the input second bit 35 as input, the first bit 37 of the binary number from the first gate 37 and the input second bit 35 and the most significant bit reproduction output 46 as input The second gate 38 outputs a second bit 40 of a binary number.

Therefore, the binary signal 46, 39, 40 causes the receiving system to output the most significant 3-bit signal to the channel signal detection circuits 26, 27 as the outputs of the I signal data complementing circuit 32 and the Q signal data complementing circuit 33. Decoder 28 which is supplied and extracts the I and Q signals of the desired channel j and receives the two outputs
Will reproduce the baseband signal j (29) of channel j.

At the same time, the binary signals 46, 39 and 40 are supplied to the first and second gates 41 and 42 for inverse conversion, and are again gray coded. That is, the inverse conversion first gate 41 of the exclusive OR circuit which receives the first bit 39 and the second bit 40 of the binary signal is the gray-coded first bit signal 43.
The second gate 42 for inverse conversion of the exclusive OR circuit which receives the second bit 40 of the binary signal and the most significant bit 46 as the input generates the second bit signal 44 gray coded respectively, and the most significant bit It is supplied to the reproduction comparison circuit 45. The most significant bit reproduction comparison circuit 45 is also supplied with the input first bit 34 and the input second bit 35, which are the upper two bits of the data demodulated by the receiving system, and outputs the input first bit 34 and the first bit signal 43. Input second
The bit 35 and the second bit signal 44 are compared, and if they do not match at the same time, the most significant bit reproduction output 46 is inverted.

As described above, the most significant bit is reproduced, and correct information can be reproduced even if the most significant bit to be originally transmitted is truncated by the transmission system. Therefore, it is possible to limit the dynamic range of the transmission system modulator.

Next, the gray code binary number conversion of the second embodiment of the present invention will be described with reference to FIG. First before
In the embodiment shown in FIG. 1, the baseband signal 1 (1), the baseband signal 2 (2), ..., The baseband signal n (3) are respectively encoded by the corresponding channel recognition coding as in the conventional example. , 6, and is added with a channel recognition code. Each output which has been added with the channel recognition code is subjected to quadrature modulation I, Q slicing divider 7 to obtain quadrature component I,
Each signal divided into Q and synthesized is multiplied by the quadrature modulation reference carrier signal 10. I signal synthesis /
In the data converter 30 and the Q signal synthesizer / data converter signal 31, the upper bits are truncated when the data length exceeds the required value.

The fluctuation speed of the upper bits is the slowest among all the bits, and the bit with the highest fluctuation, that is, the highest frequency is the LSB. Therefore, it can be said that the bits necessary for correctly transmitting information are close to LSB.

If the upper bits are simply truncated, a significant discontinuity occurs before and after the digit digit raising operation. Therefore, the digit digit raising procedure before and after the bits to be truncated is made similar to the Gray code conversion. That is, when targeting the upper bits composed of 3 bits, in general binary numbers,
000, 001, 010, 011, 100, 101, 110, 1 increasing status
It is circulated and expressed as 11,000, but the part following 111,000 becomes large discontinuity. Furthermore, if the upper 1 bit is truncated, it circulates as 00, 01, 11, 00, and the discontinuity between 11 and 00 becomes a problem. Therefore, the code is 000, 001, 011, 010,
Circulate 110, 111, 101, 100,000. In this case, the Hamming distances of adjacent codes are all 1 and at the same time,
Even if the most significant bit is cut off, 00, 01, 11, 10, 10, 10, 11,
The cycle is 01, 00, 00, and the Hamming distance is 1 or less even in this case. Although there is a part where 10 and 00 overlap, it is obvious that the effect of preventing discontinuity outweighs the harmful effects. A similar method can be used to encode a number of 4 bits or more. In this way, by keeping the signal with more digits than necessary in the desired digit range, it is possible to realize a modulated signal that falls within the desired dynamic range without significantly mistaking the signal information.

The information processed in this way is gray-coded in binary as illustrated in FIG. 3 (a). Then, the same processing as in the conventional example is performed, demodulated in the receiving system, and further supplied to the I signal data complementing circuit 32 and the Q signal data complementing circuit 33 of the demodulated QPSK, and the upper order cut off in the transmitting system here. The bit is estimated from the data of the I signal and the Q signal that have been received, and complemented. Further, in the I-signal data complementing circuit 32 and the Q-signal data complementing circuit 33, the reproduced gray coded I-signal and Q-signal data is returned to the original binary data shown in FIG. 3B. I signal complement /
From the outputs of the data conversion unit 32 and the Q signal data complement circuit 33, the I and Q signals of the desired channel j are extracted by the channel signal extraction circuits 26 and 27, as in the conventional example, and the two outputs are received. The decoder 28 reproduces the baseband signal j (29) of channel j.

FIG. 4 shows a system configuration diagram of the transmission system and the reception system of the base station communication device in the third embodiment of the present invention.
I / Q signal digital-analog converter in FIG. 1
(D / A) I / Q signal synthesizer / data converter in the latter stage of 8 and 9
The difference is that it has 30, 31. The operation is the same as in the conventional example. Each channel signal that has entered the quadrature modulation IQ division / divider 7 through the channel recognition encoders 4, 5, ... , Q signal, I signal digital analog converter (D / A)
8 and the output of the Q signal digital-analog converter (D / A) 9 outputs the output corresponding to the linear digital input as its square root via the I, Q signal synthesizing / data converting units 30, 31 and the like. . In the receiving system (II), the I and Q demodulated signals after quadrature demodulation pass through the low-pass filters (LPF) 22 and 23, and then the I and Q signal analog-digital converter (D / D). A) Added to 24, 25. here,
The I, Q signal analog-digital converters (D / A) 24, 25 output a square action with respect to a linear input.

Hereinafter, I and Q signal data complementing circuits 32 and 33
The operations such as the above are similar to those described with reference to FIG.

[0034]

As described above, the demodulator according to the present invention can prevent the excessive transmission power dynamic range generated by the synthesis of digital signals in the receiving system without impairing the basic performance in the channel where the channels are multiplexed. Only by adding a very simple circuit, it becomes possible to fit within the necessary and sufficient transmission power dynamic range that is originally necessary.

[Brief description of drawings]

FIG. 1 is a system configuration diagram of a transmission system and a reception system of a base station communication device according to a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a specific example of a data complementing circuit for I and Q signals shown in FIG.

FIG. 3 shows a Gray code in the second embodiment of the present invention.
It is an example figure of a binary number conversion.

FIG. 4 is a system configuration diagram of a transmission system and a reception system of a base station communication device according to a third embodiment of the present invention.

FIG. 5 is a system configuration diagram of a transmission system and a reception system of a conventional base station communication device.

6 is a view of the output of the quadrature modulation IQ signal digital-analog converter of FIG. 5 viewed on the IQ plane.

[Explanation of symbols]

1 ... Baseband signal 1, 2 ... Baseband signal 2,
3 ... Baseband signal n, 4, 5, 6 ... Channel recognition encoder, 7 ... Quadrature modulation I, Q conversion divider, 8 ... I signal digital / analog converter, 9 ... Q signal digital / analog converter, 10 ... Reference carrier signal for quadrature modulation, 11 ... I
Quadrature modulation multiplier for signal, 12 ... Phase shifter, 13 ... Quadrature modulation multiplier for Q signal, 14 ... Quadrature modulation adder, 15 ... Band pass filter (BPF), 16 ... Transmission output amplifier, 17
... Propagation path, 18 ... Quadrature demodulation reference carrier signal, 19 ... I
Quadrature demodulation multiplier for signals, 20 ... Phase shifter, 21 ... Quadrature modulation multiplier for Q signals, 22, 23 ... Low pass filter (LP
F), 24 ... I signal analog-digital converter, 25 ... Q
Signal analog-digital converter, 26, 27 ... Channel signal detection circuit, 28 ... Decoder, 29 ... Baseband signal j of channel j, 30 ... I signal synthesis / data converter, 31 ...
Q signal synthesizer / data converter, 32 ... I signal data complement circuit, 33 ... Q signal data complement circuit.

Claims (2)

[Claims] 1. Means for receiving multiplexed communication signals,
A demodulation device comprising means for squaring the digitally converted data of the communication signal and means for decoding the output. 2. Means for receiving multiplexed communication signals,
Means for estimating higher-order bits truncated from the adjacent data string of the communication signal based on the characteristics of the Gray code;
A demodulation device comprising means for converting the estimated Gray code output into a binary signal.