JPH07211909A - Thin film transistor and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] To easily manufacture a thin film transistor which can operate at high speed, has a small off current, has a small fluctuation in threshold value, and has a large on current. A semiconductor layer 1 in a channel region formed under a gate electrode 58 has a multilayer film structure in which a plurality of hydrogenated amorphous silicon layers 53 and polycrystalline silicon layers 54 are alternately laminated. The semiconductor layer 1 is formed by MBE. The semiconductor layer 2 in the source region formed under the source electrode 55 and the semiconductor layer 3 in the drain region formed under the drain electrode 56 are formed only of a hydrogenated amorphous silicon layer regardless of the multilayer film structure. .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (TFT) used in a contact image sensor, a drive circuit of a liquid crystal display, and the like, and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, JP-A-3-80569 (IP
C; H01L 29/784) has been proposed.

FIG. 4 is a sectional view of an inverted stagger type TFT showing the first embodiment described in the publication. The structure of this TFT is described in column 7, line 12 to column 8, line 15 of the publication.
21 is an insulating substrate made of glass or the like, 22 is tantalum (T
a) a gate electrode, 23 an insulating layer made of an amorphous silicon nitride film (a-SiNx), 24 a semiconductor layer formed by a plasma CVD method or a reactive sputtering method, and 25 a film made of an amorphous semiconductor. Thickness is 50Å
Or less hydrogenated amorphous silicon (a-Si:
H) layer, 26 is a polycrystalline silicon (poly-Si) layer having a film thickness of about 100 Å or less, and 27 is n ⁺ -a-Si or n.
^An ohmic junction layer made of ⁺ -poly-Si, 28 is a source electrode, and 29 is a drain electrode. The characteristic of this TFT structure is that the a-Si: H layer 25 and poly-S are
This is that the semiconductor layers 24 are formed by alternately laminating a plurality of i layers 26. As a result, the actions and effects as described in column 8, line 16 to column 12, line 19 of the publication can be obtained.

FIG. 5 is a sectional view of a stagger type TFT showing a second embodiment described in the publication. The structure of this TFT is described in column 12, line 20 to column 13, line 15 of the publication. 41 is an insulating substrate, 42 is a source electrode made of Ta,
43 is a drain electrode made of Ta, 44 is a semiconductor layer, 4
5 is an a-Si: H layer, 46 is a poly-Si layer, 47 is an insulating layer, and 48 is a gate electrode. Also in this TFT,
A plurality of a-Si: H layers 45 and poly-Si layers 46 are alternately stacked to form a semiconductor layer 44. As a result, the same action and operation as those of the first embodiment shown in FIG. 4 can be obtained, and the source and drain electrodes 42 and 43 are
Is formed on the surface of the insulating substrate 41, each electrode 4
The 2, 43 wirings can be easily formed.

FIG. 6 is a cross-sectional view of a Coplanar type TFT showing a third embodiment described in the publication. This T
The structure of FT is described in column 13, line 16 to column 14, line 12 of the publication. 51 is an insulating substrate, 52 is a semiconductor layer, 53
Is an a-Si: H layer, 54 is a poly-Si layer, 55 is a source electrode, 56 is a drain electrode, 57 is an insulating layer, and 58 is a gate electrode. Also in this TFT, the semiconductor layer 52 is formed by alternately laminating a-Si: H layers 53 and poly-Si layers 54. As a result, the same action and operation as those of the first embodiment shown in FIG. 4 are obtained, and since the semiconductor layer 52 is formed on the flat insulating substrate 51, the film thickness of each layer 53, 54 is uniform. Can be

As described in column 14, line 16 to column 16, line 12 of the publication, each of the above embodiments can be modified. For example, the poly-Si layers 26, 46 and 54 may be replaced with single crystal silicon layers. In that case, the single crystal silicon layer has a more uniform crystal structure than the poly-Si layer, so that the carrier travels smoothly and the operation accuracy of the TFT is improved.

[0007]

In each of the above TFTs, each semiconductor layer (24, 44, 52) is entirely composed of an amorphous semiconductor layer (25, 45, 53) and a poly-Si layer (26, 4).
6, 54) or single crystal silicon layers are alternately laminated to form a multilayer film structure. However, the fact that the entire semiconductor layer has a multilayer film structure does not mean that not only the channel region but also the source region and the drain region have a multilayer film structure. Therefore, there is a problem that the contact resistance in the source region and the drain region increases, carrier movement is restricted, and the on-current decreases.

Further, according to the publication, each semiconductor layer (2
4, 44, 52) are formed by the plasma CVD method or the reactive sputtering method. However, it is difficult to stably form the multilayer film structure as described in the publication by such a method, and it is difficult to put it into practical use without lowering the throughput.

The present invention has been made to solve the above problems, and an object thereof is to provide a thin film transistor capable of high-speed operation, having a small off-current and a small threshold variation, and having a large on-current. To do. Another object of the present invention is to easily manufacture such a thin film transistor.

[0010]

The gist of the invention described in claim 1 is that only the semiconductor layer in the channel region is formed of a superlattice structure film.

According to a second aspect of the present invention, only the semiconductor layer in the channel region is formed of the superlattice structure film, and at least a part of the semiconductor layer in at least one of the source region and the drain region is a superlattice structure. The gist is that it does not have.

According to a third aspect of the present invention, a semiconductor layer in a channel region having a multilayer film structure in which an amorphous semiconductor layer and a polycrystalline silicon layer or a single crystal silicon layer are alternately laminated is formed, and the semiconductor layer is laminated. The gist of the present invention is to have a semiconductor layer having a source region and a drain region having no structure.

According to a fourth aspect of the present invention, a step of forming a superlattice structure film on an insulating substrate, and a step of forming an etching mask so as to cover only a portion corresponding to the channel region of the superlattice structure film. And a step of injecting appropriate ions into the surface of the superlattice structure film to destroy the superlattice structure in a portion corresponding to at least one of the source region and the drain region.

According to a fifth aspect of the present invention, a semiconductor layer having a multilayer film structure in which an amorphous semiconductor layer and a polycrystalline silicon layer or a single crystal silicon layer are alternately laminated on an insulating substrate is formed. And a step of forming an etching mask so as to cover only a portion corresponding to the channel region of the semiconductor layer, and implanting silicon ions into the surface of the semiconductor layer, and at least one of the source region and the drain region. The gist of the present invention is to have a step of amorphizing the corresponding portion.

[0015]

According to the first or second aspect of the present invention, since the contact resistance in the source region or the drain region does not increase and carrier movement is not restricted, the on-current can be increased.

According to the third aspect of the invention, since the semiconductor layer in the channel region has the multilayer film structure, high-speed operation is possible, the off current is small, and the threshold fluctuation is small.
In addition, since the semiconductor layers in the source region and the drain region do not have a stacked structure, contact resistance in the source region or the drain region does not increase and carrier movement is not restricted, so that the on-state current can be increased.

According to the fourth aspect of the invention, the thin film transistor according to the second aspect can be easily manufactured by a general and simple process of forming an etching mask and implanting ions.

According to the invention of claim 5, the thin film transistor of claim 3 can be easily manufactured by a general and simple process of forming an etching mask and implanting ions.

[0019]

Embodiments of the present invention will now be described with reference to the drawings. In each embodiment, the same components as those in the conventional example shown in FIGS. 4 to 6 have the same reference numerals, and detailed description thereof will be omitted.

(First Embodiment) FIG. 1 is a sectional view of a coplanar TFT showing a first embodiment of the present invention. The difference between the conventional example shown in FIG. 6 and this embodiment is as follows.

The semiconductor layer 1 in the channel region formed below the gate electrode 58 is a-Si:
It has a multilayer film structure in which a plurality of H layers 53 and poly-Si layers 54 are alternately laminated.

The semiconductor layer 2 in the source region formed below the source electrode 55 and the semiconductor layer 3 in the drain region formed below the drain electrode 56 are formed of only the a-Si: H layer regardless of the multilayer film structure. Has been formed.

To form such a structure, first, M
By BE (Molecular Beam Epitaxy), a-Si: H layer 53 and poly-S are formed on an insulating substrate 51 made of glass or the like.
The i layers 54 are formed alternately. According to MBE, each layer 53, 54 is different from the plasma CVD method or the reactive sputtering method.
Even when the film thickness is as thin as several tens of liters or less, it can be manufactured stably and easily with high throughput. Each layer 5
When the multilayer film structure in which 3, 54 are alternately stacked is completed, only the channel region (semiconductor layer 1) is covered and the source region (semiconductor layer 2) and the drain region (semiconductor layer 3) are exposed. Thus, an etching mask made of photoresist or the like is formed on the surface of the multilayer film structure. Then, silicon ions are implanted into the surface of the multilayer film structure.
Then, the multilayer film structure of each semiconductor layer 2 and 3 collapses and becomes amorphous, and each semiconductor layer 2 and 3 comes to be formed only from an a-Si: H layer. On the other hand, the multilayer film structure of the semiconductor layer 1 is retained. Next, the source electrode 55 and the drain electrode 56 made of Ta are formed on each of the semiconductor layers 2 and 3.
Subsequently, an insulating layer 57 made of a-SiNx is formed, and a gate electrode 58 made of Ta is formed on the insulating layer 57 to form a TFT.
Is completed.

As described above, in this embodiment, only the multilayer film structure of the channel region, which is involved in the operation and effect of the conventional example, is left, and the source region and the drain region are formed only by the amorphous layer. Become. Therefore, according to this embodiment, the contact resistance in the source region and the drain region is reduced while maintaining the operation and effect of the conventional example shown in FIG. 6 (high-speed operation is possible, off-current is small, and threshold fluctuation is small). Therefore, the on-current can be increased. Further, since the semiconductor layer 1 is formed by MBE,
The manufacturing becomes easier as compared with the conventional example using the plasma CVD method or the reactive sputtering method.

(Second Embodiment) FIG. 2 is a sectional view of a stagger type TFT showing a second embodiment of the present invention. The difference between the conventional example shown in FIG. 5 and this embodiment is as follows.

The semiconductor layer 4 in the channel region formed below the gate electrode 48 is a-Si:
It has a multilayer film structure in which a plurality of H layers 45 and poly-Si layers 46 are alternately laminated.

The semiconductor layer 5 in the source region formed above the source electrode 42 and the semiconductor layer 6 in the drain region formed above the drain electrode 43 are formed of only the a-Si: H layer regardless of the multilayer structure. Has been formed.

To form such a structure, first, the source electrode 42 and the drain electrode 4 are formed on the insulating substrate 41.
3 is formed. Next, the a-Si: H layer 45 and the poly- are formed on the insulating substrate 41 and the electrodes 42 and 43 by MBE.
The Si layers 46 are formed alternately. When the multilayer film structure in which the layers 45 and 46 are alternately laminated is completed, only the channel region (semiconductor layer 4) is covered and the source region (semiconductor layer 5) and the drain region (semiconductor layer 6) are exposed. As described above, an etching mask made of photoresist or the like is formed on the surface of the multilayer film structure. Then, silicon ions are implanted into the surface of the multilayer film structure. Next, the insulating layer 47 is formed on each of the semiconductor layers 4 to 6, and the gate electrode 58 is formed on the insulating layer 47 to complete the TFT.

Also in this embodiment, as in the first embodiment,
The ON current can be increased while maintaining the operation and effect of the conventional example shown in FIG. Further, since the semiconductor layer 4 is formed by MBE, the manufacturing becomes easier as compared with the conventional example.

(Third Embodiment) FIG. 3 is a sectional view of an inverted stagger type TFT showing a third embodiment of the present invention. The difference between the conventional example shown in FIG. 4 and this embodiment is as follows.

The semiconductor layer 7 in the channel region formed above the gate electrode 22 is formed of a-Si:
It has a multilayer film structure in which a plurality of H layers 25 and poly-Si layers 26 are alternately laminated.

The semiconductor layer 8 in the source region formed below the source electrode 28 and the semiconductor layer 9 in the drain region formed below the drain electrode 29 are formed of only the a-Si: H layer regardless of the multilayer film structure. Has been formed.

To form such a structure, first, the gate electrode 22 is formed on the insulating substrate 21. Next, the insulating layer 23 is formed on the insulating substrate 21 and the gate electrode 22. Then, a- is formed on the insulating layer 23 by MBE.
The Si: H layers 25 and the poly-Si layers 26 are formed alternately. When the multilayer film structure in which the layers 25 and 26 are alternately laminated is completed, only the channel region (semiconductor layer 7) is covered and the source region (semiconductor layer 8) and the drain region (semiconductor layer 9) are exposed. As described above, an etching mask made of photoresist or the like is formed on the surface of the multilayer film structure. Then, silicon ions are implanted into the surface of the multilayer film structure. Next, an ohmic junction layer 27 is formed on each of the semiconductor layers 4 to 6 so as to be divided into two above the gate electrode 22. Subsequently, the source electrode 28 is formed on one side of the ohmic junction layer 27, and the drain electrode 29 is formed on the other side, thereby completing the TFT.

Also in this embodiment, as in the first embodiment,
The ON current can be increased while maintaining the operation and effect of the conventional example shown in FIG. Further, since the semiconductor layer 7 is formed by MBE, the manufacturing becomes easier as compared with the conventional example.

The above embodiments may be carried out as follows. 1) The poly-Si layers 26, 46 and 54 may be replaced with single crystal silicon layers. In that case, the single crystal silicon layer is po
Since the crystal structure is more uniform than that of the ly-Si layer, the carrier travels smoothly and the operation accuracy of the TFT is improved.

2) The a-Si: H layers 25, 45, 53 (including the semiconductor layers 2, 3, 5, 6, 8, 9) have a band gap larger than that of single crystal silicon or poly-Si (for example, Amorphous silicon carbide (a-SiC) or amorphous silicon germanium (a-SiGe) or other amorphous semiconductor) may be used instead.

3) The semiconductor layers 2, 3, 5, 6, 8, 9 may be replaced with a single crystal silicon layer or a poly-Si layer. In this case, laser annealing is performed after the implantation of silicon ions, so that the semiconductor layers 2, 3, 3, which have once been made amorphous, can be obtained.
5, 6, 8 and 9 may be single crystal silicon layers or poly-Si layers.

3) The insulating substrates 21, 41 and 51 may be formed using a material other than glass (eg, quartz or sapphire). 4) Each electrode 11, 48, 58, 28, 29, 42, 4
3, 55 and 56 are materials other than Ta (for example, chromium (C
r), a metal material such as aluminum (Al) or tungsten (W), or poly-Si doped with impurities) may be used.

5) The insulating layers 23, 47 and 57 are made of a-SiN.
It may be formed using a material other than x (for example, an amorphous silicon oxide film (a-SiO ₂ ), etc.). 6) The same multilayer film structure as the channel region may be left in either the source region or the drain region. Further, a part of the source region or the drain region may have the same multilayer film structure as the channel region.
In that case, the effect of increasing the on-current is lower than that of each of the above-described embodiments, but can be higher than that of the conventional example.

7) As the etching mask for ion implantation, any material may be used as long as it blocks ions and can be removed after the ion implantation. 8) The semiconductor layers 1, 4, and 7 are formed of an amorphous semiconductor layer and poly-Si.
Instead of forming a multilayer film structure in which layers or single crystal silicon layers are alternately stacked, an appropriate superlattice structure film is replaced. The combination of the well layer and the barrier layer forming the superlattice structure film is disclosed in JP-A-63-28073, column 8, a combination of aluminum arsenic (AlAs) and gallium arsenide (GaAs), and the like. , It can be anything.

[0041]

As described above in detail, according to the present invention, it is possible to provide a thin film transistor which can operate at high speed, has a small off-current, a small threshold variation, and a large on-current. Further, there is also an excellent effect that such a thin film transistor can be easily manufactured.

[Brief description of drawings]

FIG. 1 is a sectional view of a TFT of a first embodiment embodying the present invention.

FIG. 2 is a sectional view of a TFT of a second embodiment embodying the present invention.

FIG. 3 is a sectional view of a TFT of a third embodiment embodying the present invention.

FIG. 4 is a cross-sectional view of a conventional TFT.

FIG. 5 is a cross-sectional view of a conventional TFT.

FIG. 6 is a cross-sectional view of a conventional TFT.

[Explanation of symbols]

1, 4, 7 semiconductor layer in channel region 2, 5, 8 semiconductor layer in source region 3, 6, 9 semiconductor layer in drain region 21, 41, 51 insulating substrate 25, 45, 53 hydrogen as amorphous semiconductor layer Amorphous silicon layer 26,46,54 polycrystalline silicon layer

Claims (5)

[Claims] 1. A thin film transistor in which only a semiconductor layer in a channel region is formed of a superlattice structure film. 2. A semiconductor layer only in the channel region is formed of a superlattice structure film, and at least a part of the semiconductor layer in at least one of the source region and the drain region does not have a superlattice structure. Thin film transistor. 3. A semiconductor layer in a channel region having a multilayer film structure in which an amorphous semiconductor layer and a polycrystalline silicon layer or a single crystal silicon layer are alternately stacked, a source region not having a stacked structure, and A thin film transistor comprising a semiconductor layer in a drain region. 4. A step of forming a superlattice structure film on an insulating substrate, a step of forming an etching mask so as to cover only a portion corresponding to a channel region of the superlattice structure film, 3. A method of manufacturing a thin film transistor according to claim 2, further comprising the step of implanting appropriate ions into the surface to destroy the superlattice structure in a portion corresponding to at least one of the source region and the drain region. . 5. A step of forming a semiconductor layer having a multilayer film structure in which an amorphous semiconductor layer and a polycrystalline silicon layer or a single crystal silicon layer are alternately laminated on an insulating substrate, and the semiconductor layer. A step of forming an etching mask so as to cover only a portion corresponding to the channel region, and implanting silicon ions into the surface of the semiconductor layer so that the portion corresponding to at least one of the source region and the drain region is amorphous. 4. The method for manufacturing a thin film transistor according to claim 3, further comprising: