JPH0722310A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve the high frequency gain characteristics of MMIC by a method wherein an air gap is provided under the T-shaped gate of the FET in a semiconductor MMI with an MIM capacitor, and the capacitance between a gate and a drain is reduced. CONSTITUTION:An aperture part 4 is formed by etching the gate formation region of the silicon oxide film 3 formed on a semiconductor substrate 1, a T-shaped gate electrode 6 and a capacitor lower electrode 7 are formed by depositing a gold film on the aperture part 4 and the gold film is patterned, and the silicon oxide film 3 is removed by wet etching. Then, after a silicon nitride film 8 has been formed, the FET part and the capacitor lower electrode 7 are buried and flattened by a silicon oxide film 10, and a capacitor upper electrode 12 is formed through the intermediary of a dielectric film 11. Then, an air gap is formed under the T-shaped gate electrode by selectively wet- etching the silicon oxide film around the T-shaped gate electrode 6 using the silicon nitride film 8 as an etching stopper.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of manufacturing a microwave semiconductor integrated circuit.

[0002]

2. Description of the Related Art A compound semiconductor FET is widely used as a microwave band device because it has a higher electron mobility than silicon. In particular, compound semiconductor microwave integrated circuits (microwave monolithic ICs: hereinafter referred to as MMICs) are advanced by forming passive elements such as resistors, capacitors, and inductances on the same substrate as FETs. These functions can be realized at a low price, and their importance has been increasing in recent years.

2 (a) to 2 (d) are sectional views of a semiconductor chip showing the order of steps for explaining a conventional method for manufacturing a semiconductor integrated circuit.

First, as shown in FIG. 2A, after oxygen is selectively ion-implanted into the surface of a semiconductor substrate 1 having an active layer formed on a semi-insulating GaAs substrate to form an insulating layer 2. The surface of the active layer of the semiconductor substrate 1 other than the insulating layer 2 is selectively etched to form recesses. Next, the silicon oxide film 3 is deposited on the surface of the semiconductor substrate 1 including the recess, and the silicon oxide film 3 on the recess is selectively etched to form the opening 4.

Next, as shown in FIG. 2B, the opening 4
A tungsten silicide film 5 for forming a Schottky junction with the semiconductor substrate 1 is deposited on the surface of the silicon oxide film 3 containing silicon, a gold film is deposited on the tungsten silicide film 5 and patterned, and a T-shaped gate on the recess is formed. Each of the electrode 6 and the capacitor lower electrode 7 on the insulating layer 2 is formed simultaneously.

Next, as shown in FIG. 2C, the tungsten silicide film 5 is etched and removed using the gate electrode 6 and the capacitor lower electrode 7 as a mask, and then the silicon oxide film 3 is selectively etched. Contact holes are formed, and source / drain electrodes 9 are formed on the surface of the active layer exposed in the contact holes.

Next, as shown in FIG. 2D, a silicon oxide film 10 is thickly deposited as an interlayer insulating film on the entire surface including the gate electrode 6 and the capacitor lower electrode 7 to planarize the upper surface, and then the capacitor lower electrode. Silicon oxide film 10 on 7
Is etched to form an opening, and a dielectric film 11 made of a silicon nitride film is deposited on the surface including the opening. Next, the silicon oxide film 10 on the source / drain electrodes 9 is etched to form through holes, and a gold film is selectively formed in each of the openings and the through holes on the capacitor lower electrode 7 to form the capacitor upper electrode 12. And wiring 1
3 is formed to form a semiconductor integrated circuit in which the FET and the passive element are formed on the same substrate.

[0008]

Since the conventional semiconductor integrated circuit has a structure in which the eaves lower portion of the T-shaped gate of the FET is filled with the insulating film, the amount of the dielectric constant of the insulating film is caused. Only, the gate-drain capacitance Cgd of the FET increases. The high frequency gain of the FET is the maximum effective gain (MA
G),

[0009]

Therefore, there has been a problem that the high frequency gain is reduced by the increase of Cgd.

[0011]

A semiconductor integrated circuit of the present invention comprises a step of selectively forming an insulating layer on a surface of a semiconductor substrate and selectively forming a recess in a region other than the insulating layer, A step of forming a first insulating film on a surface including an insulating layer and a recess and selectively etching the first insulating film on the recess to form an opening for forming a gate electrode; A step of sequentially depositing a conductive film and a metal film for forming a Schottky junction with the semiconductor substrate on the surface including the T-shaped gate electrode on the opening and the conductive film and the conductive film. A step of simultaneously forming a capacitor lower electrode on the insulating layer; a step of etching and removing the first insulating film using the capacitor lower electrode as a mask to form a space under the eaves of the gate electrode. Forming a second insulating film on the surface of the semiconductor substrate including the recess, by selectively etching the second insulating film of the gate electrode near the contact holes are formed source in the contact hole
A step of forming a drain electrode; a step of depositing a third insulating film on the surface including the gate electrode and the capacitor lower electrode to planarize the upper surface; and a step of selectively forming the third insulating film on the capacitor lower electrode. A step of etching an opening to form an opening and forming a dielectric film on the surface including the opening;
The dielectric film and the third insulating film on the source / drain electrodes are selectively sequentially etched to form through holes, and metal films are formed in the openings on the capacitor lower electrodes and the through holes on the source / drain electrodes, respectively. Selectively forming the capacitor upper electrode and the source / drain wiring, and selectively using the second insulating film as an etching stopper for the dielectric film and the third insulating film in the region including the gate electrode. And then sequentially removing it to form an air gap under the eaves of the gate electrode.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIGS. 1A to 1D are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 1A, an n-type GaAs layer is grown on a semi-insulating GaAs substrate by the MBE (molecular beam epitaxial) method to select an active layer on the surface of the semiconductor substrate 1. Specifically, oxygen is ion-implanted to form the insulating layer 2 to partition the element formation region, and the surface of the element formation region is selectively etched to form a recess. Next, the silicon oxide film 3 is deposited on the surface of the semiconductor substrate 1 including the recess, and the silicon oxide film 3 on the recess is selectively etched by RIE (activated ion etching) to form the opening 4.

Next, as shown in FIG. 1B, the opening 4
A tungsten silicide film 5 is deposited on the silicon oxide film 3 containing silicon to form a conductor film for obtaining a Schottky junction with the substrate 1 in the opening 4. Next, a gold film is deposited on the tungsten silicide film 5 and patterned to form the T-shaped gate electrode 6 on the recess and the capacitor lower electrode 7 on the insulating layer 2 at the same time.

Next, as shown in FIG. 1C, the tungsten silicide film 5 is anisotropically etched using the gate electrode 6 and the capacitor lower electrode 7 as a mask, and then wet oxidation is performed to oxidize the lower portion of the gate electrode 6 including the eaves. The silicon film 3 is removed. Next, a silicon nitride film 8 having a selectivity of 7 times that of wet etching of a silicon oxide film is deposited on the surface of the substrate 1 including the recess and the surface of the capacitor lower electrode 7 to a thickness of 100 nm and patterned, Form a contact hole. Next, the source / drain electrodes 9 which make ohmic contact with the active layer in the contact holes are formed.

Next, as shown in FIG. 1D, a silicon oxide film 10 is deposited to a thickness of 1.5 μm on the entire surface including the gate electrode 6 and the capacitor lower electrode 7 to planarize the upper surface, Silicon oxide film 10 on capacitor lower electrode 7
Are selectively etched to form an opening, and a dielectric film 11 made of a silicon nitride film is formed on the surface including the opening. Next, the dielectric film 1 on the source / drain electrodes 9
1 and the silicon oxide film 10 are selectively and sequentially anisotropically etched to form through holes, and a gold film is selectively formed on each of the openings and the through holes on the capacitor lower electrode 7 to form the capacitor upper electrode 12. And wiring 13
To form each of. Next, the dielectric film 11 in the region including the gate electrode 6 is selectively dry-etched, and then the silicon oxide film 10 is wet-etched with buffered hydrofluoric acid. At this time, the silicon nitride film 8 serves as an etching stopper and the silicon oxide film 10 below the eaves of the gate electrode 6.
Is also removed, and an air gap can be formed in the lower part of the eaves.

Electrode amplification MMIC formed in this way
As for the characteristics, the linear gain at 30 GHz was 12 dB and the power output was 400 mW. On the other hand, in the conventional method, the linear gain when the power output was 400 mW was 8 dB, and a significant improvement in characteristics was obtained.

As a semiconductor substrate, semi-insulating GaA is used.
The active layer may be formed by implanting Si ions into the s substrate.

[0020]

As described above, according to the present invention, the FET having the air gap below the eaves of the T-shaped gate electrode is M.
A semiconductor M that can be formed at the same time as the IM capacitor and has excellent characteristics in the high frequency band, particularly in the millimeter wave band
It has an effect that MIC can be realized.

[Brief description of drawings]

1A to 1D are cross-sectional views showing a process sequence for explaining an embodiment of the present invention.

FIG. 2 is a sectional view showing the order of steps for explaining a conventional method for manufacturing a semiconductor integrated circuit.

[Explanation of symbols]

 1 Semiconductor Substrate 2 Insulating Layer 3, 10 Silicon Oxide Film 4 Opening 5 Tungsten Silicide Film 6 Gate Electrode 7 Capacitor Lower Electrode 8 Silicon Nitride Film 9 Source / Drain Electrode 11 Dielectric Film 12 Capacitor Upper Electrode 13 Wiring

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 27/04 27/095 7376-4M H01L 29/80 E

Claims (2)

[Claims] 1. A step of selectively forming an insulating layer on a surface of a semiconductor substrate and selectively forming a recess in a region other than the insulating layer; and a step of forming a recess on the surface including the insulating layer and the recess. Forming an insulating film and selectively etching the first insulating film on the recess to form an opening for forming a gate electrode; and forming a Schottky junction with the semiconductor substrate on a surface including the opening. For sequentially depositing a conductive film and a metal film, and patterning the metal film and the conductive film sequentially to simultaneously form a T-shaped gate electrode on the opening and a capacitor lower electrode on the insulating layer. A step of etching and removing the first insulating film by using the capacitor lower electrode as a mask to form a space under the eaves of the gate electrode, and a second step on the surface of the semiconductor substrate including the recess. Forming an insulating film, forming a contact hole by selectively etching the second insulating film in the vicinity of the gate electrode, and forming a source / drain electrode in the contact hole, the gate electrode and the capacitor A step of depositing a third insulating film on the surface including the lower electrode to planarize the upper surface, and a step of selectively etching the third insulating film on the lower electrode of the capacitor to form an opening. A step of forming a dielectric film on the surface including the dielectric film on the source / drain electrodes and a third step.
The insulating film is selectively and sequentially etched to form a through hole, and a metal film is selectively formed in the opening on the capacitor lower electrode and the through hole on the source / drain electrode to form a capacitor upper electrode and a source / drain electrode, respectively. A step of forming a drain wiring, and using the second insulating film as an etching stopper, the dielectric film and the third insulating film in the region including the gate electrode are selectively and sequentially etched and removed, and the eaves lower part of the gate electrode is removed. And a step of providing an air gap in the semiconductor integrated circuit. 2. The second insulating film is a silicon nitride film,
The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein the third insulating film is a silicon oxide film.