JPH0722410B2 - Phase matching method of color subcarrier signal of digital VTR and digital composite color video signal - Google Patents

Description

TECHNICAL FIELD The present invention relates to a digital VTR for recording / reproducing a composite color video signal and a phase alignment method for color subcarrier signals of a digital composite color video signal.

[Background Art and Problems] In a conventional digital VTR, for example, a VTR for recording a digital composite color video signal according to the NTSC system, data to be recorded is recorded, for example, in data that has been subjected to interleave processing for each field. After various kinds of processing such as addition of an apology correction code are performed, an address is added to each block of data at the time of interleaving and the data is recorded on the recording medium.

At the time of reproduction, since the color framing is completed in 4 fields based on the address to which the data for each block reproduced from the recording medium is added, the color framing is stored in a memory having a capacity of 4 fields and the data for 4 fields After all the data is stored in the memory, the original data is obtained by reading the data from, for example, the head address of the memory, and a reproduction process such as an error correction process is performed on the original data to reproduce the digital composite color video signal. I have to.

Further, at the time of reproduction other than the reproduction at the normal speed described above, for example, at the time of so-called high-speed reproduction, the recording signal recorded on the recording medium cannot be continuously reproduced, and only a part of data is obtained. Therefore, the obtained small amount of data is written in the memory having the capacity of 4 fields described above based on the address added to the data. That is, since the previously stored data remains in the memory, if the obtained data is written in the memory, the previous data remains in the area of the address corresponding to the unobtained data. If the memory is read out after the writing of the fields is completed, one reproduced image can be obtained although the completely reproduced image cannot be obtained.

However, the use of the four-field memory significantly increases the distance between the devices, and the response becomes slower due to the increased capacity.

Therefore, there is a demand for the memory to have a capacity as small as one field or two fields. If the capacity of the memory is reduced, it is possible to reduce the number of devices, and the response speed can be increased as the capacity is reduced.

However, as is well known, in the digital composite color video signal, the phase of the color subcarrier signal is inverted depending on the field. This situation will be described with reference to FIGS. 4 and 5.

The phase of the color subcarrier signal of the NTSC system color television signal with respect to the horizontal synchronizing signal in each horizontal scanning line (hereinafter referred to as a line) is shown in FIGS. As shown in FIG. Here, the phase of the color subcarrier signal in the state as shown in FIG. 5A (the phase in which the first color subcarrier signal after the horizontal synchronizing signal rises in the positive direction) is called the positive phase. Represented by "N", the phase of the color subcarrier signal in the state shown in FIG. 5B (the phase in which the color subcarrier signal of the first wave after the horizontal synchronization signal falls in the negative direction) is reversed. Call it "A"
It is represented by.

FIG. 4 shows the phase of the color subcarrier signal inverted for each line in each field. Fourth
FIG. A shows the first field, FIG. 4B shows the second field, FIG. 4C shows the third field, and FIG. 4D shows the fourth field. The line marked with "*" in FIG. 4 indicates the head line on which the color subcarrier signal of that field is superimposed, and the head line of the first field is the normal phase N and the head of the second field. Line is reverse phase I, 3rd
The leading line of the field is the reverse phase I, and the leading line of the fourth field is the normal phase N.

Here, the positive phase N and the negative phase I indicated by the leading line in each field will be hereinafter referred to as the phase of the color subcarrier signal. Thus, the phase of the color subcarrier signal is the first
From the field to the fourth field, the phase changes from the normal phase N, the negative phase 1, the negative phase I, and the normal phase N, and the color subcarrier signal is generated between the first field and the second field and between the third field and the fourth field. The phase of is reversed. Based on the phase property of the color subcarrier signal, the phase of the color subcarrier signal of the digital composite color video signal similarly changes.

Therefore, if a memory with a capacity of 1 field is used, all the data can be obtained at the time of reproduction, but there is no problem. However, at the time of high-speed reproduction described above, all the data to be reproduced cannot be obtained. The data of the previous field and the data of the current field (data that can be obtained during high-speed reproduction) are mixed in the storage area of the memory after writing the data for the field in the memory.

As described above, the phase of the color subcarrier signal is inverted depending on the field. Therefore, if the image is reproduced from the data read from the memory in which the data having different phases of the color subcarrier signal are mixed, the color reproduction cannot be normally performed. Will end up.

[Object of the Invention] The present invention has been made in consideration of the above points, and minimizes the capacity of the memory provided in the reproduction circuit system to reduce the cost and improve the memory response speed, and to completely store data. An object of the present invention is to propose a phase matching method for a color subcarrier signal of a digital VTR and a digital composite color video signal, which can improve color reproducibility even in reproduction that cannot be reproduced, for example, in high speed reproduction.

[Means for Solving the Problems] The first invention is to provide a memory (44), (45) for storing a digital composite color video signal to be recorded, and at least a synchronization obtained from the digital composite color video signal to be recorded. Control for indicating various timing signals based on the signal and the leading line of the digital composite color video signal to be recorded where the phase of the color subcarrier signal is in phase over successive fields of the digital composite color video signal to be recorded Timing generating means (5) for generating a signal and a count operation based on the control signal from the timing generating means (5) to generate an address signal for supplying to the memories (44), (45). Address signal generating means (46) and an address from this address signal generating means (46). Based on the control means (47), (48), (49), (5) for controlling the writing or reading timing of the digital composite color video signal to the memories (44), (45) based on
0) and (51), and signal processing means (3) for performing signal processing for recording on the digital composite color video signals read from the memories (44) and (45).
(6), (7a), (7b), ... (20a), (20b),
Ha and Hb are provided, and the signal processing means (3), (6),
(7a), (7b), ... (20a), (20b), a digital VTR adapted to record the output signals from Ha and Hb on a recording medium TP.

A second aspect of the present invention is that the phase of the color subcarrier signal is in phase over successive fields of the digital composite color video signal to be recorded based on a synchronization signal obtained from the digital composite color video signal to be recorded. A control signal indicating the top line of the digital composite color video signal to be recorded is obtained, and the phase of the color subcarrier signal of each field of the digital composite color video signal to be recorded is positive or negative based on this control signal. Phase adjustment method of the color subcarrier signal of the digital composite color video signal in which the phase of the color subcarrier signal of each field of the digital composite color video signal to be recorded is made uniform by outputting when either one becomes Is.

[Operation] According to the first invention described above, at least various timing signals based on a synchronization signal obtained from a digital composite color video signal to be recorded, and color over continuous fields of the digital composite color video signal to be recorded. Timing generating means (5) outputs a control signal indicating the leading line of the digital composite color video signal to be recorded, where the subcarrier signals are in phase with each other.
The address signal generating means (46) generates an address signal for performing the counting operation based on the control signal and supplying it to the memories (44) and (45). ) Control means (47), (48), (49), (50), (51) for writing or reading the digital composite color video signal to or from the memories (44), (45) based on the address from Signal processing means (3), (6), (7a), (7) for controlling the digital composite color video signal read from the memories (44), (45) by the signal processing means for recording.
b), ... (20a), (20b), Ha, Hb, and the signal processing means (3), (6), (7a), (7b) ,.
-Record the output signals from (20a), (20b), Ha, and Hb on the recording medium TP. As a result, when one field memory is used on the playback side and the high speed playback such as shuttle playback is performed, even if the data of the previous field and the data of the current field are mixed in the field memory, the color subcarrier signal is generated. The phases of can be matched.

According to the second aspect of the invention described above, the phase of the color subcarrier signal is in-phase over the continuous fields of the digital composite color video signal to be recorded based on the synchronization signal obtained from the digital composite color video signal to be recorded. A control signal indicating the leading line of the digital composite color video signal to be recorded is obtained, and the phase of the color subcarrier signal of each field of the digital composite color video signal to be recorded is positive based on this control signal. Alternatively, by outputting at either one of the opposite phases, the phases of the color subcarrier signals of the respective fields of the digital composite color video signal to be recorded are aligned. As a result, when one field memory is used on the playback side and the high speed playback such as shuttle playback is performed, even if the data of the previous field and the data of the current field are mixed in the field memory, the color subcarrier signal is generated. The phases of can be matched.

[Embodiment] An embodiment of the method of phasing the color subcarrier signals of the digital VTR and the digital composite color video signal according to the present invention will be described in detail below. 1 and 2
The figure shows the recording system and the reproducing system of the digital VTR, and with reference to FIGS. 1 and 2 below, this digital VTR will be described.
The configuration of will be described. First, prior to the description of the recording system and the reproducing system of FIGS. 1 and 2, the configuration of the rotary magnetic head device will be described. A rotary magnetic head for recording and a rotary magnetic head for reproduction are attached to the rotating upper drum of a tape guide drum composed of a fixed lower drum and a rotating upper drum at an angular interval of, for example, 120 °. Each of the recording rotary magnetic head and the reproducing rotary magnetic head is composed of a pair of closely arranged rotary magnetic heads (head chips) having different azimuths of the gaps. Then, on this tape guide drum, a magnetic tape, for example, 330
It is designed to be obliquely wound and guided with a wrapping angle of °.

Further, a pair of recording magnetic heads for recording forms a pair of inclined recording tracks that are close to each other per 1/2 field,
Therefore, the digital video signal is recorded on the magnetic tape so as to form two pairs of inclined recording tracks per field. Then, the digital video signals of each pair of inclined recording tracks recorded in this manner can be reproduced by the pair of reproducing rotary magnetic heads.

First, the recording circuit system of the digital VTR will be described with reference to FIG. (1) is an input terminal for an analog composite color video signal. The analog composite color video signal from the input terminal (1) is supplied to the clamp circuit (3) and the sync separation circuit (4) via the low pass filter (2). The pedestal clamp level detection signal from the sync separation circuit (4) is supplied to the clamp circuit (3). The horizontal and vertical sync signals and the color subcarrier signals from the sync separation circuit (4) are supplied to the timing signal generation circuit (5), respectively. Here, the timing signal generation circuit (5) generates, for example, various timing signals based on the horizontal and vertical synchronization signals from the sync separation circuit (4), and also generates horizontal and vertical synchronization signals and color subcarrier signals or horizontal and vertical synchronization signals. Based on the vertical synchronizing signal, a signal indicating the head line of the field to be recorded and a timing signal are generated. This timing signal is generated on a line such that the phase of the color subcarrier signal is in phase, either positive or negative, over the successive fields. The timing signal is supplied to an address counter (46) described later with reference to FIG. 3 as a reset pulse, a count enable pulse, or the like. Further, the composite color video signal from the clamp circuit (3) is supplied to the A / D converter (6) and converted into a parallel 8-bit digital composite color video signal (one line consists of 768 sample data). At the same time, by channel coding, one line is divided into two channels so as to consist of 384 samples of data and supplied to the shuffling circuits (7a) and (7b) of each channel.

Each of the shuffling circuits (7a) and (7b) has a memory for, for example, 20 to 30 lines, and a timing signal from the timing signal generating Rio (5) described above allows the timing of writing a signal to the memory. Controlled. The configurations of these shuffling circuits (7a) and (7b) will be described in detail later.

The outputs from the shuffling circuits (7a) and (7b) are supplied to the time axis compression circuits (8a) and (8b), respectively. Each of these time axis compression circuits (8a) and (8b) has a memory having a capacity of, for example, 1/6 field, and a shuffling circuit (7a),
The digital video signal from (7b) into its memory, for example
Time axis compression is performed by writing with a 7 MHz clock signal and reading with an 8 MHz clock signal.

The outputs of the time axis compression circuits (8a) and (8b) are the CRC code signal addition circuits (9a) and (9b), the vertical parity check code signal addition circuits (10a) and (10b), and the block address addition circuit (1 (Add block address for every 6 lines) (11a) and (11b), through the horizontal parity check code signal adding circuits (12a) and (12b),
When a bit error exists in the MSB, it is supplied to 8-8 conversion circuits (13a) and (13b) for reducing the amount of the error, respectively. The outputs of the 8-8 conversion circuits (13a) and (13b) are the block synchronization signal adding circuits (14a) and (14), respectively.
b), preamble and postamble addition circuit (15a)
And (15b) and the delay compensation circuits (16a) and (16b) in order, and are supplied to the parallel-to-serial conversion circuits (17a) and (17b), respectively.

The outputs of the parallel-to-serial conversion circuits (17a) and (17b) are supplied to scramble circuits (18a) and (18b) for averaging the numbers of 1s and 0s of bits, respectively. The outputs of the scramble circuits (18a) and (18b) are delayed by the delay compensation circuit {having a delay amount smaller than that of the delay compensation circuits (16a) and (16b)} (19a) and (19b), respectively. It is supplied to the ECL circuits (20a) and (20b), and the outputs thereof are supplied to the recording rotary magnetic heads Ha and Hb, respectively, and are recorded on the magnetic tape TP.

Next, the reproducing circuit system of the digital VTR will be described with reference to FIG. The digital video signal recorded on the magnetic tape TP is reproduced by the rotary magnetic heads H'a and H '.
PLL (Phase Locked Loop) for detecting a clock signal and a block synchronization signal detection circuit (23a) after being reproduced by b through amplifiers (22a) and (22b).
And (23b) respectively. The outputs of the PLL and the block synchronization signal detection circuits (23a) and (23b) are supplied to the serial-parallel conversion circuits (24a) and (24b) to be converted into 8-bit parallel digital signals, and then the block synchronization signals and the blocks. It is supplied to the address signal reproducing circuits (25a) and (25b), respectively. If the block address is reproduced, the address of each sample data is also known based on it. The outputs of the reproduction circuits (25a) and (25b) are the 8-8 inverse conversion circuit (26
It is supplied to the horizontal error correction circuits (27a) and (27b) through a) and (26b), respectively. Horizontal error correction circuit (27a)
The outputs of and (27b) are vertical error correction circuits (28a) and (28
b) respectively.

The outputs of the vertical error correction circuits (28a) and (28b) are supplied to the error detection circuits (30a) and (30b) via the switching means (29a) and (29b). During shuttle playback (variable speed playback), horizontal error correction circuits (27a) and (2
The output of 7b) is directly supplied to the error detection circuits (30a) and (30b) through the switching circuits (29a) and (29b).

The outputs of the error detection circuits (30a) and (30b) are supplied to the time axis error correction circuit, time axis expansion circuit and deshuffling circuit (31a) and (31b), respectively, and their outputs are deshuffling circuit (32a) and (32b) respectively.

The time axis error correction circuit, the time axis expansion circuit and the deshuffling circuits (31a) and (31b) have a memory having a capacity of, for example, one field, and sample data for one field based on the block address during variable speed reproduction. When the sample data for one field is collected, it is read out and the deshuffling circuits (32a) and (32
It is sent to b). In fact, the same is true during constant speed reproduction. Also, the error detection circuits (30a) and (30b)
The output of is written to the memory with a clock signal of approximately 8 MHz, and is read out with a fixed 7 MHz clock signal to perform time-axis expansion and frequency-modulate the write clock signal according to the time-axis fluctuation, Time axis error correction is performed. Deshuffling circuit (32
Each of a) and (32b) has a memory with a capacity of 1/6 line. The time axis error correction circuit, the time extension circuit / deshuffling circuits (31a) and (31b), and the deshuffling circuits (32a) and (32b) will be described in detail later.

The outputs of the deshuffling circuits (32a) and (32b) are supplied to the mixing circuit (33), channel coded, and then supplied to the error correction circuit (34). Error correction circuit (3
The output of 4) is supplied to the luminance / chromaticity separation circuit and the chromaticity phase normal / inversion control circuit (35). The output of the luminance / chromaticity separation circuit and the chromaticity phase forward / reverse control circuit (35) is supplied to the horizontal and vertical and burst signal addition circuit (37) through the dark clip circuit and limiter circuit (36), and this horizontal The horizontal and vertical synchronizing signals and the burst signal from the synchronizing signal source (38) are added to the digital color video signal in the vertical and burst signal adding circuit (37). The output of the synchronization signal addition circuit (37) is the D / A converter (39).
To the output terminal (41) through the low-pass filter and buffer circuit (40).

Next, a specific configuration of the shuffling circuits (7a) and (7b) in the recording circuit system of FIG. 1 described above will be described with reference to FIG. The channel-coded 8-bit digital composite color video signal from the input terminal (42) is supplied to the memories (44) and (45) and written alternately, and read alternately from the memories (45) and (44). The output digital composite color video signal is output to the output terminal (43). (46) counts the clock signal from the input terminal (46a) when the timing signal from the timing generation circuit (5) described with reference to FIG. 1 via the input terminal (46b) is active. , An address counter for generating an address signal, and the parallel 13-bit address signal from the address counter is commonly supplied to the address selection circuits (48) and (49) and the address encoders (50) and (51). This address counter (4
6) is a timing signal from the timing signal generator (5), the start timing of counting for each field is controlled, and the colors of the first to fourth field signals of the color framing are shown in FIGS. Line signals a to d having the same subcarrier phase, that is, both positive phases N (negative phase I is also possible)
From the memory to the memories (44) and (45) is started. In FIG. 4, VS is a vertical synchronizing signal section and H is a horizontal period.

Parallel 13-bit address signals from the address selection circuits (48) and (49) are supplied to the memories (44) and (45), respectively. In the address selection circuits (48) and (49),
The address signal directly from the address counter (46) and the address signal encoded by the address encoders (50) and (51) are switched, and the switched address signals are stored in the memories (44) and (45), respectively. Supplied.

(47) is a selection control circuit, and this selection control circuit (47)
Is the count value from the address counter (46),
Alternatively, a selection control signal is supplied to the address selection circuits (48) and (49) based on carry or the like, and the address selection circuit (4
8) and (49) select the address signal from the address counter (46) or the encoded address from the address encoder (50), and the address signal from the address counter (46) or the encoded address from the address encoder (51). Is selected, the memory (44) and (45) are written, and a read control signal is supplied to put the memories (44) and (45) into a write state or a read state. Then, when the memory (44) is writing, the memory (45) is in a reading state, and when the memory (45) is writing, the memory (44) is in a reading state. This allows the memory (44) and (45)
A parallel 8-bit digital composite color video signal is written by the address signal from the address counter (46), and is read by the address signal encoded by the address encoders (50) and (51). Shuffling of the video signal is performed. In this case, the first sample data of the line signal in which the phases of the color subcarriers of the first to fourth field signals of the color framing are equal are stored in the memory (44) or (45) as the sample data of address 0 (start address). Written. On the contrary, the digital composite color video signal is written in the memories (44) and (45) by the address signal encoded by the address encoders (50) and (51), which is read from the address counter (46). The digital composite color video signal may be shuffled by being read by the address signal.

Now, the data thus written and read in the memories (44) and (45) are recorded by the recording system described above so as to form inclined tracks on the recording medium TP. Then, at the time of reproduction in which all the data in the field cannot be obtained by the reproduction system, for example, at the time of high-speed reproduction such as so-called shuttle reproduction, for example, the field memories of the circuits (31a) and (31b) shown in FIG. In the above, the data of the previous field and the data that can be obtained at present are mixed, but as described above, the memory (44) and (4
When writing data to 5), it is always written from either I or V data, so that data with different phases of the color subcarrier signals will not be equivalently mixed in the field memory. Therefore, when a reproduced image is obtained based on the data read from the field memory, it is possible to obtain a good color reproducibility.

Thus, in this example, when the digital composite color video signal is stored in the memories (44) and (45), the timing signal from the timing signal generation circuit (5), for example, the phase of the color subcarrier signal is positive. If the color subcarrier signal is stored in the phase, the address counter (46) starts the counting operation when the color subcarrier signal becomes the positive phase. Therefore, as shown in FIG. Is N (normal phase), the second field is I (negative phase), the third field is I (negative phase), and the fourth field is N (normal phase). By changing the timing, the first to fourth fields are all stored from either N or I in the memory (44) or (45), and then read, processed, and recorded on the recording medium. As described above, the data of the previous field and the data of the current field are mixed in the field memory when high-speed playback such as shuttle playback is performed when one field memory is used during playback. Also, since the phases of the color subcarrier signals are the same, it is possible to reproduce a normal color and significantly improve the color reproduction accuracy of the reproduced image.

[Advantages of the Invention] According to the first invention described above, at least various timing signals based on a synchronization signal obtained from a digital composite color video signal to be recorded, and consecutive fields of the digital composite color video signal to be recorded. The timing generation means generates a control signal indicating the leading line of the digital composite color video signal to be recorded, in which the color subcarrier signals are in phase with each other, and the counting operation is performed based on the control signal to perform the memory operation. An address signal for supplying to the memory is generated by the address signal generating means, and the writing or reading timing of the digital composite color video signal to the memory is controlled by the control means based on the address from the address signal generating means, Digital read from Since signal processing for recording the composite color video signal is processed by the signal processing means and the output signal from this signal processing means is recorded on the recording medium TP, one field memory is provided on the reproducing side. When used, when performing high-speed playback such as shuttle playback, even if the data of the previous field and the data of the current field are mixed in the field memory, the phase of the color subcarrier signal can be made to match. There is an effect that a normal color can be reproduced and the color reproducibility of a reproduced image can be significantly improved.

According to the second aspect of the invention described above, the phase of the color subcarrier signal is in-phase over the continuous fields of the digital composite color video signal to be recorded based on the synchronization signal obtained from the digital composite color video signal to be recorded. A control signal indicating the leading line of the digital composite color video signal to be recorded is obtained, and the phase of the color subcarrier signal of each field of the digital composite color video signal to be recorded is positive based on this control signal. Since it is possible to align the phase of the color subcarrier signal of each field of the digital composite color video signal to be recorded by outputting when either the phase or the reverse phase is reached, for example, when applied to a digital VTR. In the case of using, one field memory is used on the playback side. Even if the data of the previous field and the data of the current field are mixed in the field memory when performing high-speed playback such as video playback, the phase of the color subcarrier signal can be made to match. There is an effect that the reproduction can be performed and the color reproducibility of the reproduced image can be significantly improved.

[Brief description of drawings]

1 and 2 are block diagrams showing a recording circuit and a reproducing circuit system, respectively, of an embodiment of a phase matching method of a color subcarrier signal of a digital VTR and a digital composite color video signal according to the present invention, and FIG. FIG. 1 is a block diagram showing a specific structure of the shuffling circuit of the recording circuit system, and FIGS. 4 and 5 are waveform diagrams of video signals used for explaining the present invention. (3) is a clamp circuit, (5) is a timing signal generation circuit, (6) is an A / D converter, (7a) and (7b) are shuffling circuits, and (8a) and (8b) are time axis compression, respectively. Circuit, (9a) and (9b) are CRC code signal adding circuit,
(10a) and (10b) are vertical parity check code signal addition circuits, (11a) and (11b) are block address addition circuits, (12a) and (12b) are horizontal parity check code signal addition circuits, and (13a) ) And (13b) are 8-8 conversion circuits, (14a) and (14b) are block synchronization signal addition circuits, (15a) and (15b) are postamble addition circuits, and (16a) and (16b) are Delay compensation circuits, (17a) and (17b) are parallel-serial conversion circuits,
(18a) and 818b) are scramble circuits, (19a) and (19b) are delay compensation circuits, (20a) and (20b), respectively.
Are TTL and ECL circuits respectively, Ha and Hb are rotary magnetic heads for recording respectively, TP is magnetic tape, (44) and (45) are memories,
(46) is an address counter, (47) is a selection control circuit,
(48) and (49) are address selection circuits, and (50) and (51) are address encoders.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Yoshihiro Murakami Inventor Yoshihiro Murakami 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Sony Corporation (56) References JP-A-55-26781 (JP, A) JP-A-SHO 58-148584 (JP, A) JP-A-57-79784 (JP, A)

Claims (2)

[Claims] 1. A memory for storing a digital composite color video signal to be recorded, various timing signals based on at least a synchronization signal obtained from the digital composite color video signal to be recorded, and the digital composite color video to be recorded. Timing generating means for generating a control signal indicating the leading line of the digital composite color video signal to be recorded, where the phase of the color subcarrier signal is in phase over successive fields of the signal; and the control from the timing generating means. An address signal generating means for generating an address signal for performing a counting operation based on the signal and supplying it to the memory, and writing the digital composite color video signal to the memory based on an address from the address signal generating means, Some Includes a control means for controlling the read timing and a signal processing means for performing a signal processing for recording the digital composite color video signal read from the memory, and records an output signal from the signal processing means. A digital VTR characterized by being recorded on a medium. 2. A recording signal in which the phase of a color subcarrier signal is in phase over successive fields of the digital composite color image signal to be recorded based on a synchronization signal obtained from the digital composite color image signal to be recorded. A control signal indicating the first line of the digital composite color video signal to be recorded is obtained, and based on this control signal, the phase of the color subcarrier signal of each field of the digital composite color video signal to be recorded is either positive or negative. The color subcarrier signal of the digital composite color video signal is characterized in that the phase of the color subcarrier signal of each field of the digital composite color video signal to be recorded is made uniform by outputting at one point. Phase matching method.