JPH0722478A - Probe test apparatus and probe test method - Google Patents

Abstract

PURPOSE:To measure a plurality of semiconductor chips simultaneously regarding the DC characteristics of the semiconductor chips and characteristics containing functionality without increasing testing heads by mounting a specific flexible probe card. CONSTITUTION:An insulating flexible film 40, a plurality of openings 42 formed to the film 40, a plurality of TAB bumps formed around the openings 42, and first and second wiring layers 46, 48, etc., containing each of first and second leads 45, 47 extended from each TAB bump to the periphery of the flexible film 40 are provided. Pads 56 for connecting tester pins set up to the outer peripheral section or outside of the flexible film 40 in response to the TAB bumps and a connecting means mutually connecting the first or second leads 45, 47 extended from TAB pads at the same positions of each opening 42 while bonding the corresponding pads 56 for connecting the tester pins are provided. Such a flexible probe card 16 is mounted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a probe test apparatus and a probe test method, and more particularly to a flexible probe capable of simultaneously performing a probe test of a wafer such as an LSI tester or an IC tester on a plurality of LSIs or ICs. The present invention relates to a probe test device and a probe test method using a card.

[0002]

2. Description of the Related Art As a wafer probe test, input / output characteristics (V _IL , V _IH , V _OL , V _OH ) of semiconductor chips (semiconductor integrated circuits) such as LSI and IC formed on a wafer are used.
DC for measuring DC characteristics such as current and current characteristics (Idds)
A test and a function test for measuring the logic and function of a circuit formed in a semiconductor chip are performed. Such a probe test is currently performed on a printed wiring board having an opening at the center, terminals provided around and around the opening of the printed wiring board, a wiring pattern for connecting these internal and external peripheral terminals, and an opening. This is performed by contacting the tip of the probe with the electrode of the semiconductor chip using a probe card having a probe that is joined to a terminal provided around the inside of the part and has a tip made of a metal needle whose tip is bent at a predetermined angle.

Since such a probe card uses contact metal pins, it is expensive and large in size relative to the size of the semiconductor chip, and it is easy to fail depending on the contact pressure and handling. The problem is that it requires the cost and expertise. In addition, it takes a considerable number of days to repair the probe card, the wafer probe test cannot be performed during that time, and the delivery time may be delayed. Therefore, there is a problem that a predetermined number of expensive probe cards must be held as spares. is there.

Therefore, a flexible probe card that does not use contact metal pins is disclosed in Japanese Patent Laid-Open No. 234067/1990. The flexible probe card disclosed herein uses a flexible printed wiring board in place of the ordinary high-rigidity printed wiring board, and instead of the probe made of a metal needle, two hemispherical shapes are provided at positions facing the electrodes of the semiconductor chip. The bumps are formed. After aligning the electrodes of the semiconductor chip with the bumps of the flexible probe card, the bumps of the flexible probe card are pressed from the upper surface side of the flexible printed wiring board by a supporting material, and the connection state is inspected by two-point contact and two-line connection. This has the effect of enabling highly reliable inspection. However, since the tester using the above-mentioned probe card is one for performing a probe test on one semiconductor chip, there is no consideration of simultaneously testing a plurality of semiconductor chips, and there is a problem that simultaneous measurement cannot be performed. is there.

Further, in Japanese Patent Laid-Open No. 2-186279, for use with a prober, probe points for providing test points to a TAB frame and a die above the TAB frame are provided in advance in the TAB frame. Disclosed is a TAB test assembly and a test method therefor capable of electrically testing the electrical connection between itself and the die and the functionality of the die. However, this TAB test assembly and its test method allow easy testing of scrap coupons that have been rejected during the TAB manufacturing process and removed from the TAB tape, using a probe card or scrap flow bar separately. It is necessary, and simultaneous measurement of semiconductor chips formed on one silicon wafer is not considered at all, and there is a problem that simultaneous measurement is difficult.

By the way, some LSI testers have a function of simultaneously measuring a plurality of LSIs (so-called Multi-
Some have a DUT measurement function). These use the above-mentioned contact metal pins as tester pins. A large number of tester pins are provided, these tester pins are divided and assigned to a plurality of LSIs, and the tester pins are supplied to the LSI corresponding to these tester pins. Input signal generation circuit, judgment circuit (comparator) for judging output signal from LSI, electrical characteristics of LSI (input / output voltage,
It has a large number of test units such as a DC test unit for measuring the input / output current etc.). Then, these test units correspond to these and are connected to the pins of the LSI to be measured through the tester pins assigned to the LSI to be measured. The LSI tester with a Multi-DUT measurement function can measure a plurality of LSIs at the same time, but it requires a large number of test units and requires as many measuring pins and comparators as the number of pins to be measured, which reduces the cost of the tester. There is a problem that it increases the number and becomes an expensive tester.

For this reason, Japanese Patent Laid-Open No. 2-297236 discloses means for storing the same test data in a plurality of RAMs under test, and the test data and the RAMs under test.
By using the means for comparing the read data from the RAM simultaneous test circuit, it is possible to perform a plurality of RAM function tests under test in parallel even with an inexpensive general-purpose tester having a relatively small number of pins. It is disclosed.
Further, JP-A-4-270978 discloses an IC tester in which a multiplexer is provided in the preceding stage of a DUT (device under test) determination comparator so that one comparator can test a large number of output pins of the DUT. Has been done. However, although the testers disclosed in these documents are capable of measuring multiple devices at the same time, since they focus only on the logic measurement of the memory, it is only the functional test that allows the simultaneous measurement. However, there is a problem that the DC characteristics cannot be measured simultaneously.

[0008]

As described above, the conventional L
In SI tester, IC tester, etc., when performing probe evaluation of characteristics including DC characteristics, in order to simultaneously measure a plurality of semiconductor chips, increase the number of comparators or use DC with a plurality of memories and clocks. There was no other alternative than sacrificing properties.

An object of the present invention is to solve the above-mentioned problems of the prior art, and to increase the number of test heads for testing,
It is possible to simultaneously measure a plurality of semiconductor chips with respect to their characteristics including their DC characteristics and functionalities, that is, to perform Multi-DUT measurement capable of measuring DC characteristics, and to select any semiconductor chip capable of simultaneous measurement. Provided are a probe test apparatus and a probe test method that can be automatically selected, further shorten the wafer probe test time, improve the life of a wafer prober such as a probe card, and facilitate maintenance management. There is.

[0010]

In order to achieve the above object, a first aspect of the present invention is to provide an insulating flexible film, a plurality of openings provided in the flexible film, and a plurality of openings of the plurality of openings. A plurality of TAB bumps provided around each of them, and a first wiring layer including a first lead extending from a part of the TAB bumps of each opening to a periphery of the flexible film in a predetermined direction without overlapping. Corresponding to the remainder of the TAB bumps in each of the openings through an insulating layer with respect to the first wiring layer, and in a direction that forms a predetermined angle with the direction of the first lead without overlapping. A second wiring layer including a second lead extending to the periphery of the flexible film, and a contact for connecting the second lead with the remainder of the TAB bump in each opening. Means, a tester pin connection pad provided on the outer peripheral portion or outside of the flexible film corresponding to the TAB bump of the opening, and a first or second lead extending from the TAB pad at the same position of each opening. (EN) A probe test device provided with a flexible probe card which has a connecting means for connecting and connecting with a corresponding tester pin connecting pad. Here, it is preferable that the opening is a rectangular flexible probe card that is arranged so that its diagonal lines are aligned with each other and the first lead and the second lead are substantially orthogonal to each other.

A second aspect of the present invention is the probe test apparatus according to the first aspect, wherein the flexible probe card is further provided around the opening on the surface of the flexible film opposite to the TAB bump. An electromagnet having a stacked magnetic body, the electromagnet being arranged in proximity to the magnetic body, the polarity being changed by an injection current to the electromagnet, and a TAB bump in an opening of the flexible probe card; To provide a probe test apparatus characterized by electrically connecting or disconnecting the semiconductor chip electrodes on a wafer aligned with this, and automatically controlling the number of the semiconductor chips to be simultaneously measured. is there.

A third aspect of the present invention is the probe test apparatus according to the first aspect, further including a TAB bump for each of the plurality of openings of the flexible card and an independent TAB bump for each opening. The probe test apparatus is provided with a means for contacting an electrode of a semiconductor chip on the wafer aligned with this.

Further, a fourth aspect of the present invention uses the probe test apparatus of the second and third aspects to simultaneously measure a plurality of semiconductor chips on a wafer, and the flexible test is performed for the measurement. The number of semiconductor chips in contact with the TAB bumps of the probe card and its electrodes is detected, and the comparator level and programmable load are automatically changed according to the number of semiconductor chips to be measured. The present invention provides a probe test method characterized by performing simultaneous measurement of semiconductor chips.

Further, a fifth aspect of the present invention is a method of simultaneously measuring a plurality of semiconductor chips on a wafer for a plurality of measurement items by using the probe test apparatus of the second and third aspects. The electrodes of the semiconductor chips to be measured are brought into contact with the TAB bumps of the flexible probe card, and the measurement is performed for one measurement item in the simultaneous measurement mode in which the measurement is performed under the measurement conditions according to the number of the semiconductor chips to be measured. When all the measured semiconductor chips are normal, the process moves to the measurement of the next measurement item, and when the measured value of the one measurement item is not a normal value, only one measured semiconductor chip is measured. The electrodes are brought into contact with the TAB bumps of the flexible probe card, and a plurality of semiconductor chips to be measured 1 The defective semiconductor chips are identified one by one, and the defective semiconductor chips are removed from the measurement target, the electrodes of only the normal semiconductor chips are brought into contact with the TAB bumps of the flexible probe card, and automatically changed according to the number. Repeatedly performing the simultaneous measurement of the next measurement item under the specified measurement conditions, after the measurement of all measurement items is completed, move the flexible probe card,
The present invention provides a probe test method characterized by performing the following plurality of probe tests.

[0015]

According to the probe test apparatus of the first aspect of the present invention, the insulating flexible film is provided with the TAB bumps which come into contact with all the electrodes of one semiconductor chip formed on the wafer. 2 to extend in the direction
Since it has a plurality of basic pattern units composed of wiring layers, and has flexible probe cards in which TAB bumps at the same positions of all basic patterns are connected to each other and also to one test head pin connection pad, A characteristic test including DC characteristics and functionality can be simultaneously performed on a plurality of semiconductor chips.

The probe test apparatus according to the second aspect of the present invention includes a magnetic material laminated on a flexible probe card and an electromagnet arranged in the vicinity thereof, and the probe test apparatus according to the third aspect of the present invention. Can contact the TAB bump of the probe card with the semiconductor chip to be measured independently for each chip, so that the semiconductor chip to be measured can be arbitrarily selected.

In the probe test method according to the fourth aspect of the present invention, when simultaneously measuring a plurality of semiconductor chips, the number of semiconductor chips whose electrodes are in contact with the TAB bumps of the probe card is detected, and according to this number. Since the comparator level of the output and the programmable load can be automatically changed, the simultaneous measurement of an arbitrary number of semiconductor chips can be automatically performed without increasing the number of comparators.

The probe test method of the fifth aspect of the present invention has a simultaneous measurement mode in which a plurality of semiconductor chips are simultaneously measured and an individual measurement mode in which individual semiconductor chips are measured, and one measurement item is provided. If the measured value in the simultaneous measurement mode is normal, move to the next measurement item,
If it is abnormal, the individual measured semiconductor chips are sequentially measured in the individual measurement mode to identify the defective chip,
After the end, since the defective chip is removed and the measurement is performed in the simultaneous measurement mode, the DC characteristic test and the functional test can be similarly performed without increasing the comparator and the test head. The test time can be shortened.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A probe test apparatus and a probe test method according to the present invention will be described below in detail with reference to the preferred embodiments shown in the accompanying drawings.

FIG. 1 is a schematic view of an embodiment of the probe test apparatus according to the first aspect of the present invention. As shown in the figure, the probe test apparatus 10 according to the present invention includes a plurality of semiconductor chips (hereinafter referred to as LS) formed on a silicon wafer 12.
Flexible probe card (hereinafter referred to as probe card) for enabling measurement of I-chip 14) 1
6, a prober 18 for mounting the silicon wafer 12 on the lower side of the probe card 16, a test head 20 for setting the probe card 16, and a function of the LSI chip 14 to be measured via the test head 20. And a test unit 22 that performs a sex test and an electrical property (DC property) test.

The test unit 22 includes a generation circuit 24 for an input signal to be supplied to the LSI chip 14 to be measured and a judgment circuit (comparator) 26 for judging an output signal from the LSI chip 14 to be measured. Function test unit 27, DC test unit 28 for measuring electrical characteristics such as input / output current and output voltage, and control unit 30 for controlling these units 27 and 28.

The test head 20 also has tester pins 32 for electrical connection with the probe card 16.
Probe test apparatus 1 according to second and third aspects of the present invention
In 0, in order to enable measurement of the selected LSI chip 14 to be measured, this LSI chip 14 (electrodes)
Means 34 for bringing the probe card 16 into contact with (the TAB bump 44 of) the probe card 16, drive control means 36 for driving and controlling this contact means, and the probe card 16 is brought into contact and electrically connected by this drive control means, and simultaneous measurement is performed. And a means 38 for detecting the number of LSI chips 14 for which Here, as a matter of course, the test unit 22 and the test head 24 are electrically connected.

Next, the probe card 16 is the most characteristic feature of the present invention. It has a substantially square insulating flexible film (flexible wiring board) 40 and a plurality of perforated film 40 at predetermined positions. (Nine in the illustrated example) openings 42 (LSI chips A1, B2, C3,
, D4, ..., I9), TAB bumps 44 (see FIGS. 1 and 3) provided around the openings 42 corresponding to the electrodes of the LSI chip 14 to be measured, and on the film 40. , TAB on both vertical sides of the opening 42 in the figure
A first wiring layer 46 composed of a plurality of lateral leads 45 extending from the bump 44 to the left and right in the lateral direction, and an opening 42 in the drawing.
Second wiring layer 4 including a plurality of vertical leads 47 extending vertically from the TAB bumps 44 on both lateral sides of the
8 and the horizontal lead 45 of the first wiring layer 46 and the vertical lead 47 of the vertical wiring layer 48 at the same position of each opening 42 (the position corresponding to the same electrode of each LSI chip 14).
Connect the leads 45 and 47 extending from
The vertical and horizontal connection wirings 50 and 52 connected to the contact points 49 provided on the film 40, and the flexible film 40 provided with the openings 42, the TAB bumps 44, the wiring layers 46 and 48, the contact points 49, and the connection wirings 50 and 52 are fixed. And a TAB bump 44 (electrode of the LSI chip 14 to be measured) of the opening 42 provided on the outer peripheral portion of the printed wiring board 54 for connection with the test head 20. And a tester pin connection pad 56.

The flexible film 40 has a square shape with four corners missing, and the printed wiring board 54 is hard and has a circular outer shape, and the four corners smaller than the size of the flexible film 40 are quadrants in the center. A square opening 58 is provided, and the flexible film 40 is placed on the opening 58, and its four sides are adhesively fixed on the printed wiring board 54. In the illustrated example, the plurality of openings 42 in the film 40
Are LSI chips A1, B2, C3, D4, ...
Nine pieces are arranged in a diagonal line corresponding to I9, but the present invention is not limited to this, and the TAB bumps provided around the opening 42 to the connection wirings 50, 52 at the outer edge portion of the film 40 are formed. Any arrangement is possible as long as the leads 45 and 47 extended to the above do not overlap each other and run on the other openings 42. Further, in the illustrated example, the shape of the opening 42 is also a square according to the shape of the LSI chip 14, but the present invention is not limited to this, and a rectangle (rectangle), a rhombus, a polygon, a circle. , An elliptical shape or the like may be appropriately selected according to the arrangement of the electrodes of the LSI chip 14, and may or may not be matched with the shape of the LSI chip 14.

FIG. 3 shows a probe card 16 of the present invention.
Openings 42 and the TAB bumps 4 around the openings 42
4 shows a basic pattern unit 41 of the probe card having a wiring structure drawn from No. 4. The probe card 16 of the present invention is a combination of a plurality of these basic pattern units 41. In FIG. 3, TAB bumps 44 are provided on the periphery of the opening 42 in correspondence with the electrode positions of the LSI chip 14 to be measured. In the illustrated example, twelve TAB bumps 44 per side are provided along the inner side, but the present invention is not limited to this, and may be determined according to the number and arrangement of electrodes of the LSI chip 14 to be measured. Good.

In FIG. 3, the horizontal leads 45 extend in the horizontal direction from the TAB bumps 44 on both sides of the opening 42 in the vertical direction, and the end points (contact points) are arranged at the outer edge of the flexible film 40 so as to be slanted little by little. ) 51. The plurality of lateral leads 45 form a first wiring layer (horizontal wiring layer) 46. On the other hand, from the TAB bumps 44 on both sides of the opening 42 in the horizontal direction, vertical leads 47 that are short in the vertical direction are formed.
a is extended to the contact 47b. Although not shown in FIG. 3, the vertical lead 47 is extended from the contact point 47b and is connected to the end point (contact point) 53, which is also arranged at the outer edge portion of the flexible film 40, which is slanted little by little (FIG. 3). 2). Here, the short vertical lead 47a forms the first wiring layer 46, and the vertical lead 47 is the second wiring layer (vertical wiring layer).
48 is formed. Here, an insulating layer (not shown) is interposed between the first wiring layer 46 and the second wiring layer 48, and the contact 47b is formed.
Is a contact for electrically connecting the lead 47a and the lead 47 through a hole formed in this insulating layer. Further, the contact 51 of the horizontal lead 45 of the first wiring layer 46 is connected to the vertical connection wiring 50 through the insulating layer, and the connection wiring 50 is formed on the second wiring layer 48. On the other hand, the contact 53 of the vertical lead 47 of the second wiring layer 48 is connected to the horizontal connection wiring 52 through the above-mentioned insulating layer, and the connection wiring 52 is formed on the first wiring layer 46.

In the illustrated example, the TA around the opening 42
Although the leads 45 and 47 extending from the B bump 44 are arranged in a direction substantially orthogonal to the vertical direction and the horizontal direction as a two-layer wiring, the present invention is not limited to this, and the leads 45 and 47 from the TAB bump 44 can be formed. The extension directions may intersect at an arbitrary angle, or may be multilayer wiring of two or more layers. The probe test apparatus according to the first aspect of the present invention is basically configured as described above.

FIG. 4 shows details of the contact means 34 of the probe test apparatus 10 according to the second aspect of the present invention. Contact means 34
Is the film 4 around the opening 42 of the probe card 16.
The magnetic material 60 laminated on the upper surface side of the film 40 corresponding to the TAB bumps 44 provided on the lower surface of the magnetic disk 0 and the magnetic property when the probe card 16 is aligned (aligned) with the LSI chip 14 It has an electromagnet 62 arranged at a position facing the body 60 and separated by a predetermined distance, and a drive control means 36 (see FIG. 1) including a power source for supplying a current for driving the electromagnet 62 and a means for controlling the direction of the current. .
Depending on the direction of the current flowing through the electromagnet, the magnetic body 60 and the electromagnet 6
When the polarity is the same as that of 2, the repulsive force acts on both, and the TAB bump 44 of the probe card 16 is connected to the LSI chip A1 as in the case of the LSI chip 14 (A1) on the left side of the drawing.
The electrode is surely contacted and an electrical connection is made. In this way, the LSI chip A1 is used for measurement. On the other hand, when the polarities of the magnetic body 60 and the electromagnet 62 are reversed, an attractive force acts on both, and the probe card 16 is separated from the LSI chip B2 as in the case of the LSI chip 14 (B2) in the middle of the drawing, and the TAB The bump 44 and the electrode of the LSI chip B2 are separated by a predetermined distance, for example, 1 μm. In this way, the LSI chip B2 is removed from the measurement.

In this way, by controlling the direction of the current flowing through the electromagnet 62, the LSI chip 14 to be measured can be arbitrarily selected, and the number and position of the LSI chips 14 to be simultaneously measured can be arbitrarily selected. it can. Here, the method of providing the magnetic body 60 is not particularly limited, but the layer may be transferred by vapor-depositing an amorphous sheet of the magnetic body, for example.

In the example shown in FIG. 4, the probe card 16 is provided with the magnetic body 60, and the test head 20 is provided with the electromagnet 6.
However, the present invention is not limited to this, and a support having a predetermined weight is interposed between the probe card 16 and the electromagnet 62, and the T of the probe card 16 is interposed via this support.
The AB bumps 44 may be brought into contact with the electrodes of the LSI chip 14 to separate the support body and the probe card 16 as a unit. In addition to this mechanically probe card 1
The TAB bumps 44 around the opening 42 of 6 may be moved up and down.

The probe test apparatus according to the second and third aspects of the present invention is basically constructed as described above. The probe test methods according to the fourth and fifth aspects of the present invention will be described below.

In the probe test method according to the fourth aspect of the present invention, the detecting means 38 detects the direction of the current controlled by the current driving means 36 flowing through the electromagnet 62 of the contact means 34 shown in FIG. The number of the LSI chips 14 in the TAB bump 44 around the opening 42 of the probe card 16 is in contact with the LSI chip 14 and is electrically connected to the test unit 22.
In the control unit 30 according to the number of the LSI chips 14 to be measured selected, such as the comparator level of the comparator 26 of the function unit 27, the programmable load of the input signal generating circuit 24, and the DC test conditions. The probe test such as the function test and the DC test is performed under the automatically changed measurement conditions.
The automatic change of the measurement condition can be configured such that the measurement condition for each one of the LSI chips 14 is stored in advance in the memory of the control unit 30 and the necessary measurement condition is calculated according to the number. .

FIG. 5 shows a probe test method according to the fifth aspect of the present invention. First, the silicon wafer 12 on which the LSI chip 14 is formed is placed on the prober 18, set at a predetermined position, and the probe card 16 and the test head 20 are aligned and set thereon.

Next, the measurement routine is started, the measurement mode is set to the simultaneous measurement mode, and the total number of LSI chips 14 to be measured is set to nine in the example shown in FIG. Set initial measurement conditions such as comparator level and programmable load. At the same time, the electromagnet 6 of the contact means 34 is controlled by the drive control means 36.
2 is caused to flow in a predetermined direction to generate a repulsive force between the probe card 16 and the magnetic body 62 provided in the peripheral portion of all the openings 42, and the TAB bumps 44 and the LSI chip 14 in the periphery of all the openings 42. (A1, B2, C3, D4,
······ I9) electrode is surely contacted and electrically connected (conduction state).

Next, the measurement items are set. Here, the measurement items are the DC test, the input voltages V _IL , V _IH , the output voltages V _OL , V _OH , and the standby current Idds. In the function test, the conduction logic of the LSI chip 14 is logic 1, and the failure pattern is logic. 2 and V _IL → V _IH
→ In V _OL → V _OH → Idds → order logic 1 → Logic 2 shall perform measurements on all these against LSI chip 14.

Setting items D of the test unit 22
Measurement is performed using the C test unit 28 or the function test unit 27, the obtained result is judged by the comparator 26, and if the measured value is normal (PASS), the process moves to the next measurement item. All measurement items are completed,
If there is no measurement item to be transferred, the direction of the current flowing through the electromagnet 62 of the contact means 34 is changed to bring the magnetic body 60 of the probe card 16 into contact with the electromagnet 62, and the TAB bump 44
The contact between the electrodes and all the electrodes of the LSI chip 14 is released to bring them into a non-conductive state. After that, the probe card 16 is moved to the next LSI chip 14 group on the silicon wafer 12, and a new test routine is started. If there is no next LSI chip group, the test ends and the silicon wafer 12
Is removed from prober 18.

On the other hand, when the measured value is not normal (FAI
In L), the measurement mode is changed to the individual measurement mode. In this individual measurement mode, the measurement condition is set to one measurement condition, one LSI chip 14, for example, A1 is selected, and the measurement of the selected one LSI chip A1 is performed for the same measurement item. If the measurement result is normal (PASS), the next one LSI chip 14 is selected. On the other hand, when the measured value in the individual measurement mode is not normal (FAIL), this LSI chip 14 is identified as a defective (FAIL) chip, and the next one LSI chip 14 is selected. In this way, the LSI chips 14 are selected one by one and the measurement is repeated until there are no more LSI chips 14 to select.

LSI chip 1 selected in the individual measurement mode
When 4 disappears, the individual measurement mode changes to the simultaneous measurement mode. Here, in the measurement of the next measurement item, all the remaining LSI chips 14 except the identified defective LSI chip 14 are brought into conduction by the contact means 34. Then, the number of the LSI chips 14 in the conductive state is detected by the detecting means 38, and the current load of the output comparator is automatically changed in level according to the number to set the measurement condition. In this way, all the remaining normal LSI chips 14 are measured under the measurement conditions set according to the number. In this way, the probe test can be performed fully automatically by the probe test method according to the fourth aspect of the present invention.

The probe test apparatus and the probe test method according to the present invention are basically configured as described above, but the present invention is not limited to this, and for example, between the first wiring layer and the second wiring layer. Needless to say, the insulating layer may be an insulating flexible film of a flexible probe card, and both wiring layers may be formed on both sides of the insulating flexible film, so that the design can be changed or improved without departing from the scope of the present invention.

[0040]

As described above in detail, according to the first, second and third aspects of the present invention, the characteristics including the DC characteristics and the functional characteristics of the arbitrary plurality of semiconductor chips formed on the wafer. Tests can be measured simultaneously without increasing comparators and test heads. Further, in this way, the wafer probe test time can be shortened. Further, even if one basic pattern unit of the wafer probe card becomes defective, it is possible to perform measurement at the other portions, and it is possible to improve the life of the wafer prober and facilitate maintenance management.

According to the fourth aspect of the present invention, the T of the probe card is used when simultaneously measuring a plurality of semiconductor chips.
The number of semiconductor chips whose electrodes come into contact with the AB bumps can be detected, and the output comparator level and programmable load can be automatically changed according to this number, increasing the number of comparators for simultaneous measurement of any number of semiconductor chips. It can be done automatically without the need for it.

According to the fifth aspect of the present invention, a simultaneous measurement mode for simultaneously measuring a plurality of semiconductor chips and an individual measurement mode for measuring each semiconductor chip are provided, and one measurement item is simultaneously measured. If the measured value in the measurement mode is normal, move to the next measurement item, if abnormal, sequentially measure each semiconductor chip under test in the individual measurement mode, to identify the defective chip, After the end, the defective chip is removed and the measurement is performed in the simultaneous measurement mode.
The DC characteristic test and the functional test can be similarly performed without increasing the number of comparators and test heads, and the probe test time can be shortened.

[Brief description of drawings]

FIG. 1 is a schematic diagram of an embodiment of a probe test apparatus according to the present invention.

FIG. 2 is a schematic plan view of an example of a flexible probe card used in the probe test apparatus according to the present invention.

FIG. 3 is a schematic view of an example of a basic pattern unit of the flexible probe card shown in FIG.

FIG. 4 is a schematic view of an embodiment of contact means used in the probe test apparatus according to the present invention.

FIG. 5 is a flowchart showing an example of a probe test method according to the present invention.

[Explanation of symbols]

 10 probe test device 12 silicon wafer 14 semiconductor chip (LSI chip) 16 flexible probe card 18 prober 20 test head 22 test unit 24 input signal generation circuit 26 judgment circuit (comparator) 27 function test unit 28 DC test unit 30 control unit 32 tester pin 34 Contact Means 36 Drive Control Means 38 Detecting Means 40 Flexible Film 41 Basic Pattern Units 42, 58 Openings 44 TAB Bumps 45, 47, 47a Leads 46, 48 Wiring Layers 47b, 49, 51, 53 Contacts 50, 52 Connection Wiring 54 Print Wiring board 56 Tester pin connection pad 60 Magnetic material 62 Electromagnet

Claims (6)

[Claims] 1. An insulating flexible film, a plurality of openings formed in the flexible film, a plurality of TAB bumps provided around each of the plurality of openings, and a part of the TAB bumps in each opening. A first wiring layer including first leads extending to the periphery of the flexible film in predetermined directions without overlapping from each other,
Corresponding to the remainder of the TAB bumps in each of the openings, it is provided on the first wiring layer via an insulating layer and is flexible in a direction forming a predetermined angle with the direction of the first lead without overlapping. A second wiring layer including a second lead extending to the periphery of the film, and T of each of the openings
Connection means for respectively connecting the rest of the AB bump and the second lead, a tester pin connection pad provided on the outer peripheral portion of the flexible film or corresponding to the TAB bump of the opening, and the same position of each opening TAB
A probe test apparatus comprising a flexible probe card having first or second leads extending from a pad, which are connected to each other and connecting means for connecting to a corresponding tester pin connection pad. 2. The flexible probe card according to claim 1, wherein the opening has a rectangular shape, the diagonal lines of which are arranged in a straight line, and the first lead and the second lead are substantially orthogonal to each other. Probe test equipment. 3. The probe test apparatus according to claim 1, wherein the flexible probe card further comprises a magnetic material laminated around the opening on the surface of the flexible film opposite to the TAB bump. And further comprising an electromagnet arranged in proximity to the magnetic body, the polarity of which is changed by an electric current injected into the electromagnet, and the TAB bump of the opening of the flexible probe card and the TAB bump aligned therewith, A probe test apparatus characterized by electrically connecting or disconnecting an electrode of a semiconductor chip on a wafer and automatically controlling the number of the semiconductor chips to be simultaneously measured. 4. The probe test apparatus according to claim 1 or 2, further comprising: for a plurality of openings of the flexible card, TAB bumps in each opening and a wafer aligned with the TAB bump. 2. A probe test apparatus comprising means for contacting the electrodes of the semiconductor chip of. 5. The TAB bump of the flexible probe card and its electrode are contacted for measurement when simultaneously measuring a plurality of semiconductor chips on a wafer using the probe test apparatus according to claim 3 or 4. The number of semiconductor chips being measured, the comparator level and programmable load are automatically changed according to the number of semiconductor chips to be measured, and simultaneous measurement of multiple semiconductor chips is performed under the automatically changed measurement conditions. Characteristic probe test method. 6. When simultaneously measuring a plurality of semiconductor chips on a wafer for a plurality of measurement items by using the probe test apparatus according to claim 3, the electrodes of a plurality of semiconductor chips to be measured are One measurement item was measured in the simultaneous measurement mode in which the TAB bumps of the flexible probe card were brought into contact and the measurement was performed under the measurement conditions according to the number of the semiconductor chips to be measured, and all the semiconductor chips to be measured were normal. In this case, the process moves to the measurement of the next measurement item, and if the measurement value of the one measurement item is not a normal value, the electrode of only one semiconductor chip to be measured is formed on the TAB bump of the flexible probe card. In the individual measurement mode, in which the semiconductor chips are brought into contact with each other and measured under individual measurement conditions, a plurality of semiconductor chips to be measured are sequentially measured one by one, and defective. After identification of the conductor chip, disconnect the the defective semiconductor chip from the measurement object, by contacting the electrodes only normal semiconductor chip TAB bumps of the flexible probe card,
Repeat the simultaneous measurement of the next measurement item under the measurement conditions that are automatically changed according to the number, and after the measurement of all measurement items is completed, move the flexible probe card to move to the next multiple probes. A probe test method characterized by performing a test.