JPH0722925A - Clock disconnection detection circuit - Google Patents

Abstract

PURPOSE:To eliminate the dispersion of a disconnection monitoring time as a detection threshold in each product by making a circuit have a constitution which is suitable for realizing in an integration circuit. CONSTITUTION:A clock signal IN is inputted in a delay circuit group 21. The delay signals (IN, DLY 1 to DLYN) from at least plural delay circuits are inputted in a logical operation circuit 22 for detection. The logical operation circuit 22 for detection defines a clock disconnection detection signal OUT as significant when the inputted clock signal is disconnection based on the class contents of the logical levels of plural inputted signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock loss detection circuit for detecting a loss of a clock signal.

[0002]

2. Description of the Related Art As is well known, many digital circuits operate in synchronization with a clock signal. Therefore, a clock signal that should have arrived continuously is interrupted and then comes again. However, the circuit may malfunction or the output may be different from the original one. For example, if the digital circuit that operates on the clock signal is a D-type flip-flop circuit, the latch operation that is originally performed a plurality of times is omitted, and if it is a synchronous counter circuit, the count value will be different from the original value. . Therefore, the clock loss detection circuit that detects that the clock signal is lost
Often provided in devices that have multiple digital circuits that utilize clock signals.

FIG. 2 shows the configuration of a conventional clock loss detection circuit 10 using a monostable multivibrator circuit.

The clock loss detection circuit 10 includes a retrigger type monostable multivibrator circuit 11 and a time constant circuit 12 including a resistor R and a capacitor C that define an output pulse width from the monostable multivibrator circuit 11.
It consists of and.

In the case of this conventional example, an output from an output terminal NQ which outputs a logic "1" when a clock signal to be detected as a disconnection is input to the rising trigger input terminal B of the monostable multivibrator circuit 11 and there is a trigger. Is used as a clock loss detection signal. Further, the time constant of the time constant circuit 12 is set so that the output pulse width tw from the monostable multivibrator circuit 11 is longer than the cycle of the clock signal. For example, it is selected to be about 2.5 times the clock cycle.

In the above configuration, when the clock signal is continuously input, the monostable multivibrator circuit 11 starts the pulse width tw from a certain trigger time (this is the disconnection monitoring time for judging that the clock is disconnected). Are repeatedly triggered before the elapse of time), the output signal (clock loss detection signal) becomes a logic "1" for instructing continuous oscillation of the clock signal.

It is assumed that the clock signal is cut off from such a state. When this clock disconnection period exceeds the time tw from the time of the last rising edge, the monostable multivibrator circuit 11 becomes stationary, and the clock disconnection detection signal becomes a logic "0" indicating the disconnection of the clock signal.

[0008]

As described above, the conventional clock loss detection circuit 10 has a simple structure including the monostable multivibrator circuit 11 and the time constant circuit 12, but has the following problems. Have.

In recent years, because of the advantage of downsizing of the device, etc., the component part consisting of one or more digital circuits is often realized by an integrated circuit (eg LSI), and the clock loss detection circuit alone or , Along with other digital circuits,
It is required to realize the clock loss detection circuit by an integrated circuit (particularly a gate array).

However, since the conventional clock loss detection circuit 10 generally includes the capacitor C which is difficult to realize on an integrated circuit as a constituent element, it is difficult to form an integrated circuit. Therefore, with the monostable multivibrator circuit 11, the capacitor C and the resistor R, which are discrete components,
In many cases, the clock loss detection circuit 10 is actually configured,
In this case, the clock loss detection circuit 10 becomes large.

Further, the conventional clock loss detection circuit 10 is
Since the time constant circuit 12 including the capacitor C and the resistor R is an essential constituent element, there is also a problem that the disconnection monitoring time easily varies among products due to variations in the elements forming the time constant circuit 12. is doing.

The present invention has been made in consideration of the above points, and is suitable for implementation in an integrated circuit, and a clock break detection circuit that can make the break monitoring time as a detection threshold the same for each product. It is the one I tried to provide.

[0013]

In order to solve the above problems, in the present invention, a delay circuit group in which a plurality of delay circuits for delaying an input clock signal are cascade-connected,
Clock loss detection with a detection logic operation circuit that makes the clock loss detection signal significant when the input clock signal is interrupted, based on the set content of the logic levels of the delay signals output from at least a plurality of delay circuits Configured the circuit.

[0014]

In the present invention, the clock signal is input to the delay circuit group, and the delay signals from at least the plurality of delay circuits are input to the detection logical operation circuit. The detection logical operation circuit makes the clock loss detection signal significant when the input clock signal is disconnected based on the set contents of the logic levels of the plurality of input signals.

Since the clock loss detection circuit of the present invention is composed of the delay circuit group and the detection logical operation circuit, it is suitable to be realized by an integrated circuit. Further, since there is no time constant circuit, it is possible to eliminate the product variation with respect to the disconnection monitoring time.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a clock loss detection circuit according to the present invention will be described below in detail with reference to the drawings. Here, FIG. 1 shows the configuration of the clock loss detection circuit 20 of this embodiment.

In FIG. 1, this clock loss detection circuit 2
0 is an N-stage delay circuit group 21 in which N delay circuits 211 to 21N are connected in cascade, and an exclusive OR circuit 22.
It consists of and.

The clock signal IN to be detected is input to the N-stage delay circuit group 21. Each stage of delay circuit 211,
, 21N are set to the same delay time TD, for example, and the N delay signals DLY1 ... DLYN from the delay circuits 211, ... Is input to the exclusive OR circuit 22. The exclusive OR circuit 22 takes the exclusive OR of the input clock signal IN and the N delay signals DLY1 ... DLYN, and when all the logic levels match, that is,
When all the inputs are logic "0" or logic "1", the clock loss detection signal OUT indicating the clock loss is output.

Here, the period of the input clock signal IN is T
[Sec] and its pulse occupancy rate is d [%], the delay time Tall of the entire N-stage delay circuit group 21 is selected to be longer than the cycle T, and the delay time TD by the delay circuits 211, ... Select shorter than (T × d) / 100 [sec]. The former condition is a natural condition because the delay time Tall of the entire N-stage delay circuit group 21 defines the disconnection monitoring time to be detected, and the latter condition is synergistic with the former condition. Therefore, the exclusive OR circuit 22 does not operate in a state where there is a disconnection time shorter than the disconnection monitoring time or a clock disconnection.
Is a condition for preventing the output (clock loss detection signal OUT) from taking a logic "0" indicating a clock loss even if it is very small.

FIG. 3 shows a concrete example of the configuration of the N-stage delay circuit group 21. The N-stage delay circuit group 2 shown in FIG.
The configuration example 1 can be realized on an integrated circuit (eg, LSI). The N-stage delay circuit group 21 is composed of an inverter chain in which 2MN inverter circuits are cascade-connected, and an even number (2M
Each of the inverter circuits is a delay circuit 211 of each stage,
…, 21N. Each stage of delay circuit 211,
The delay time TD of 21N is 2M times the propagation delay time of the inverter circuit.

FIG. 4 is a timing chart of each part of the clock loss detection circuit 20 having the above configuration.

When the clock signal IN in the oscillating state is input to the clock loss detection circuit 20, as shown in the first half time of FIG. 4, N + 1 signals IN and DLY1 input to the exclusive OR circuit 22 are input. ..- DLYN are not all in the same state, and at this time, the exclusive OR circuit 22 outputs the clock loss detection signal OUT of logic "1" indicating that the clock signal IN is not disconnected.

In such a state, it is assumed that the clock signal IN is disconnected at time t1. Before the disconnection monitoring time Tall elapses from this time t1, N + 1 signals IN and DLY input to the exclusive OR circuit 22 are input.
1 to DLYN are not all in the same state, and at this time also, the exclusive OR circuit 22 outputs the clock loss detection signal OUT of logic "1" indicating that the clock signal IN is not disconnected. To be done. On the other hand, when the disconnection monitoring time Tall, which is the shortest time set to determine the clock disconnection, elapses from the time point t1, N + 1 signals IN and DLY input to the exclusive OR circuit 22.
1 to DLYN are all in the same state, and thereafter, from this exclusive OR circuit 22, the clock signal I
A clock loss detection signal OUT of logic "0" indicating that N has been disconnected is output.

Although FIG. 4 shows the change of each signal in the disconnection state in which the input clock signal IN is fixed to the logic "0", the input clock signal IN is fixed to the logic "1". Even in the disconnected state, the signals of the respective parts change similarly, and after the disconnection monitoring time Tall elapses from the time when the disconnection occurs, the clock disconnection detection signal OUT of logic "0" indicating that the clock signal IN has disconnected To be done.

Therefore, according to the above embodiment, since the clock break detection circuit 20 is composed of the delay circuit group 21 and the exclusive OR circuit 22, the clock break detection circuit suitable for integrated circuit (particularly gate array). Can be provided.

Further, according to the above-described embodiment, since the disconnection monitoring time for determining disconnection is defined by the number of cascaded stages of the delay circuit group 21, this disconnection monitoring time is determined for each product of the clock disconnection detection circuit 20. It is possible to prevent things that fluctuate.

In the above embodiment, the coincidence / non-coincidence circuit is the exclusive OR circuit. However, the exclusive NOR circuit may be applied depending on the selection of the significant logic level of the clock loss detection signal. Is also good.

Further, in the above embodiment, the delay circuit of each stage is shown to be composed of an even number of inverter circuits, but it may be composed of an odd number of inverter circuits. In this case, a circuit that detects a match / mismatch of the delay signals (and input clock signals) from the odd-numbered delay circuits counted from the first stage and the delay signals from the even-numbered delay circuits counted from the first stage (And input clock signal)
And a circuit for detecting a match / mismatch of the detection signals of the both match / mismatch circuits.

Further, in the above embodiment, the plurality of signals for judging the coincidence / non-coincidence are the input clock signal and the respective delay signals, but the plurality of delay signals on the latter half side of the delay circuit group are coincident with each other. You may make it discriminate | determine a clock interruption by detecting a mismatch. It should be noted that the plurality of delayed signals used for the judgment need to satisfy the above-mentioned conditions. By doing so, the number of input signals to the match / mismatch circuit can be reduced.

Furthermore, in the above embodiment, the delay circuit group is shown to be composed of an inverter chain, but it may have another structure.
For example, it may be a wiring pattern formed on an integrated circuit, or may be a cascade-connected asynchronous flip-flop circuit group. Also, for example, a delay line with a tap may be used, although it is difficult to realize it on an integrated circuit.

In the above embodiment, one type of clock interruption monitoring time is shown, but it is also possible to have two or more types of interruption monitoring time. That is, the information regarding the disconnection time may be obtained. For example, in addition to the configuration of FIG. 1, if an exclusive OR circuit that takes the exclusive OR of the outputs of all the delay circuits up to a certain delay circuit and the input clock signal is further provided,
The total delay time up to a delay circuit on the way can also be used as the clock break monitoring time.

[0032]

As described above, according to the present invention, the clock disconnection detection circuit is constituted by the delay circuit group and the detection logical operation circuit, and therefore, it is suitable to be realized by an integrated circuit. Since there is no constant circuit, it is possible to eliminate product variations with respect to disconnection monitoring time.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment.

FIG. 2 is a block diagram showing a conventional configuration.

FIG. 3 is a block diagram showing a configuration example of a delay circuit group according to an embodiment.

FIG. 4 is a timing chart of each part of the embodiment.

[Explanation of symbols]

20 ... Clock loss detection circuit, 21 ... Delay circuit group, 22 ...
Exclusive OR circuit, IN ... Input clock signal,
OUT: Clock loss detection signal.

Claims (1)

[Claims] 1. A delay circuit group in which a plurality of delay circuits for delaying an input clock signal are cascade-connected, and at least based on a set content of logical levels of delay signals output from the plurality of delay circuits. And a clock logic detection circuit that makes a clock loss detection signal significant when the clock signal is disconnected.