JPH0723030A - Serial data communication device - Google Patents

Abstract

(57) [Abstract] [Purpose] The purpose is to complete the data transfer between the CPU and its peripheral circuits within a fixed time and reduce the probability of erroneous communication. [Composition] The transmitting side is provided with a transmitting interface 12 for transmitting the same frame of transmitting data as N times serial data, and the receiving side is provided with a receiving interface 21 for receiving the transmitted data and a received N number of frames. A reception analysis block that analyzes normal received data rather than data,
An abnormal processing block is provided for performing abnormal processing when normal received data cannot be analyzed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data communication device.

[0002]

2. Description of the Related Art In a conventional serial data communication device, as shown in the block diagram of FIG.
11, a transmission CPU block 11 including a peripheral circuit 112
And a transmission interface 12, a communication status data reception block 13, and an abnormality processing block 14,
The reception block 2 includes a reception CPU block 23 including a CPU 231, a peripheral circuit 232, a reception interface 21, a reception analysis block 22, and a communication status data transmission block 25.

Then, as shown in the flowchart of FIG. 7, in the transmission block 1, the CPU 111 and the peripheral circuit 11 are provided.
The transmission CPU block 11 consisting of two processes the processing Ai, and the transmission interface 12 transmits the data Ai calculated by the processing Ai. In the receiving block 2, the transmitted data Ai is received by the receiving interface 21, and the receiving analysis block 22 receives the data Ai.
The data Ai is transferred to. Then, the reception analysis block 2
At 2, the communication data error detection such as the parity check or the cyclic code check or the partial correction is performed. As a result of this error detection, when the communication is normal, the CPU 231 and the peripheral circuit 232
The data Ai is transferred to the receiving CPU block 23, and the receiving CPU block 23 executes the process Bi. Further, the communication state data transmission block 25 determines that the communication state data is normal and transfers it to the transmission block 1 as a communication or a logic level signal. When the reception is abnormal, the communication state data transmission block 25 regards the communication state data as abnormal and transfers it to the transmission block 1 as a communication or a logic level signal.

The transmitted communication state data is received by the transmission block 1 in the communication state data reception block 13,
When the communication status data is normal, the receiving CPU block 1
In step 1, the next processing A _{i + 1} is performed, and the data A _{i + 1} is communicated by the above processing. Further, when the communication status data is abnormal, if it is determined that the data Ai can be retransmitted, the transmission interface 12 communicates the data Ai by the above processing, and if it is determined that the data Ai cannot be retransmitted, the abnormality processing block 14 performs the abnormal processing. .

[0005]

In such a conventional serial data communication device, handshaking is performed to reduce the probability of erroneous communication. Therefore, the sending side confirms that the communication status data signal from the receiving side is normal and executes the next processing, or holds the communication data and performs the same data again by the interrupt processing synchronized with the communication status data signal. Was communicating. Therefore, it is difficult to complete the data transfer between the CPU and its peripheral circuits within a fixed time and reduce the probability of erroneous communication.

The present invention solves such a problem. By transmitting data of the same frame a plurality of times regardless of the communication state of the receiving side, the CPU or its peripheral circuits can communicate with each other within a fixed time. An object of the present invention is to provide a serial data communication device that can complete data transfer and reduce the probability of erroneous communication.

[0007]

In order to solve the above-mentioned problems, the serial data communication apparatus of the present invention communicates data of the same frame a plurality of times to the transmitting side regardless of the communication state of the receiving side. The data communication means is provided, and the receiving side is provided with the reception analysis means for analyzing the normal received data from the received serial data, and the data transfer is completed between the CPU and its peripheral circuits within a fixed time. It was done.

[0008]

With this configuration, serial data that can be transmitted and received within a fixed time is communicated a plurality of times, so that data transfer can be completed between the CPU and its peripheral circuits within a fixed time, and the probability of erroneous communication can be reduced.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a serial data communication device of the present invention. In FIG. 1, the transmission block 1
Is a transmission CPU including a CPU 111 and a peripheral circuit 112.
The reception block 2 includes a block 11 and a transmission interface 12. The reception block 2 includes a CPU 231 and a peripheral circuit 23.
The reception CPU block 23 is composed of two, the reception interface 21, the reception analysis block 22, and the abnormality processing block 24.

Then, as shown in the flow chart of FIG. 2, in the transmission block 1, the CPU 111 and the peripheral circuit 11 are provided.
The transmission CPU block 11 composed of 2 processes the processing Ai, and the data Ai composed of K characters of one frame calculated by the processing Ai is transmitted to the transmission interface 1
2, the same data Ai is transmitted N times. In the receiving block 2, the received N identical data Ai are received by the receiving interface 21.
(However, j = 1, 2, 3 ... N), and N pieces of data Ai (j) are transferred to the reception analysis block 22. In the reception analysis block 22, the N data Ai (j)
The normal communication data is analyzed and data A is stored in the receiving CPU block 23 including the CPU 231 and the peripheral circuit 232.
hand over i. Then, the receiving CPU block 23 executes the process Bi. If normal communication data cannot be analyzed, the abnormality processing block 24 performs abnormality processing. At this time, in the transmission block 1, considering only the communication data processing time in the reception block 2, the reception CPU block 11 performs the next processing A _{i + 1} , and the data A _{i + 1} is communicated by the above processing, The receiving CPU block 23 executes the process B _{i + 1} .

At this time, the reception analysis block 22 classifies the received N data Ai (j) into the same data group as shown in the flow chart of FIG. Is determined as normal received data Ai. If there is no independent data with the largest number of data groups, it is determined that there is a communication error.

Another processing flow in the serial data communication device of FIG. 1 will be described. In FIG. 1, one frame is M
Data Ai consisting of check characters for verifying errors in M characters communicating with the characters
Is transmitted from the transmission block 1, and the same N frames of data Ai are received by the reception interface 21 in the reception block 2 of N frames of data Ai (j) (where j = 1, 2, 3 ... N). Then, the data Ai (j) of N frames is transferred to the reception analysis block 22.
At this time, the reception analysis block 22 receives the data A of the received N frames as shown in the flowchart of FIG.
The check character in i (j) is divided into the same character group, the check character with the largest number in the character group is independently determined as a normal check character, and the received data Ai (j) that becomes the check character is determined. Normal reception data Ai. If there is no independent check character with the largest number of character groups, or if there is no data Ai (j) that becomes a check character, it is determined that communication is abnormal.

In the serial data communication apparatus shown in FIG. 1, another processing flow will be described. In FIG. 1, 1
A frame transmits a data Ai consisting of a check character for verifying an error of M characters communicating with M characters from a transmission block 1, and the same N frames of data Ai are received in a reception block 2. Of the N frames of data Ai at the reception interface 21 of
(J) (where j = 1, 2, 3 ... N), and the reception analysis block 22 receives data Ai of N frames.
(J) Hand over. At this time, in the reception analysis block 22, when all the received N data Ai (j) are the same data, as shown in the flowchart of FIG. Divides the check characters in the received N frames of data Ai (j) into the same character group, independently determines that the largest number of check characters in the character group is a normal check character, and The received data Ai (j) that becomes a character is set as the normal received data Ai. If there is no independent check character with the largest number of character groups, or if there is no data Ai (j) that becomes a check character, it is determined that communication is abnormal.

[0014]

As described above, according to the present invention, the data transfer between the CPU and its peripheral circuits can be completed within a fixed time, and the probability of erroneous communication can be reduced, which is extremely useful in practice. is there.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a serial data communication device according to an embodiment of the present invention.

FIG. 2 is a flow chart diagram showing a flow of processing in the serial data communication apparatus according to the embodiment of the present invention.

FIG. 3 is a flow chart diagram showing a flow of processing in a reception analysis block of the serial data communication apparatus in one embodiment of the present invention.

FIG. 4 is a flowchart showing another processing flow in the reception analysis block of the serial data communication apparatus according to the embodiment of the present invention.

FIG. 5 is a flowchart showing the flow of yet another process in the reception analysis block of the serial data communication device in one embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration of a conventional serial data communication device.

FIG. 7 is a flowchart showing a flow of processing in the conventional serial data communication device.

[Explanation of symbols]

 1 Transmission Block 2 Reception Block 11 Transmission CPU Block 12 Transmission Interface 21 Reception Interface 22 Reception Analysis Block 23 Reception CPU Block 24 Abnormal Processing Block 111 CPU 112 Peripheral Circuit 231 CPU 232 Peripheral Circuit

Claims (4)

[Claims] 1. In a system which completes data transfer of one frame consisting of a plurality of characters between a CPU and its peripheral circuits within a fixed time, the transmitting side is within a fixed time regardless of the communication state of the receiving side. A serial data communication device comprising: a data communication unit for communicating serial data of the same frame a plurality of times; and a receiving side having a reception analysis unit for analyzing normal received data from the received serial data. 2. In a system for completing the data transfer of one frame consisting of K characters between the CPU or its peripheral circuits within a fixed time, the reception analysis means comprises:
The reception interface that receives the transmitted data, the reception analysis block that individually determines and analyzes the most numerous data as normal reception data from the received N frames of data, and the normal reception data An abnormality processing block for performing abnormality processing when analysis is not possible, and a receiving CPU block including a CPU and peripheral circuits.
The serial data communication device described. 3. A system for completing one frame of data transfer consisting of check characters for verifying an error of M characters communicating with M characters between a CPU and its peripheral circuits within a fixed time. The reception analysis means determines that the reception interface that receives the transmitted data and the M characters that are the largest number of check characters independently of the received N frames of data are normal reception data. -Reception analysis block for analysis, abnormal processing block for performing abnormal processing when normal received data cannot be analyzed, and CPU
The serial data communication device according to claim 1, further comprising: a reception CPU block including a peripheral circuit. 4. A system for completing one-frame data transfer consisting of check characters for verifying an error of M characters communicating with M characters between a CPU or its peripheral circuits within a fixed time. When the reception analysis means receives the transmitted data and the received N frames of data are all the same data, the reception analysis means determines that the data is normal. It consists of a reception analysis block that determines and analyzes M characters that are a large number of check characters as normal received data, an abnormal processing block that performs abnormal processing when normal received data cannot be analyzed, and a CPU and peripheral circuits. Receiving CPU
The serial data communication device according to claim 1, further comprising a block.