JPH07230366A - Image processing device - Google Patents

Abstract

(57) [Abstract] [Purpose] A synchronous DRAM is used as an image memory to further improve the processing speed. [Structure] CPU 1 and SDRAM 3 which are access request sources
An intermediate buffer 4 is provided between and. The request data from the CPU 1 and the subsequent data are read from the SDRAM 3,
The prefetched data is held in the data holding means 45 of the intermediate buffer 4, and the read request data is supplied without being read from the SDRAM 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in the processing speed of an image processing apparatus such as a printer or a scanner, especially an image processing apparatus using a synchronous DRAM as a storage device.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor memory device used in an image processing device, in order to realize a large capacity and a low price, a high speed page mode, a static column mode or a nibble mode is used.・ It consisted of mode DRAM.

A high speed page mode DRAM has a column address strobe (CAS) with a row address strobe (RAS *, where * indicates negative logic) being asserted. By inputting *) and column address, high speed random access to the same row address can be performed. Static column mode D
The RAM can access the same row address at high speed by changing the column address while RAS * is asserted, as in the case of the high speed page mode. In addition, a column by CAS *
Since it is not necessary to strobe the address, the speed can be increased. In addition, the nibble mode DRAM is CA with RAS * asserted after the normal access is completed.
By the toggle operation of S *, the data of the address whose lower 2 bits are incremented is sequentially accessed. This nibble mode DRAM can be burst-accessed only for 4 words, but it has a feature that it is faster than other modes.

The above-mentioned DRAMs of various modes are capable of high-speed access during continuous access to the nearby space.
Particularly, when the image data is sent to the printer which requires high-speed operation and the read image data is written by the scanner, the sequential access is performed, so that this feature can be effectively utilized.

There is also a CPU having a cache memory inside and configured to perform a refill operation at the time of a cache memory miss hit in a unit of a plurality of word blocks. Even in this case, since many of them can be converted into sequential access or sequential access, many of them can be accessed at high speed.

However, when the DRAM of each mode is used, although the access can be realized at high speed, the cycle time is about 40 nsec (25 MHz). For this reason, an expensive SRA is required to realize even faster access.
It was necessary to use M or the bank interleave technique. Bank interleaving speeds up sequential access by accessing the previous address at the same time, but the bus width for banks is required, and the minimum configuration unit becomes larger. There is.

The use of a synchronous DRAM can be cited as a method for solving such a drawback. Synchronous D
RAM is a completely synchronous type, unlike ordinary DRAM. Therefore, a low address, column address entry, refresh, etc. are given as a command to the rising edge of the clock. In case of a lead, the first data
The access time to the data is the same as that of a normal DRAM, but the data thereafter is output at every clock. At this time, the access order is set in the mode setting.
It is not necessary to input the address every clock. In the case of write, it can be input from the first data every clock. And because the cycle of this clock is as high as 100MHz,
It enables high-speed access. The order of burst access is sequential mode and interleave.
Two types of modes can be set. The sequential mode is to access from the start address while incrementing the burst length. At this time, when the maximum address in the block is reached, the process returns to the minimum address in the block. When the burst length is L, the interleave mode accesses the start address in the same address order as the exclusive OR operation is performed in order from 0 to (L-1). To go. Here, the block indicates a partition for each burst length. Therefore, for example, in a 16M synchronous DRAM having a 2M × 8 bit structure, assuming that the burst length is 4, there are (2 × 1024 × 1024 ÷ 4) = (512 × 1024) blocks.

In the case of image memory access for image data transfer to the printer, the rate of sequential access is very high. Therefore, by using the synchronous DRAM, high speed transfer can be achieved. Easy to achieve. Also, when the CPU refills the cache memory, it can be interleaved, sequential or one word.
There are many things to access, but synchronous DRA
When M is used, all of these can be dealt with, and high-speed processing can be realized.

[0009]

When the synchronous DRAM is used as described above, a large-capacity and high-speed image memory can be realized at a low price. However, the synchronous DRAM is used until the first read data is obtained. The time is the same as that of a normal DRAM, and this time is slow. Furthermore, the delay in obtaining the first read data becomes an obstacle when trying to increase the processing speed.

An object of the present invention is to solve the above drawbacks and to obtain an image processing apparatus which uses a synchronous DRAM as an image memory and can further improve the processing speed.

[0011]

An image processing apparatus according to the present invention is an image processing apparatus having a central processing unit and a storage device composed of a synchronous DRAM, wherein an intermediate buffer is provided between the central processing unit and the storage device. The intermediate buffer has a data holding means for holding the data sent from the storage device and a data output means. The data output means is the data holding means for reading. When the data of the requested address is held, the data held in the data holding means
When the data holding means does not hold the data of the target address of the read request, it outputs more data than the requested data length from the storage device and outputs the requested data. It is characterized in that only the data is output and the surplus data is held by the data holding means.

The image processing apparatus according to the second invention is
In an image processing apparatus having a central processing unit and a storage device composed of a synchronous DRAM, an intermediate buffer is provided between the central processing unit and the storage device, and the intermediate buffer holds data sent from the storage device. Has a plurality of data holding means and data output means, and the data output means is a data output means.
When the data holding means holds the data of the target address of the read request, the data holding means outputs the held data, and the data holding means outputs the target of the read request. When the address data is not held, more data than the requested data length is read from the storage device, only the requested data is output, and the valid data in the data holding means is output. -If there is data holding means that does not hold data or data holding means that has already supplied data to the access request source, hold excess data in the data holding means. When there is no data holding means that does not hold valid data and data holding means that has already supplied data to the access request source, the oldest data is held. The data holding means is made to hold the surplus data.

In the above image forming apparatus, when the data holding means does not hold the data of the target address of the read request and the read request is an instruction, the data holding means has an excess. It is preferable to retain the data of.

Further, when the data holding means does not hold the data of the target address of the read request and the read request has a specific data length, the data holding means Surplus data
May be held.

Further, when the data holding means does not hold the data of the target address of the read request and the read request is within the range of the address indicated by the target address setting register. Alternatively, the data holding means may hold the surplus data.

When the data holding means holds the data of the target address of the write request, the supply of the data held in the data holding means is prohibited or the data holding means is prohibited. The data held in the data holding means may be rewritten with the data to be written.

[0017]

According to the present invention, an intermediate buffer is provided between the central processing unit which is the access request source and the synchronous DRAM (SDRAM), and the request data from the central processing unit is provided.
The data and the data ahead of it are read from the SDRAM, the pre-read data is held in the data holding means of the intermediate buffer, and the read request data is read without being read from the SDRAM. Supply.

Further, a plurality of data holding means are provided in the intermediate buffer, and the data holding means is used by switching to the data holding means holding the oldest data in response to a read request. It prevents the new data held in the means from being overwritten.

Further, when the read request indicates that it is an instruction read, the data holding means is made to hold the surplus data, or the read request is made to have a specific data length. , The data holding means is made to hold the surplus data, and the data read is carried out during the instruction access.
Even if a read occurs, the data in the data holding means is prevented from being overwritten.

When the read request is within the address range set in the target address setting register, the intermediate buffer has a target address setting register for setting a target address for holding data. The data holding means is made to hold the surplus data, and even if another read access occurs during the sequential access, the data is also stored.
SD by the subsequent rewriting while being held by the data holding means
Prevents having to reload from RAM.

Further, the target address of the write request is the data
When the address is the address of the data held by the data holding means, it is prohibited to supply the data held in the data holding means or held by the data holding means. Further, the old data is prevented from being supplied by rewriting the data of the target address of the write request to the data to be written.

[0022]

1 is a block diagram showing an embodiment of the present invention. As shown in the figure, the image processing apparatus includes a CPU 1 that controls the entire apparatus and performs image processing, a ROM 2 that stores instructions of the CPU 1 and various parameters, a synchronous DRAM (SDRAM) 3, and an intermediate buffer 4. , A printer interface (printer I / F) 5 for exchanging signals with a printer, and a host interface (host I / F) for exchanging signals with a host computer or the like.
/ F) 6 and an ASIC 7 that interprets a request from the CPU 1 and controls each part of the apparatus. A printer interface 5 and an ASIC 7 which are required to transfer high speed data are connected to a CPU bus 8 which transfers high speed data.
, And the SDRAM 3 is connected to the CPU bus 8 via the intermediate buffer 4. Low-speed bus 9 is ASI
This low-speed bus 9 is connected to the CPU bus 8 via C7.
The ROM 2 and the host interface 6 are connected to.

The CPU 1 has an on-chip cache memory, and at the time of instruction cache miss hit, refill is performed by burst access every 4 words, and data cache miss hit. Sometimes refilling is performed by burst access every 2 words. Further, the CPU 1 indicates whether the read request to the status terminal at the time of read access is read as an instruction or read as data. The SDRAM 3 stores the image data and the CP
U1 instruction and CPU1 working data
Memory etc.

As shown in the internal configuration diagram of FIG. 2, the intermediate buffer 4 includes an intermediate buffer control section 40, a data bus terminal 41 on the CPU bus 8 side, and a data bus terminal on the SDRAM 3 side.
Bus terminal 42, write register 43, SDRAM
A side output buffer 44, a data holding means 45 having, for example, a four-stage FIFO structure, and a data output means 46 including a selector 47, a read register 48, and a CPU side output buffer 49. Have. Intermediate buffer control unit 4
0 controls each part in the intermediate buffer 4, and A
The control signals CLK, SS *, RDE *, WDE *, and RW *, which are control signals for the SDRAM 3 generated by the SIC 7, are input. The * mark of each signal indicates that it is a negative logic. Where CLK is the clock signal,
RDE *, WDE *, RW * control signal sampling, write register 43, read register 48
Used as the sampling clock for the. Also SS
* Is a signal indicating that the target data of the read request is in the data holding means 45, and is used as it is without being sampled by CLK. RDE * is CP
A signal for controlling the enable of the U side output buffer 49, WDE * is a signal for controlling the data writing to the data holding means 45, and RW * is an enable of the SDRAM side output buffer 44. A signal for controlling the bull.

In the intermediate buffer 4, at the time of writing various data, the write data sent from the CPU 1 is input from the data bus terminal 41 on the CPU bus 8 side, and the input write data is input. Data is once latched in the write register 43. At this time, since the SDRAM side output buffer 44 is enabled, the data latched in the write register 43 is buffered in the SDRAM side output buffer 44 and is transferred to the data bus terminal 42 on the SDRAM 3 side. Is output. The write register 43 latches the data once in the SDRAM 3
This is to improve the setup time margin.

At the time of data read, the SDRAM
The data stored in No. 3 is input from the data bus terminal 42 on the SDRAM 3 side and supplied to the data holding means 45 and the selector 47. At this time, the output buffer 44 on the SDRAM side is disabled. Selector 47 is
When the data holding means 45 has read-requested data from the CPU 1, the read-requested data in the data holding means 45 is passed to the read register 48. In addition,
When there is no data requested to be read from the CPU 1 in the data holding means 45, the selector 47 controls the data on the SDRAM 3 side.
The data input from the bus terminal 42 is read by the read register 4
Pass through 8. The data sent to the read register 48 is once latched by the read register 48. CP at this time
Since the U side output buffer 49 is enabled,
The data latched in the read register 48 is CP.
The data is buffered in the U-side output buffer 49 and output to the data bus terminal 41 on the CPU bus 8 side. CP here
When U1 refills the instruction cache memory, the block refill is performed every 4 words, but the SDRAM 3 is read by 8 words. Therefore, the CPU side output buffer 49 outputs only 4 words of the data input from the data bus terminal 42 on the SDRAM 3 side to the data bus terminal 41 on the CPU bus 8 side, and thereafter outputs the data. -Be Bull. On the other hand, the data holding means 45 stores only the last 4 words of the burst read from the SDRAM 3.

Next, the read operation of the image processing apparatus configured as described above will be described with reference to the timing chart of FIG. In FIG. 3, CLK is a clock signal for managing the entire device. ALE is a signal output by the CPU 1, and by asserting this signal, C
It indicates that PU1 is outputting the target address of the access request to the CPU bus 8. AD is an address / data bus of the CPU bus 8 and is used for transfer of both address and data. RD * and Burst * are signals output by the CPU 1, and when the access request of the CPU 1 is a read, the RD * is asserted, and the request is 4-word.
Burst * is asserted when it is a lead for a minute. C
S *, RAS *, CAS *, and WE * are a part of the control signals of the SDRAM 3, and these signals are used for SDRA.
Give a command to M3. That is, when CS * and RAS * are asserted, it is a request to input a low address.
When CS * and CAS * are asserted, a column address input request is shown, and when CS *, RAS * and WE * are asserted, a precharge request is shown. Also, DRA
MD is a data bus of SDRAM3.

First, the ASIC 7 starts RD at the first clock.
Since the * and Burst * assertions are sampled, C
Recognize that PU1 requests a read for 4 words. Further, the ASIC 7 recognizes that the address at that time is (A0) through the AD bus. Inside the ASIC 7, there is an address of the data held in the data holding means 45 of the intermediate buffer 4, and this address is compared with the access request address from the CPU 1. As a result of the comparison, if the address of the data held in the data holding means 45 does not match the access request address, the low address is read at the fourth clock so that the SDRAM 3 reads it. , The column address input request is sent out at the 6th clock, and the SDRAM 3 is made to sample. Upon receiving this request, the SDRAM 3 outputs the first data on the DRAM-D at the 8th clock.
At this time, since RDE * is asserted in the intermediate buffer 4, data is output to the AD bus. However, since SS * is not asserted, the data on the DRAM-D is clocked. Latch at rising edge and retake timing
Output to D bus. Then, this data is sampled by the CPU 1 at the 9th clock.

On the other hand, the SDRAM 3 has, for example, a burst length of 4
Since it is set to sequential mode, 9
Outputs data incremented by clock, 10 clock, and 11 clock. Furthermore, data from SDRAM 3
The column address is sampled at the 10th clock to read the data. In response to this, the SDRAM 3 outputs data from 12 clocks to 4 clocks ahead. At the 12th clock, since RDE * is negated and WDE * is asserted, the output to the AD bus is disabled and the data on the DRAM-D is transferred to the intermediate buffer 4. The data is written in the data holding means 45. AS at the 14th clock
The IC 7 recognizes a new word read request from the CPU 1, but this address is (A4) and the data can be supplied from the data holding means 45 of the intermediate buffer 4, so that the intermediate buffer can be supplied. 4th is 17th clock SS * and RDE *
Allow sampling of the assertions in. SDRA
For M3, CS *, RAS *, and WE * are asserted so that the precharge command can be sampled at the 15th clock in preparation for the next read request, and then the next read. In preparation for a request, the SDRAM 3 is made to sample the row address and the column address at the 17th and 19th clocks, the destination address requested to be accessed is read, and the data is stored in the data holding means 45 of the intermediate buffer 4. .

Since data is often accessed sequentially, the read-ahead data is often requested to be read. In such a case, as described above, the intermediate buffer 4 is provided between the CPU 1 which is the access request source and the SDRAM 3, and the request data from the CPU 1 and the data subsequent thereto are read from the SDRAM 3 and prefetched. Since the data is held in the data holding means 45 of the intermediate buffer 4, the read request data can be supplied without being read from the SDRAM 3. Therefore, data can be supplied at high speed. In addition, the time loss due to prefetching is extremely small because it can be done only by the number of clocks obtained by dividing the prefetched data amount by the bus width.
In many cases, it is completely hidden by the shadow of the bus arbitration cycle, and the penalty can be zero.

Although the above embodiment has been described with respect to the case where the intermediate buffer 4 is provided with one data holding means 45, the intermediate buffer 4 may be provided with a plurality of data holding means.

FIG. 4 shows two data holding means 45a, 45.
The structure of the intermediate buffer 4 provided with b is shown. As shown in the figure, the intermediate buffer controller 40 has CLK, SS *, RD
In addition to the E *, WDE *, and RW * control signals, a control signal FO indicating which of the data holding means 45a and the data holding means 45b is used is input. This control signal FO is used by switching to the data holding means which holds the oldest data among the data holding means 45a and the data holding means 45b when a read request is made. Thus, by switching the data holding means 45a and the data holding means 45b in response to the read request, the new data held in the data holding means is overwritten. The probability can be reduced.

In this case, when the read request indicates that it is an instruction read, if the data holding means 45 holds the preread data, the data is read during the instruction access. Even if a data read occurs, the probability that the data in the data holding means 45 has been rewritten can be reduced.

When the read request has a specific data length, the data holding means 45 holds the prefetched data, and the instruction and other read access data are stored. CPUs having different data lengths can determine that the data is an instruction read. Even if a data read occurs during instruction access, the data in the data holding means 45 is rewritten. You can reduce the probability that you are

When the intermediate buffer 4 has a target address setting register for setting a target address for holding data, and the read request is within the range of the addresses set in the target address setting register. When the pre-read data is held in the data holding means 45, the data holding means 45 holds the data even if another read access occurs during the sequential access. However, the probability of having to reread from the SDRAM 3 can be reduced by the subsequent rewriting.

Further, the target address of the write request is the data
When the address is the address of the data held by the data holding means 45, the data held in the data holding means 45 is C
By prohibiting supply to PU1, the old data
Can be prevented from being supplied. Further, in this case, if the data held at the data holding means 45 is rewritten to the data for writing the target address of the write request, the supply of old data can be prevented. It is possible and SDR when the data is read further
The data can be supplied from the AM3 without reading the data.

[0037]

As described above, according to the present invention, an intermediate buffer is provided between the access request source CPU and the SDRAM, and the request data from the CPU and the subsequent data are read from the SDRAM. Since the prefetched data is held in the data holding means of the intermediate buffer, SDR
The read request data can be supplied without being read from the AM, and the data can be supplied at high speed.

By providing a plurality of data holding means in the intermediate buffer and switching to the data holding means holding the oldest data at the time of a read request, the data holding means is used.
It is possible to prevent the new data held in the data holding means from being overwritten.

When the plurality of data holding means are switched, if the read request indicates that it is an instruction read, the data holding means holds the prefetched surplus data. Even if a data read occurs during instruction access, it is possible to prevent the data in the data holding means from being overwritten.

When the read request has a specific data length, the data holding means holds the prefetched surplus data, and the instruction and other read access data are stored. Instructions for CPUs with different data lengths
It is possible to judge that the data is the data and it is possible to reduce the probability that the data of the data holding means is rewritten even if the data read occurs during the instruction access.

When the intermediate buffer 4 has a target address setting register for setting a target address for holding data and the read request is within the range of the addresses set in the target address setting register. When the data holding means holds the prefetched surplus data, it is held in the data holding means even if another read access occurs during the sequential access. Subsequent rewriting can reduce the probability of having to reread from the SDRAM.

Further, the target address of the write request is the data
When the address of the data stored in the data storage means is an address, it is possible to prevent the supply of the data stored in the data storage means to supply the old data. Can be prevented.

Further, if the data held by the data holding means is rewritten to the data for writing the target address of the write request, the supply of old data can be prevented. At the same time, when the data is further read, the data can be supplied from the SDRAM without being read, and the data can be supplied quickly.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an intermediate buffer of the above embodiment.

FIG. 3 is a time chart showing the operation of the above embodiment.

FIG. 4 is a block diagram showing a configuration of an intermediate buffer according to another embodiment.

[Explanation of symbols]

 1 CPU 2 ROM 3 Synchronous DRAM (SDRAM) 4 Intermediate buffer 7 ASIC 40 Intermediate buffer control unit 45 Data holding means 46 Data output means 47 Selector 48 Read register 49 CPU side output buffer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tomoki Ishii 1-3-6 Nakamagome, Ota-ku, Tokyo Inside Riko Co., Ltd.

Claims (7)

[Claims] 1. An image processing apparatus having a central processing unit and a storage device comprising a synchronous DRAM, wherein an intermediate buffer is provided between the central processing unit and the storage device, and the intermediate buffer is sent from the storage device. It has a data holding means for holding data and a data output means, and the data output means has the data holding means for the data of the target address of the read request.
When the data is held, the held data is output to the data holding means, and when the data holding means does not hold the data of the target address of the read request, the request data is output. An image processing apparatus characterized in that more data than the data length is read from the storage device, only the requested data is output, and the surplus data is held by the data holding means. 2. An image processing apparatus having a central processing unit and a storage device comprising a synchronous DRAM, wherein an intermediate buffer is provided between the central processing unit and the storage device, and the intermediate buffer is sent from the storage device. It has a plurality of data holding means for holding data and data output means, and the data output means holds the data of the target address of the read request by the data holding means. When the data holding means outputs the data held in the data holding means, and when the data holding means does not hold the data of the target address of the read request, it is larger than the requested data length. Data is read from the storage device, only the requested data is output, and the data holding means that does not hold valid data or the access request source has already been output. If there is data holding means that supplies data, Data holding means for holding the surplus data, and the data holding means for not holding valid data and the data holding means for already supplying the data to the access request source. An image processing apparatus characterized in that, when there is no data, the data holding means holding the oldest data holds the surplus data. 3. When the data holding means does not hold the data of the target address of the read request and the read request is an instruction, the surplus data is stored in the data holding means.
The image processing apparatus according to claim 1, wherein the image processing apparatus holds the data. 4. When the data holding means does not hold the data of the target address of the read request and the read request has a specific data length, the data holding means The image processing apparatus according to claim 1 or 2, which retains excess data. 5. When the data holding means does not hold the data of the target address of the read request and the read request is within the range of the address indicated by the target address setting register. 3. The image processing apparatus according to claim 1, wherein the data holding means holds the surplus data. 6. The method according to claim 1, wherein the supply of the data held in the data holding means is prohibited when the data of the target address of the write request is held in the data holding means. 5. The image processing device according to any one of 5. 7. When the data holding means holds the data of the target address of the write request, the data held in the data holding means is rewritten to the data to be written. The image processing apparatus according to claim 1.