JPH07230421A - Information processing equipment - Google Patents

Abstract

(57) [Summary] [Purpose] An object of the present invention is to provide an information processing apparatus with excellent workability that can reduce the processing waiting state of a bus master and improve the overall processing speed. [Configuration] An internal memory 17, an input / output unit 18 having a low processing speed, first and second bus buffers 20 and 21 for disconnecting the first and second bus masters 15 and 16 from the system bus 8, An address storage unit 22 that stores the address of the input / output unit 18, and first and second bus masters 15 and 1
6, a conflict determination unit 23 that determines whether a conflict has occurred,
If the addresses accessed by the second bus masters 15 and 16 are the same as those stored in the address storage unit 22 and the comparison unit 24 that compares the addresses, the first and second bus masters 15 and 16 are compared. And a high-speed processing priority execution unit 25 for giving the right to use the system bus 8 to the other first and second bus masters 15 and 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a central processing unit (hereinafter abbreviated as CPU), direct memory access (hereinafter DM).
The present invention relates to a multi-bus master system information processing apparatus in which a system bus is shared by two or more bus masters each having a mechanism or the like.

[0002]

2. Description of the Related Art In recent years, with the increase in CPU processing speed,
Various improvements have been made to improve the data transfer speed in the system bus to which the CPU is connected to improve the processing speed of the entire information processing apparatus.

A conventional information processing apparatus will be described below with reference to the drawings. FIG. 6 is a circuit block diagram of a conventional information processing apparatus. 1 is a system bus 8 described later
First, which consists of a CPU and a DMA mechanism that requests the right to use
Bus master, 2 is a second bus master similar to the first bus master 1, 3 is a bus arbiter that permits a bus master that has requested the right to use the system bus 8 to use the system bus 8, and 4 is a system bus 8 to be described later. And a first bus buffer for disconnecting the first bus master 1 from the
Reference numeral 5 is a second bus buffer for disconnecting a system bus 8 and second bus master 2 described later, 6 is a RAM,
Internal storage device 7 including a ROM and the like for storing data, etc.
Is an input / output device for connecting a device such as a printer (not shown) to the information processing device, and 8 is a system for connecting the bus masters, the internal storage device 6, the input / output device 7, etc. to transfer data. Bus, 9 is a first bus request signal for the first bus master 1 to request the right to use the system bus 8, and 10 is a first bus request signal indicating that the first bus master 1 has acquired the right to use the system bus 8. Bus grant signal,
Reference numeral 11 is a first bus acknowledge signal indicating that the first bus master 1 is using the system bus 8, and 12 is a second bus for the second bus master 2 to request the right to use the system bus 8. Request signal, 13 is a second bus grant signal indicating that the second bus master 2 has acquired the right to use the system bus 8, and 14 is the second bus master 2.
Is a second bus acknowledge signal indicating that the system bus 8 is being used.

The operation of the conventional information processing apparatus configured as described above will be described below. FIG. 7 is a flowchart in the conventional information processing apparatus, and FIG. 8 is a timing chart in the conventional information processing apparatus.

First, as shown in FIG. 8, when the system bus 8 is in an unused state, the first bus master 1 acquires the system bus 8 and requests the I / O device 7 for access. The bus request signal 9 of 1 is output (S
1). Next, since the system bus 8 is currently unused,
The bus arbiter 3 transfers the system bus 8 to the first bus master 1.
1st bus grant signal 1
0 is output (S2). Next, the first bus master 1 outputs the first bus acknowledge signal 11 indicating that the system bus 8 is being used (S3). Here, the first bus master 1 that has acquired the right to use the system bus 8
Access to the input / output device 7 is started. Next, the second bus master 2 outputs the second bus request signal 12 in order to access the internal storage device 6 (S4). Here, since the first bus master 1 is using the system bus 8, the second bus master 2 continues to wait for the processing in the input / output device 7 to end. Next, in order to determine whether the processing of the first bus master 1 is completed, it is determined whether the first bus acknowledge signal 11 is released (S).
5). If No, the system waits for the release of the first bus acknowledge signal 11, and if Yes, the bus arbiter 3 permits the second bus master 2 to acquire the right to use the system bus 8. Bus grant signal 13
Is output (S6). Next, the second bus master 2 outputs the second bus acknowledge signal 14 indicating that the system bus 8 is being used (S7). At this point, the second bus master 2 that has acquired the right to use the system bus 8
Starts access to the internal storage device 6.

[0006]

However, in the above-mentioned conventional configuration, when one bus master accesses an input / output device or the like having a speed lower than that of the internal memory or the like, another bus master acquires the right to use the system bus. Requesting
Until the bus master that has the right to use the system bus completes a long-time process, the bus master that requested the right to use the system bus waits for processing, increasing the processing time of the entire information processing device. However, there is a problem in that workability is lacking.

The present invention solves the above-mentioned conventional problems, and provides an information processing apparatus excellent in workability which can reduce the processing waiting state of a bus master and improve the processing speed as a whole. With the goal.

[0008]

In order to achieve this object, an information processing apparatus according to the present invention comprises two or more bus masters composed of a CPU and the like, two or more bus slaves shared by the bus masters, a bus master and a bus slave. An information processing apparatus comprising: a system bus for connecting a bus, an internal memory that forms a bus slave, an input / output unit that forms a bus slave and has a lower speed than the internal memory, and each bus master and the system bus. Bus buffers connected between each other, an address storage unit that stores addresses on the system bus such as an input / output unit, and when the bus master is using the system bus, other bus masters request the use of the system bus. Contention determination unit that determines whether a conflict has occurred, and if the contention determination unit determines that a contention has occurred, The system bus is used by the comparison unit that compares the address accessed by the master on the system bus with the address stored in the address storage unit, and if the comparison result of the comparison unit matches. And a high-speed processing priority execution unit that gives the right to use the system bus to the bus master that has requested the use of the system bus.

Here, as the bus master, CPU, D
MA mechanism and the like.

[0010]

With this configuration, when the address storage unit stores the address on the system bus of the bus slave having a slow processing speed such as the input / output unit, the contention determination unit determines when a certain bus master is using the system bus. Another bus master requests the right to use the system bus to determine whether a conflict has occurred, and when the comparison unit determines that a conflict has occurred, the bus master using the system bus accesses the bus. The address on the system bus that is being used is compared with the address stored in the address storage unit, and if the two match, the high-speed processing priority execution unit is currently using the system bus, and the low-speed input / output unit, etc. The bus master that is accessing the
Since the system bus usage right is given to another bus master that has requested the usage right of the system bus, the processing by the other bus master can be preferentially executed, and the processing waiting state of the bus master can be reduced. The processing speed can be improved.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An information processing apparatus according to an embodiment of the present invention will be described below with reference to the drawings. 1 is a functional block diagram of an information processing apparatus according to an embodiment of the present invention, and FIG. 2 is a circuit block diagram of the information processing apparatus according to an embodiment of the present invention. 1 is the first bus master, 2 is the second
Bus master, 3 is a bus arbiter, 4 is a first bus buffer, 5 is a second bus buffer, 6 is an internal storage device, 7
Is an input / output device, 8 is a system bus, 9 is a first bus request signal, 10 is a first bus grant signal, 11 is a first bus acknowledge signal, 12 is a second bus request signal, and 13 is a second bus request signal. 2 bus grant signals, 14 second
Of the bus acknowledge signal, which are the same as those in the conventional example, the same reference numerals are given and the description thereof will be omitted. 1
5 is a first bus master having a right to use the system bus 8,
16 is a second bus master similar to the first bus master 15, 17 is an internal memory accessed by the first bus master 15 or the second bus master 16, and 18 is accessed by the first bus master 15 or the second bus master 16. An input / output unit that is slower than the internal memory 17, an input / output bus latch unit 19 that is connected between the system bus 8 and the input / output unit 18 and temporarily stores information on the system bus 8, and 20 is a first input / output bus latch unit. A first bus buffer connected between the first bus master 15 and the system bus 8 for disconnecting the first bus master 15 from the system bus 8;
Reference numeral 21 is a second bus buffer similar to the first bus buffer 20 connected between the second bus master 16 and the system bus 8, and 22 is on the system bus 8 such as the input / output unit 18 having a slow processing speed. Address storage unit for storing addresses, 2
Reference numeral 3 denotes a contention determination unit that determines whether one bus master is using the system bus 8 and another bus master requests the use of the system bus 8 to cause a contention. Reference numeral 24 indicates that the contention determination unit 23 has a contention. When it is determined, a comparison unit that compares the address on the system bus 8 accessed by the bus master using the system bus 8 with the address stored in the address storage unit 22, 25 is a comparison unit 24. When the comparison results of the two match, the high-speed processing for disconnecting the bus master currently using the system bus 8 from the system bus 8 by the bus buffer and giving the right to use the system bus 8 to the bus master requesting the use of the system bus 8 It is a priority execution unit. In FIG.
Reference numeral 26 is a bus buffer / bus master control device that constitutes the high-speed processing priority execution unit 25 and controls the bus master and the bus buffer. Reference numeral 27 is an address on the system bus 8 accessed by the bus master using the system bus 8 A comparator for comparing the addresses registered in the address registration storage device 28, an address registration storage device 28 for configuring the address storage unit 22 and registering an address on the system bus 8 such as the input / output device 7 having a low processing speed, 29
Is a bus latch that constitutes the input / output bus latch unit 19 and temporarily stores information of the system bus 8, 30 is a first output enable signal that permits output of information from the first bus master 1, and 31 is a first output enable signal. A first wait signal for stopping the processing at the bus master 1, 32 is a second output enable signal for permitting the output of information from the second bus master 2, and 33 is for stopping the processing at the second bus master 2. The second wait signal, 34 is a latch signal for controlling the bus latch 29, and 35 is the bus buffer / bus master control unit 26 which bus master is the system bus 8.
Is a bus master number signal for notifying whether the bus is being used, 36 is a disconnect signal for instructing disconnection of the bus master which is currently using the system bus 8 from the system bus 8, and 37 is a bus master number which is using the system bus 8. This is a disconnection request signal for requesting disconnection from the system bus 8.

The operation of the information processing apparatus having the above-described structure according to the embodiment of the present invention will be described below. 3 is a flowchart of the information processing apparatus according to the embodiment of the present invention, FIG. 4 is a timing chart when the buses of the information processing apparatus according to the embodiment of the present invention compete, and FIG. 7 is a timing chart when the buses of the information processing devices in the embodiment do not conflict with each other. Here, first, as shown in FIG. 4, a case where the second bus master 2 requests access to the internal storage device 6 while the first bus master 1 is accessing the input / output device 7 will be described. explain.

First, the first bus master 1 outputs the first bus request signal 9 to access the input / output device 7 (S8). Next, the bus arbiter 3 recognizes that the system bus 8 is unused by the bus acknowledge signal and the disconnect signal 36 which indicate which bus master is accessing the system bus 8 (S9). Next, the bus arbiter 3 permits the first bus master 1 to use the system bus 8 and the first bus grant signal 10 and the bus master indicating that the first bus master 1 has acquired the right to use the system bus 8. The number signal 35 is output (S10). Next, the bus buffer / bus master controller 26 outputs the first output enable signal 30 to connect the first bus master 1 and the system bus 8 (S11). Then the first
Of the first bus request signal 9 by the bus master 1 of
Is released, the first bus master 1 outputs the first bus acknowledge signal 11 notifying that the system bus 8 is being used, and the first bus master 1 obtains the control right of the system bus 8. At the same time, the second bus master 2 outputs the second bus request signal 12 requesting the right to use the system bus 8 (S1).
2). Next, the bus arbiter 3 determines that a conflict has occurred and determines that the first bus master 1 that is using the system bus 8
The disconnection request signal 37 for requesting disconnection from the system bus 8 is output (S13). Next, the comparator 27 compares the address accessed by the first bus master 1 indicated by the address line of the system bus 8 with the address registered in the address registration storage device 28 to check whether they match ( S14). Here, it is assumed that the address registration storage device 28 stores the address on the system bus 8 of the input / output device 7 having a slow processing speed.

If Yes, that is, if the first bus master 1 is accessing a low speed slave, a disconnect signal for disconnecting the first bus master 1 and the system bus 8 currently using the system bus 8 from each other. 36 is output (S15). Next, the bus arbiter 3 outputs the second bus grant signal 13 to the second bus master 2 and the bus master number signal 35 indicating that the second bus master 2 has acquired the right to use the system bus 8 ( S
16). Next, the bus buffer / bus master controller 26
Thus, the first wait signal 31 and the second output enable signal 32 are output, the first output enable signal 30 is temporarily released, and the first bus master 1 is disconnected from the system bus 8 (S17).
At this point, the second bus master 2 acquires the right to use the system bus 8 and starts accessing the internal storage device 6. Next, the internal storage device 6 is operated by the second bus master 2.
When the processing of 1 is completed, it is determined whether or not the second bus acknowledge signal 14 is released in order to determine whether or not the right to use the system bus 8 is released (S18). If No, jump to S18, and if Yes,
The bus arbiter 3 determines that there is no conflict,
The disconnection request signal 37 that requests disconnection of the first bus master 1 and the system bus 8 is released (S1
9). Next, the comparator 27 recognizes that the disconnection request signal 37 has been released, and releases the disconnection signal 36 (S20). Next, Bus Arbiter 3
Outputs a bus master number signal 35 indicating that the first bus master 1 has acquired the usage right on the system bus 8 (S21). Next, the bus buffer / bus master controller 26 separates the system bus 8 from the second bus master 2 so as to disconnect the second output enable signal 32 and the first wait signal 31 of the first bus master 1.
And the first output enable signal 30 for giving the right to use the system bus 8 to the first bus master 1 is output again (S22). At this point, the first bus master 1 obtains the right to use the system bus 8 again and restarts the access to the input / output device 7.

On the other hand, if No in S14, that is, if the first bus master 1 is accessing a high-speed slave, the disconnect signal 36 is not output from the comparator 27 as shown in FIG. In order to determine whether the processing of the bus master 1 has been completed, it is determined whether the first bus acknowledge signal 11 has been released (S23). If No, jump to S23,
In the case of Yes, the disconnection request signal 37 is released and the second bus grant signal 13 and the bus master number signal 35 are output (S24). Next, the first output enable signal 30 is released and the second output enable signal 32 is output (S25). Here, from this point, the second bus master 2
Obtains the right to use the system bus 8 and the processing in the input / output device 7 is started.

[0016]

As described above, according to the present invention, the address storage unit stores the address on the system bus of the bus slave having a slow processing speed such as the input / output unit, and the contention determination unit is assigned to the bus master. When another bus master requests the right to use the system bus and determines whether a conflict has occurred, the comparison unit uses the system bus when the conflict determination unit determines that a conflict has occurred. The address on the system bus being accessed by the bus master that is accessing is compared with the address stored in the address storage unit, and if the two match, the high-speed processing priority execution unit is currently using the system bus. The bus master that is accessing the low-speed input / output unit is separated from the system bus by using the bus buffer, and the system is sent to another bus master that has requested the right to use the system bus. Since the right to use the bus is given, the processing by other bus masters can be executed with priority to reduce the processing waiting state of the bus master, and the overall processing speed can be improved. The processing device can be realized.

[Brief description of drawings]

FIG. 1 is a functional block diagram of an information processing device according to an embodiment of the present invention.

FIG. 2 is a circuit block diagram of an information processing device according to an embodiment of the present invention.

FIG. 3 is a flowchart of an information processing device according to an embodiment of the present invention.

FIG. 4 is a timing chart when the buses of the information processing devices compete with each other according to the embodiment of the present invention.

FIG. 5 is a timing chart when the buses of the information processing devices do not conflict with each other in the embodiment of the present invention.

FIG. 6 is a circuit block diagram of a conventional information processing device.

FIG. 7 is a flowchart of a conventional information processing device.

FIG. 8 is a timing chart of a conventional information processing device.

[Explanation of symbols]

 1,15 First Bus Master 2,16 Second Bus Master 3 Bus Arbiter 4,20 First Bus Buffer 5,21 Second Bus Buffer 6 Internal Storage Device 7 Input / Output Device 8 System Bus 9 First Bus Request Signal 10 First Bus Grant Signal 11 First Bus Acknowledge Signal 12 Second Bus Request Signal 13 Second Bus Grant Signal 14 Second Bus Acknowledge Signal 17 Internal Memory 18 Input / Output Section 19 Input / Output Bus Latch Section 22 Address storage unit 23 Contention determination unit 24 Comparison unit 25 High-speed processing priority execution unit 26 Bus buffer / bus master control device 27 Comparator 28 Address registration storage device 29 Bus latch 30 First output enable signal 31 First wait signal 32 Second Output enable signal 33rd Wait signal 34 latch signal 35 bus master number signal 36 Disconnect signal 37 Disconnect request signal

Claims (1)

[Claims] 1. An information processing system comprising: two or more bus masters including a central processing unit; two or more bus slaves shared by the bus masters; and a system bus connecting the bus masters and the bus slaves. A device, an internal memory that constitutes the bus slave, an input / output unit that constitutes the bus slave and is slower than the internal memory, and a bus buffer connected between each of the bus masters and the system bus. And an address storage unit that stores an address on the system bus, such as the input / output unit, and when the bus master is using the system bus, another bus master requests the use of the system bus and competes therewith. And the system bus used when it is determined that a conflict has occurred. When the comparison result of the comparison unit and the comparison unit that compares the address on the system bus being accessed by the bus master with the address stored in the address storage unit are the same, A high-speed processing priority execution unit that disconnects the bus master that is using the system bus by a bus buffer and gives the right to use the system bus to the bus master that has requested the use of the system bus. Information processing equipment.