JPH0723064A - Encoding and decoding method and modem - Google Patents

Abstract

PURPOSE:To suppress jitter, and to attain self-synchronization and synchronization restoration by outputting a specific state code, state change code, and state change position code according to the change of a sampled value obtained by sampling input data. CONSTITUTION:An encoding part 2 operates encoding based on the sampled value of the input data sampled by a sampling unit 1, and a transmitting part 3 transmits an encoded signal as a carrier pulse. Also, a receiving part 4 equalizes a received signal and outputs a sampling clock and an identification signal, a decoding part 6 decodes the data, and a frequency-divider 5 frequency- divides the sampling clock, and generates the basic clock of a carrier frequency. Then, when the sampled value of the sampling unit 1 is not changed within one period of the basic clock, the encoding part 2 outputs the value of one period, 1 or 0 as the state code. Also, when the sampled value is changed, the encoding part 2 outputs the state change code indicating the direction of the change, and the state change position code indicating whether the change is generated at the first half or latter half of the basic clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in an asynchronous pulse modulation / demodulation system of a data transmission system in which a modulated signal frequency of input data and a carrier frequency are not an integer ratio. The present invention suppresses jitter in a data transmission system in which a modulation signal is encoded and data is transmitted by multipoint sampling when the modulation signal frequency and the carrier frequency are not an integer ratio, and self-synchronization and synchronization are performed in a decoding unit. The present invention relates to a recoverable encoding / decoding method and a modulation / demodulation device therefor.

[0002]

2. Description of the Related Art In the transmission of digital signals in a digital communication system, when the modulation signal frequency and the carrier frequency of the transmission line are equal to each other or equal to an integral multiple thereof, the logical value 1, 0 of the modulation signal is the direct carrier wave. It can be converted into the presence or absence of pulse, and an efficient modulation method can be realized.

However, if the modulation signal frequency and the carrier frequency are not equal to each other or cannot be an integral multiple thereof, the logical values 1 and 0 of the modulation signal cannot be directly converted into the presence or absence of the carrier pulse. A conventionally known method of pulse-modulating an asynchronous signal is a method of sampling a modulation signal by using a carrier frequency as a sampling pulse and making one pulse of the modulation signal correspond to a plurality of carrier pulses.

[0004]

First, when the modulation signal frequency and the carrier frequency are asynchronous, it is considered that the change points of the modulation signal occur randomly during the sampling interval TS, so that the maximum TS interval is available at the time of demodulation. However, there is a problem in that the error, that is, the jitter is generated on the time axis.

In order to improve this problem, it is necessary to reduce the sampling interval to an integer fraction. In the above-mentioned conventional asynchronous pulse modulation method, this means that the carrier frequency is directly multiplied by an integer, and thus there is a problem in that the transmission efficiency at the time of transmitting the modulated signal decreases.

In order to solve this problem, a sampling frequency is set to an integral multiple of the carrier frequency, and a signal obtained by encoding the changing point position of the modulation signal, the value of the modulation signal, etc. based on the sampling result is transmitted as a carrier pulse. A method of doing is also possible. In this method, it is premised that the encoding and the decoding are synchronized, that is, the decoder correctly recognizes what the current signal is being received. However, there is a problem in establishing synchronization between the encoder and decoder at the start of transmission and resynchronization when synchronization is lost due to an error on the transmission path. There is a problem of how to do it easily.

The present invention solves the above-mentioned problems.
In a data transmission method in which an asynchronous signal is encoded by multipoint sampling for data transmission, jitter is suppressed, and a decoder is capable of self-synchronization and synchronization recovery, and its transmission efficiency is high. Another object of the present invention is to provide a modulation / demodulation device therefor.

[0008]

The first aspect of the present invention is to:
The present invention relates to an encoding method using an asynchronous pulse modulation method, and in the encoding method of input data when the carrier frequency is asynchronous with the modulation frequency of the input data, a sample value obtained by sampling the input data with a sampling clock is 1 of the carrier frequency. If it does not change within the cycle, a status code (c _n-1 ) indicating whether the input data one time series before is 1 or 0 is output, and the sample value of the input data is within one cycle of the carrier frequency. If it changed outputs the input data state change code indicating whether it has changed from 1 or changes from 0 to 1 to 0 (a _n), followed by the change time point is set in the first half of one cycle of the carrier frequency It is characterized in that the state change position code (b _n ) indicating whether it is the latter half or the latter half is output.

A second aspect of the present invention relates to the method of decoding the coded signal, which is the state code (c _n ) and the state code (c _n ) at the time of n (n is a time series) of the received data code. The change code (a _n ) is the same, and the state code (c _n ) at the time point n and the state change code (a _{n + 1} ) at the time point _{n + 1} establish self-synchronization based on a different rule. It is characterized in that the received data is decoded by performing code determination based on the time-series state code, state change code, and state change position code.

When a change point is detected in the received data, post-detection determination processing for determining whether the state change code and the state code are the same for the three bits after the change point is performed. If and are equal,
It is possible to determine the code based on the state change code, the state change position code, and the state code, decode the received data, and hold the current output when the state change code and the state code are not equal.

A third aspect of the present invention relates to a modulation / demodulation apparatus used in the above-mentioned coding / decoding method, and a sampling device for sampling input data on the basis of a sampling clock, and sampling by this sampling device. An encoding unit that encodes based on a sample value, a transmitting unit that transmits the signal encoded by this encoding unit as a carrier pulse, and a sampling clock that equalizes the signal received from the transmission line and performs timing extraction and reproduction. In a modulation / demodulation device including a receiving unit that outputs the identification signal and a decoding unit that decodes the signal reproduced by the receiving unit, the sampling clock output from the receiving unit is divided to obtain the basic clock of the carrier frequency. The encoder includes a frequency divider for generating the basic clock output from the frequency divider, and the sampling value of the sampler It is determined whether the value has changed within one cycle of the basic clock. If it does not change, the value for one cycle is output as a status code. If it changes, whether the value changes from one logical value to the other logical value. Decoding means provided with means for outputting a state change code indicating whether the other logic value has changed to one logic value and a state change position code indicating whether the change is the first half or the second half of the basic clock. The converting unit inputs the basic clock output from the frequency divider, and the received signal reproduced by the receiving unit has the same state code and state change code at the time point n (n is a time series). , Next n +
Decoding the received data by establishing self-synchronization based on the rule that the state change code at time point 1 is not equal to the state code at time point n and determining the state code, the state change code, and the state change position code. It is characterized in that it is provided with a means for performing the conversion.

The decoding unit detects a change in the logic of the received data, a unit that detects that the status code and the status change code are equal in three bits after the change point, and a status. When the code and the state change code are the same, a unit for determining and decoding the logical value of the received data at the time based on the state change code, the state change position code, and the state code can be provided.

Further, the encoding unit and the decoding unit may include a shift register therein, and a unit for inputting the sample value of the input data and the received signal to the shift register for shifting.

[0014]

First, the encoding will be described. When one cycle of the carrier wave frequency is used as a basic cycle, when the input data (modulated signal) sampled at multiple points does not change between the basic cycles, the state signal c _n-1 indicating the value of the previous cycle as it is.
Is output. 0 to 1 when changing within the basic period
The state change code a _n indicating either the change to 1 or the change from 1 to 0 is output. Then, the state change position code b _n indicating whether the change occurs in the first half or the latter half of the basic cycle is output following the state change code a _n .

The following rules apply to this encoded data.

Rule 1 a _n = c _n Rule 2 c _n ≠ a _{n + 1 In the} decoding by the decoding unit, the above Rule 1 and Rule 2
Establish self-synchronization based on. Then, the state code c _n-1 , the state change code a _n , and the state change position code b _n are determined and the received data is decoded.

In this decoding procedure, first, when the change point of the encoded data is detected by the change point detection process, it is confirmed whether Rule 1 is satisfied by the 3 bits after the detected change point, and it is established. In this case, the output data is created by decoding with the state code c, the state change code a, and the state change position code b, and the change point detection process is started again from the state code c and thereafter. On the other hand, when the rule 1 is not satisfied, the output data holds the current output and shifts to the change point detection processing immediately after the change point.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a modulation / demodulation device according to an embodiment of the present invention.

A sampling device 1 for sampling input data based on a sampling clock, a coding unit 2 for coding based on sample values sampled by the sampling device 1, and a coding unit for coding by this coding unit. A transmitting unit 3 for transmitting the received signal as a carrier pulse, a receiving unit 4 for equalizing the received signal, performing timing extraction and reproduction, and outputting a sampling clock and an identification signal, and a decoding unit for decoding the signal reproduced by the receiving unit 4. In the modulation / demodulation apparatus including the encoding unit 6, a frequency divider 5 that divides the sampling clock output from the receiving unit 4 to generate a basic clock of the carrier frequency is provided as the present embodiment, and the encoding unit 2 includes , The basic clock output from the frequency divider 5 is input, it is determined whether the sampled value of the sampler has changed within one cycle of the basic clock, and it is not changed. If so, the value for one cycle, 1 or 0, is output as the state code, and if it changes, the state change code indicating whether the value has changed from 1 to 0 or 0 to 1, and the change is The decoding unit 6 is provided with means for outputting a state change position code indicating whether it is the first half or the second half of the basic clock, and the decoding unit 6 inputs the basic clock output from the frequency divider 5 and reproduces it in the receiving unit 4. For the received signal, the state code and the state change code at the time point n (n indicates a time series) are equal, and the state change code at the time point n + 1 and the state code at the time point n in the next time series are equal. Means is provided for establishing self-synchronization based on a rule that does not exist, determining the status code, the status change code, and the status change position code and decoding the received data.

FIG. 2 is a block diagram showing the configuration of the encoding unit 2, and FIG. 3 is a block diagram showing the configuration of the decoding unit 6.

The encoding unit 2 comprises a shift register circuit 11 and an encoding circuit 12, and the shift register circuit 1
The sampling value of the input data sampled by the sampling clock in the sampling unit 1 is input to the input terminal 1, and the coding is performed by determining at which point in the basic clock the sampling value has changed to which state. Similarly, the decoding unit 6 also includes a shift register circuit 13 and a decoding circuit 14,
The change point of the received data is detected to establish self-synchronization, and the decoding process is performed based on the detection of the change point.

The encoding and decoding operations of the embodiment of the present invention will be described with reference to the timing chart for explaining the encoding and decoding of the input data in FIG.

First, in the encoding of this embodiment, the input data is sampled by the sampling clock 22 which is twice the carrier frequency 21.

If the sampled value does not change during one cycle of the carrier frequency (the basic clock 21 output from the frequency divider 5), the value of the input data 23 as the encoded data 24 is used as it is as the state code c _n-1. It outputs according to the basic clock 21 output from the frequency divider 5.

When the sampled value changes during one cycle of the basic clock 21, it is judged whether it is "change from 0 to 1" or "change from 1 to 0". 1 "to 1
If it is → 0, "0" is output as encoded data 24 according to the basic clock 21 output from the frequency divider 5 as the state change code a _n . Further, it is determined whether the change has occurred in the second half of the first half of the fundamental period, was if "0" occurs in the first half, was if "1" occurs in the second half as a state change position code b _n, the state change code a _n Followed by basic clock 2
Output according to 1.

Since the change from "0" to "1" of the input data 23 of FIG. 4 at the time n occurs in the first half of the basic clock, the status code a _n at the time _n becomes "1" and continues. The state change position code b _n becomes “0”, and the state code c _n
Becomes "1". Further, since the time point n + 1 when the input data 23 changes from "1" to "0" occurs in the latter half of the basic clock, the state change code a _{n + 1} is "0" and the state change position code b _{n + 1.} Is "1" and the state code cn _{+ 1} is "0".

The following rules are established for this encoded data.

Rule 1 a _n = c _n Rule 2 c _n ≠ a _{n + 1 In} decoding, self-synchronization is established using this rule, and the state change code a, the state change position code b, and the state code c
Each sign of is determined.

The decoding procedure is a repetition of the change point detection process, the post-detection determination process, and the decoding process.

First, when the change point of the encoded data is detected in the change point detection processing, the process proceeds to the post-detection determination processing. In the post-detection determination process, the rule 1
Check whether is satisfied.

Here, when the rule 1 is established,
The process shifts to the decoding process, the output data is created by decoding with the respective values of the state change code a, the state change position code b, and the state code c, and the process proceeds to the next change point detection process from the state code c and thereafter. On the other hand, when the rule 1 is not established, the output data holds the current output, and shifts to the change point detection processing immediately after the next change point.

The output data 25 of this embodiment and the output data 26 of the conventional method are shown in comparison. It can be seen that the encoding of the present embodiment can suppress the jitter to 1/2 of the carrier pulse width as compared with the conventional method.

Next, the decoding when noise is mixed in as input data will be described with reference to FIG. In this case, noise that changes from “0” to “1” within the basic cycle and immediately returns from “1” to “0” occurs, and the state change code a _n is “1”, state change as encoded data. position code is "1", even if the state code c _n generates a code to be "0", a _n ≠ c _{n + 1} since the decoded output data 33 does not change state. Therefore, the influence of noise is eliminated.

Next, FIG. 6 shows the timing in the case where an error occurs during data transmission and a loss of synchronization occurs, and the synchronization recovery operation will be described.

Assuming that the input data 34 to be transmitted is in the state shown in FIG. 6, if the state code a _{n of the} encoded data 35 input to the decoding unit 6 is missing due to an error, the change point detection is in the state. The change point is detected by the change position code b _n , but regarding the 3 bits after the change point, the above-mentioned rule 1 is used.
Holds, the current output is retained. When the determination processing after detection is performed by the change point detection at the next time of n + 1, Rule 1 is established and the decoding processing is performed. Similarly, at the time of n + 2, the rule 1 is established and the decoding process is performed. Therefore, even if an error occurs during data transmission and the synchronization is lost, the synchronization can be restored only by performing the decoding process.

[0037]

As described above, according to the present invention, jitter can be suppressed in the encoding by the multipoint sampling of the asynchronous modulation system. Also, the transmission efficiency is improved. Further, the self-synchronization establishment and the synchronization recovery in the decoder can be facilitated.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a modulation / demodulation device to which the present invention is applied.

FIG. 2 is a block diagram showing the configuration of a modulator according to the embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a demodulation unit according to an embodiment.

FIG. 4 is a timing chart for explaining encoding / decoding according to the embodiment of the present invention.

FIG. 5 is a timing chart for explaining coding / decoding during abnormal operation in the embodiment of the present invention.

FIG. 6 is a timing chart for explaining encoding / decoding during abnormal operation in the embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 sampler 2 encoding part 3 transmitting part 4 receiving part 5 frequency divider 6 decoding part 11, 13 shift register circuit 12 encoding circuit 14 decoding circuit

Claims (6)

[Claims] 1. A coding method of input data in the case where a carrier frequency is asynchronous with a modulation frequency of input data, when a sample value obtained by sampling the input data with a sampling clock does not change within one cycle of the carrier frequency. A state code (cn _-1 ) indicating whether the input data one time series before is 1 or 0 is output, and when the sample value of the input data changes within one cycle of the carrier frequency, the input data is Change from 0 to 1 1
A state change code (a _n ) indicating whether the carrier frequency has changed from 0 to 0, and then a state change position code (b) indicating whether the change time point is the first half or the second half of one cycle of the carrier frequency.
A coding method characterized by outputting _n ). 2. A decoding method for decoding received data encoded according to claim 1, wherein a state code (c _n ) and a state change code at a point of n (n is a time series) of the received data code. (A _n ), the state code (c _n ) at the time point of n and the state change code (a _{n + 1} ) at the time point of _{n + 1} establish self-synchronization based on a different rule. A decoding method for decoding received data by performing code determination based on the state code, the state change code, and the state change position code in. 3. When a change point is detected in the received data, post-detection determination processing for determining whether or not the state change code and the state code are the same for the three bits after the change point is performed. If and are equal, the code is determined based on the state change code, the state change position code, and the state code to decode the received data, and if the state change code and the state code are not equal, the current output is held. The decoding method according to claim 2. 4. A sampling device for sampling input data based on a sampling clock, a coding unit for coding based on sample values sampled by the sampling device, and a coding unit for coding by this coding unit. A transmission unit that transmits the signal as a carrier pulse, a reception unit that equalizes the signal received from the transmission path, outputs a sampling clock and an identification signal by performing timing extraction and reproduction, and a decoding unit that decodes the signal reproduced by this reception unit. A modulation / demodulation device including a frequency division unit, a frequency divider that generates a basic clock of a carrier frequency by dividing a sampling clock output from the reception unit, and the encoding unit includes a basic frequency output from the frequency divider. Input a clock to determine whether the sampled value of the sampler has changed within one cycle of the basic clock, and if it does not change, one cycle The value of is output as a state code, and if it changes, the state change code indicating whether the value has changed from one logical value to the other logical value or from the other logical value to one logical value, and A unit for outputting a state change position code indicating whether the change is the first half or the second half of the basic clock, the decoding unit inputs the basic clock output from the frequency divider, and the receiving unit. With respect to the received signal reproduced in step 1, the state code at the time point n (n indicates a time series) and the state change code are equal, and the state change code at the next point n + 1 and the state code at the time point n are not equal. A modulator / demodulator provided with means for establishing self-synchronization based on a rule, determining the status code, the status change code, and the status change position code to decode received data. 5. The decoding unit includes means for detecting that the logic of the received data has changed, and means for detecting that the status code and the status change code are equal in 3 bits after the change point. The modulation / demodulation according to claim 4, further comprising means for determining and decoding the logical value of the received data at the time based on the state change code, the state change position code, and the state code when the code and the state change code are equal. apparatus. 6. The encoding unit and the decoding unit include a shift register therein, and a unit for inputting a sample value of input data and a received signal to the shift register to shift the sample value and the received signal. Modulator / demodulator.